* [PATCH v1] target/loongarch/cpu: Fix cpucfg default value
@ 2022-07-15 6:48 Xiaojuan Yang
2022-07-19 5:35 ` Richard Henderson
2022-07-19 7:02 ` Richard Henderson
0 siblings, 2 replies; 3+ messages in thread
From: Xiaojuan Yang @ 2022-07-15 6:48 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, gaosong, maobibo, mark.cave-ayland, mst,
imammedo, ani, f4bug, peter.maydell
We should config cpucfg[20] to set value for the scache's ways, sets,
and size arguments when loongarch cpu init. However, the old code
wirte 'sets argument' twice, so we change one of them to 'size argument'.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
target/loongarch/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 89ea971cde..4cfce8c9d2 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -406,7 +406,7 @@ static void loongarch_la464_initfn(Object *obj)
data = 0;
data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15);
data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14);
- data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 6);
+ data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6);
env->cpucfg[20] = data;
env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
--
2.31.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v1] target/loongarch/cpu: Fix cpucfg default value
2022-07-15 6:48 [PATCH v1] target/loongarch/cpu: Fix cpucfg default value Xiaojuan Yang
@ 2022-07-19 5:35 ` Richard Henderson
2022-07-19 7:02 ` Richard Henderson
1 sibling, 0 replies; 3+ messages in thread
From: Richard Henderson @ 2022-07-19 5:35 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel
Cc: gaosong, maobibo, mark.cave-ayland, mst, imammedo, ani, f4bug,
peter.maydell
On 7/15/22 12:18, Xiaojuan Yang wrote:
> We should config cpucfg[20] to set value for the scache's ways, sets,
> and size arguments when loongarch cpu init. However, the old code
> wirte 'sets argument' twice, so we change one of them to 'size argument'.
>
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
> ---
> target/loongarch/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 89ea971cde..4cfce8c9d2 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -406,7 +406,7 @@ static void loongarch_la464_initfn(Object *obj)
> data = 0;
> data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15);
> data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14);
> - data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 6);
> + data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6);
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
> env->cpucfg[20] = data;
>
> env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v1] target/loongarch/cpu: Fix cpucfg default value
2022-07-15 6:48 [PATCH v1] target/loongarch/cpu: Fix cpucfg default value Xiaojuan Yang
2022-07-19 5:35 ` Richard Henderson
@ 2022-07-19 7:02 ` Richard Henderson
1 sibling, 0 replies; 3+ messages in thread
From: Richard Henderson @ 2022-07-19 7:02 UTC (permalink / raw)
To: Xiaojuan Yang, qemu-devel
Cc: gaosong, maobibo, mark.cave-ayland, mst, imammedo, ani, f4bug,
peter.maydell
On 7/15/22 12:18, Xiaojuan Yang wrote:
> We should config cpucfg[20] to set value for the scache's ways, sets,
> and size arguments when loongarch cpu init. However, the old code
> wirte 'sets argument' twice, so we change one of them to 'size argument'.
>
> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Queued.
r~
> ---
> target/loongarch/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 89ea971cde..4cfce8c9d2 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -406,7 +406,7 @@ static void loongarch_la464_initfn(Object *obj)
> data = 0;
> data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15);
> data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14);
> - data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 6);
> + data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6);
> env->cpucfg[20] = data;
>
> env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-07-19 7:03 UTC | newest]
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2022-07-19 5:35 ` Richard Henderson
2022-07-19 7:02 ` Richard Henderson
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