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[50.200.230.211]) by smtp.gmail.com with ESMTPSA id i14sm16556133pjh.17.2021.04.05.08.10.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 05 Apr 2021 08:10:38 -0700 (PDT) Subject: Re: [PATCH v1 4/8] target/riscv: Remove the hardcoded MSTATUS_SD macro To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <7efb55362999a5b709ea8e7fa0ea188e740d9c67.1617393702.git.alistair.francis@wdc.com> From: Richard Henderson Message-ID: <81cbeace-c357-1ef3-1a1c-f1b266e66a98@linaro.org> Date: Mon, 5 Apr 2021 08:10:35 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 MIME-Version: 1.0 In-Reply-To: <7efb55362999a5b709ea8e7fa0ea188e740d9c67.1617393702.git.alistair.francis@wdc.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, bmeng.cn@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 4/2/21 1:02 PM, Alistair Francis wrote: > @@ -369,6 +369,9 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) > static void mark_fs_dirty(DisasContext *ctx) > { > TCGv tmp; > + CPUState *cpu = ctx->cs; > + CPURISCVState *env = cpu->env_ptr; > + > if (ctx->mstatus_fs == MSTATUS_FS) { > return; > } > @@ -377,12 +380,24 @@ static void mark_fs_dirty(DisasContext *ctx) > > tmp = tcg_temp_new(); > tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); > - tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); > + if (riscv_cpu_is_32bit(env)) { This is less than ideal, and will be incorrect long term. You should check ctx->misa instead. Eventually you'll need to change riscv_tr_init_disas_context to not just copy ctx->misa from env. At present we flush all translation blocks when misa changes, which works. But you won't want to do that when the hypervisor is 64-bit and the guest is 32-bit. Anyway, I think it would be a good idea to create a helper local to translate, akin to has_ext(). > + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS32_SD); > + } else { > +#if defined(TARGET_RISCV64) > + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS64_SD); > +#endif The ifdefs are ugly. I presume there's some sort of compiler warning here? Does it go away if you cast to target_ulong? How about target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD; tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); r~