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From: Damien Hedde <damien.hedde@greensocs.com>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, pbonzini@redhat.com,
	peter.maydell@linaro.org, edgar.iglesias@xilinx.com,
	mark.burton@greensocs.com, saipava@xilinx.com,
	luc.michel@greensocs.com, alistair@alistair23.me,
	Damien Hedde <damien.hedde@greensocs.com>
Subject: [Qemu-devel] [RFC PATCH 4/6] cadence_uart: add clock/power gating support
Date: Fri, 27 Jul 2018 16:37:23 +0200	[thread overview]
Message-ID: <81e37f79d335d17d8802f127d59f89e263c50136.1532701430.git.damien.hedde@greensocs.com> (raw)
In-Reply-To: <cover.1532701430.git.damien.hedde@greensocs.com>

Only discard input characters when unpowered/unclocked.
As it is a sysbus device, mmio are already disabled when unpowered
or unclocked.

Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
---
 hw/char/cadence_uart.c | 25 ++++++++++++++++++++++++-
 1 file changed, 24 insertions(+), 1 deletion(-)

diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index fbdbd463bb..dd51d9a087 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -335,8 +335,14 @@ static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
 static void uart_receive(void *opaque, const uint8_t *buf, int size)
 {
     CadenceUARTState *s = opaque;
+    DeviceState *dev = DEVICE(s);
     uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
 
+    /* ignore characters if unpowered or unclocked */
+    if (!dev->powered || !dev->clocked) {
+        return;
+    }
+
     if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
         uart_write_rx_fifo(opaque, buf, size);
     }
@@ -348,8 +354,14 @@ static void uart_receive(void *opaque, const uint8_t *buf, int size)
 static void uart_event(void *opaque, int event)
 {
     CadenceUARTState *s = opaque;
+    DeviceState *dev = DEVICE(s);
     uint8_t buf = '\0';
 
+    /* ignore event if we're unpowered or unclocked */
+    if (!dev->powered || !dev->clocked) {
+        return;
+    }
+
     if (event == CHR_EVENT_BREAK) {
         uart_write_rx_fifo(opaque, &buf, 1);
     }
@@ -516,10 +528,19 @@ static int cadence_uart_post_load(void *opaque, int version_id)
     return 0;
 }
 
+static int cadence_uart_pre_load(void *opaque)
+{
+    DeviceState *s = opaque;
+    s->clocked = true;
+    s->powered = true;
+    return 0;
+}
+
 static const VMStateDescription vmstate_cadence_uart = {
     .name = "cadence_uart",
-    .version_id = 2,
+    .version_id = 3,
     .minimum_version_id = 2,
+    .pre_load = cadence_uart_pre_load,
     .post_load = cadence_uart_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
@@ -531,6 +552,8 @@ static const VMStateDescription vmstate_cadence_uart = {
         VMSTATE_UINT32(tx_count, CadenceUARTState),
         VMSTATE_UINT32(rx_wpos, CadenceUARTState),
         VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
+        VMSTATE_BOOL_V(powered, DeviceState, 3),
+        VMSTATE_BOOL_V(clocked, DeviceState, 3),
         VMSTATE_END_OF_LIST()
     }
 };
-- 
2.18.0

  parent reply	other threads:[~2018-07-27 14:37 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-27 14:37 [Qemu-devel] [RFC PATCH 0/6] Clock and power gating support Damien Hedde
2018-07-27 14:37 ` [Qemu-devel] [RFC PATCH 1/6] qdev: add a power and clock " Damien Hedde
     [not found]   ` <994d20ce-5332-b0db-aac0-bc906ef12fdb@amsat.org>
2018-07-31 10:35     ` Damien Hedde
2018-07-27 14:37 ` [Qemu-devel] [RFC PATCH 2/6] qdev: add power/clock gating control on bus tree Damien Hedde
2018-07-27 16:39   ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-08-02 11:07     ` Damien Hedde
2018-07-27 14:37 ` [Qemu-devel] [RFC PATCH 3/6] sysbus: Specialize gating_update to enable/disable memory regions Damien Hedde
2018-07-27 16:43   ` Philippe Mathieu-Daudé
2018-07-27 14:37 ` Damien Hedde [this message]
2018-07-27 17:13   ` [Qemu-devel] [RFC PATCH 4/6] cadence_uart: add clock/power gating support Philippe Mathieu-Daudé
2018-07-27 14:37 ` [Qemu-devel] [RFC PATCH 5/6] zynq_slcr: add uart clock gating and soft reset support Damien Hedde
2018-07-27 14:37 ` [Qemu-devel] [RFC PATCH 6/6] xilinx_zynq: add uart clock gating support Damien Hedde
2018-07-27 14:59 ` [Qemu-devel] [RFC PATCH 0/6] Clock and power " Peter Maydell
2018-07-27 15:12   ` KONRAD Frederic
2018-07-30 13:17     ` Mark Burton

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