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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4395a1aa7bcsm21972115e9.28.2025.02.12.06.58.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Feb 2025 06:58:40 -0800 (PST) Message-ID: <824c0c10-8aba-4778-b653-d0e2eb6115ea@linaro.org> Date: Wed, 12 Feb 2025 15:58:39 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/8] hw/arm/realview: Explicit number of GIC external IRQs To: Peter Maydell Cc: qemu-devel@nongnu.org, "Edgar E. Iglesias" , Rob Herring , qemu-arm@nongnu.org, Alistair Francis , Igor Mitsyanko References: <20250130182441.40480-1-philmd@linaro.org> <20250130182441.40480-4-philmd@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 30/1/25 19:36, Peter Maydell wrote: > On Thu, 30 Jan 2025 at 18:25, Philippe Mathieu-Daudé wrote: >> >> When not specified, Cortex-A9MP configures its GIC with 64 external >> IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts >> configurable"). Add the GIC_EXT_IRQS definition (with a comment) >> to make that explicit. >> >> Except explicitly setting a property value to its same implicit >> value, there is no logical change intended. >> >> Signed-off-by: Philippe Mathieu-Daudé >> --- >> hw/arm/realview.c | 17 +++++++++++++++-- >> 1 file changed, 15 insertions(+), 2 deletions(-) >> >> diff --git a/hw/arm/realview.c b/hw/arm/realview.c >> index 9900a98f3b8..4a62c83506b 100644 >> --- a/hw/arm/realview.c >> +++ b/hw/arm/realview.c >> @@ -35,6 +35,14 @@ >> #define SMP_BOOT_ADDR 0xe0000000 >> #define SMP_BOOTREG_ADDR 0x10000030 >> >> +/* >> + * The Cortex-A9MP may have anything from 0 to 224 external interrupt >> + * IRQ lines (with another 32 internal). We default to 64+32, which >> + * is the number provided by the Cortex-A9MP test chip in the >> + * Realview PBX-A9 and Versatile Express A9 development boards. >> + */ > > On the other hand, this really *is* the Realview PBX-A9 > development board. So we can just say that that's the right > number (and the vexpress is irrelevant, and the range of > settings the CPU itself can have isn't very important either). > > (PS: there's no verb "to explicit" in English (ignoring some > obscure obsolete ones); French "expliciter" => English "to make > explicit"; or you in the case of the subject line here, > "specify explicitly" is probably most natural.) TIL, thanks :)