* [PATCH v5 1/7] trans_rvv.c.inc: mark_vs_dirty() before loads and stores
2024-02-21 2:22 [PATCH v5 0/7] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
@ 2024-02-21 2:22 ` Daniel Henrique Barboza
2024-02-21 2:22 ` [PATCH v5 2/7] trans_rvv.c.inc: remove 'is_store' bool from load/store fns Daniel Henrique Barboza
` (6 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Daniel Henrique Barboza @ 2024-02-21 2:22 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
While discussing a problem with how we're (not) setting vstart_eq_zero
Richard had the following to say w.r.t the conditional mark_vs_dirty()
calls on load/store functions [1]:
"I think it's required to have stores set dirty unconditionally, before
the operation.
Consider a store that traps on the 2nd element, leaving vstart = 2, and
exiting to the main loop via exception. The exception enters the kernel
page fault handler. The kernel may need to fault in the page for the
process, and in the meantime task switch.
If vs dirty is not already set, the kernel won't know to save vector
state on task switch."
Do a mark_vs_dirty() before both loads and stores.
[1] https://lore.kernel.org/qemu-riscv/72c7503b-0f43-44b8-aa82-fbafed2aac0c@linaro.org/
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 23 ++++++++---------------
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 9e101ab434..7a98f1caa6 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -636,11 +636,9 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
- fn(dest, mask, base, tcg_env, desc);
+ mark_vs_dirty(s);
- if (!is_store) {
- mark_vs_dirty(s);
- }
+ fn(dest, mask, base, tcg_env, desc);
gen_set_label(over);
return true;
@@ -797,11 +795,9 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
- fn(dest, mask, base, stride, tcg_env, desc);
+ mark_vs_dirty(s);
- if (!is_store) {
- mark_vs_dirty(s);
- }
+ fn(dest, mask, base, stride, tcg_env, desc);
gen_set_label(over);
return true;
@@ -904,11 +900,9 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
tcg_gen_addi_ptr(index, tcg_env, vreg_ofs(s, vs2));
tcg_gen_addi_ptr(mask, tcg_env, vreg_ofs(s, 0));
- fn(dest, mask, base, index, tcg_env, desc);
+ mark_vs_dirty(s);
- if (!is_store) {
- mark_vs_dirty(s);
- }
+ fn(dest, mask, base, index, tcg_env, desc);
gen_set_label(over);
return true;
@@ -1102,11 +1096,10 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
base = get_gpr(s, rs1, EXT_NONE);
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, vd));
+ mark_vs_dirty(s);
+
fn(dest, base, tcg_env, desc);
- if (!is_store) {
- mark_vs_dirty(s);
- }
gen_set_label(over);
return true;
--
2.43.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v5 2/7] trans_rvv.c.inc: remove 'is_store' bool from load/store fns
2024-02-21 2:22 [PATCH v5 0/7] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
2024-02-21 2:22 ` [PATCH v5 1/7] trans_rvv.c.inc: mark_vs_dirty() before loads and stores Daniel Henrique Barboza
@ 2024-02-21 2:22 ` Daniel Henrique Barboza
2024-02-21 8:57 ` Philippe Mathieu-Daudé
2024-02-21 2:22 ` [PATCH v5 3/7] target/riscv: remove 'over' brconds from vector trans Daniel Henrique Barboza
` (5 subsequent siblings)
7 siblings, 1 reply; 11+ messages in thread
From: Daniel Henrique Barboza @ 2024-02-21 2:22 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
After the 'mark_vs_dirty' changes from the previous patch the 'is_store'
bool is unused in all load/store functions that were changed. Remove it.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 69 ++++++++++++-------------
1 file changed, 34 insertions(+), 35 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 7a98f1caa6..15ccebf3fc 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -609,8 +609,7 @@ typedef void gen_helper_ldst_us(TCGv_ptr, TCGv_ptr, TCGv,
TCGv_env, TCGv_i32);
static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
- gen_helper_ldst_us *fn, DisasContext *s,
- bool is_store)
+ gen_helper_ldst_us *fn, DisasContext *s)
{
TCGv_ptr dest, mask;
TCGv base;
@@ -673,7 +672,7 @@ static bool ld_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VMA, s->vma);
- return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
+ return ldst_us_trans(a->rd, a->rs1, data, fn, s);
}
static bool ld_us_check(DisasContext *s, arg_r2nfvm* a, uint8_t eew)
@@ -710,7 +709,7 @@ static bool st_us_op(DisasContext *s, arg_r2nfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
+ return ldst_us_trans(a->rd, a->rs1, data, fn, s);
}
static bool st_us_check(DisasContext *s, arg_r2nfvm* a, uint8_t eew)
@@ -739,7 +738,7 @@ static bool ld_us_mask_op(DisasContext *s, arg_vlm_v *a, uint8_t eew)
/* Mask destination register are always tail-agnostic */
data = FIELD_DP32(data, VDATA, VTA, s->cfg_vta_all_1s);
data = FIELD_DP32(data, VDATA, VMA, s->vma);
- return ldst_us_trans(a->rd, a->rs1, data, fn, s, false);
+ return ldst_us_trans(a->rd, a->rs1, data, fn, s);
}
static bool ld_us_mask_check(DisasContext *s, arg_vlm_v *a, uint8_t eew)
@@ -756,7 +755,7 @@ static bool st_us_mask_op(DisasContext *s, arg_vsm_v *a, uint8_t eew)
/* EMUL = 1, NFIELDS = 1 */
data = FIELD_DP32(data, VDATA, LMUL, 0);
data = FIELD_DP32(data, VDATA, NF, 1);
- return ldst_us_trans(a->rd, a->rs1, data, fn, s, true);
+ return ldst_us_trans(a->rd, a->rs1, data, fn, s);
}
static bool st_us_mask_check(DisasContext *s, arg_vsm_v *a, uint8_t eew)
@@ -776,7 +775,7 @@ typedef void gen_helper_ldst_stride(TCGv_ptr, TCGv_ptr, TCGv,
static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
uint32_t data, gen_helper_ldst_stride *fn,
- DisasContext *s, bool is_store)
+ DisasContext *s)
{
TCGv_ptr dest, mask;
TCGv base, stride;
@@ -823,7 +822,7 @@ static bool ld_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VMA, s->vma);
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool ld_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@@ -857,7 +856,7 @@ static bool st_stride_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
return false;
}
- return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
+ return ldst_stride_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool st_stride_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@@ -880,7 +879,7 @@ typedef void gen_helper_ldst_index(TCGv_ptr, TCGv_ptr, TCGv,
static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
uint32_t data, gen_helper_ldst_index *fn,
- DisasContext *s, bool is_store)
+ DisasContext *s)
{
TCGv_ptr dest, mask, index;
TCGv base;
@@ -947,7 +946,7 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, NF, a->nf);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
data = FIELD_DP32(data, VDATA, VMA, s->vma);
- return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, false);
+ return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool ld_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@@ -999,7 +998,7 @@ static bool st_index_op(DisasContext *s, arg_rnfvm *a, uint8_t eew)
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, emul);
data = FIELD_DP32(data, VDATA, NF, a->nf);
- return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s, true);
+ return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
}
static bool st_index_check(DisasContext *s, arg_rnfvm* a, uint8_t eew)
@@ -1078,7 +1077,7 @@ typedef void gen_helper_ldst_whole(TCGv_ptr, TCGv, TCGv_env, TCGv_i32);
static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
uint32_t width, gen_helper_ldst_whole *fn,
- DisasContext *s, bool is_store)
+ DisasContext *s)
{
uint32_t evl = s->cfg_ptr->vlenb * nf / width;
TCGLabel *over = gen_new_label();
@@ -1109,42 +1108,42 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
* load and store whole register instructions ignore vtype and vl setting.
* Thus, we don't need to check vill bit. (Section 7.9)
*/
-#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH, IS_STORE) \
+#define GEN_LDST_WHOLE_TRANS(NAME, ARG_NF, WIDTH) \
static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
{ \
if (require_rvv(s) && \
QEMU_IS_ALIGNED(a->rd, ARG_NF)) { \
return ldst_whole_trans(a->rd, a->rs1, ARG_NF, WIDTH, \
- gen_helper_##NAME, s, IS_STORE); \
+ gen_helper_##NAME, s); \
} \
return false; \
}
-GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1, false)
-GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2, false)
-GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4, false)
-GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8, false)
-GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1, false)
-GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2, false)
-GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4, false)
-GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8, false)
-GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1, false)
-GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2, false)
-GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4, false)
-GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8, false)
-GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1, false)
-GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2, false)
-GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4, false)
-GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8, false)
+GEN_LDST_WHOLE_TRANS(vl1re8_v, 1, 1)
+GEN_LDST_WHOLE_TRANS(vl1re16_v, 1, 2)
+GEN_LDST_WHOLE_TRANS(vl1re32_v, 1, 4)
+GEN_LDST_WHOLE_TRANS(vl1re64_v, 1, 8)
+GEN_LDST_WHOLE_TRANS(vl2re8_v, 2, 1)
+GEN_LDST_WHOLE_TRANS(vl2re16_v, 2, 2)
+GEN_LDST_WHOLE_TRANS(vl2re32_v, 2, 4)
+GEN_LDST_WHOLE_TRANS(vl2re64_v, 2, 8)
+GEN_LDST_WHOLE_TRANS(vl4re8_v, 4, 1)
+GEN_LDST_WHOLE_TRANS(vl4re16_v, 4, 2)
+GEN_LDST_WHOLE_TRANS(vl4re32_v, 4, 4)
+GEN_LDST_WHOLE_TRANS(vl4re64_v, 4, 8)
+GEN_LDST_WHOLE_TRANS(vl8re8_v, 8, 1)
+GEN_LDST_WHOLE_TRANS(vl8re16_v, 8, 2)
+GEN_LDST_WHOLE_TRANS(vl8re32_v, 8, 4)
+GEN_LDST_WHOLE_TRANS(vl8re64_v, 8, 8)
/*
* The vector whole register store instructions are encoded similar to
* unmasked unit-stride store of elements with EEW=8.
*/
-GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1, true)
-GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1, true)
-GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1, true)
-GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1, true)
+GEN_LDST_WHOLE_TRANS(vs1r_v, 1, 1)
+GEN_LDST_WHOLE_TRANS(vs2r_v, 2, 1)
+GEN_LDST_WHOLE_TRANS(vs4r_v, 4, 1)
+GEN_LDST_WHOLE_TRANS(vs8r_v, 8, 1)
/*
*** Vector Integer Arithmetic Instructions
--
2.43.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v5 2/7] trans_rvv.c.inc: remove 'is_store' bool from load/store fns
2024-02-21 2:22 ` [PATCH v5 2/7] trans_rvv.c.inc: remove 'is_store' bool from load/store fns Daniel Henrique Barboza
@ 2024-02-21 8:57 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 11+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-02-21 8:57 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou
On 21/2/24 03:22, Daniel Henrique Barboza wrote:
> After the 'mark_vs_dirty' changes from the previous patch the 'is_store'
> bool is unused in all load/store functions that were changed. Remove it.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 69 ++++++++++++-------------
> 1 file changed, 34 insertions(+), 35 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 3/7] target/riscv: remove 'over' brconds from vector trans
2024-02-21 2:22 [PATCH v5 0/7] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
2024-02-21 2:22 ` [PATCH v5 1/7] trans_rvv.c.inc: mark_vs_dirty() before loads and stores Daniel Henrique Barboza
2024-02-21 2:22 ` [PATCH v5 2/7] trans_rvv.c.inc: remove 'is_store' bool from load/store fns Daniel Henrique Barboza
@ 2024-02-21 2:22 ` Daniel Henrique Barboza
2024-02-21 2:22 ` [PATCH v5 4/7] target/riscv/translate.c: remove 'cpu_vstart' global Daniel Henrique Barboza
` (4 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Daniel Henrique Barboza @ 2024-02-21 2:22 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
Most of the vector translations has this following pattern at the start:
TCGLabel *over = gen_new_label();
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
And then right at the end:
gen_set_label(over);
return true;
This means that if vstart >= vl we'll not set vstart = 0 at the end of
the insns - this is done inside the helper that is being skipped. The
reason why this pattern hasn't been a bigger problem is because the
conditional vstart >= vl is very rare.
Checking all the helpers in vector_helper.c we see all of them with a
pattern like this:
for (i = env->vstart; i < vl; i++) {
(...)
}
env->vstart = 0;
Thus they can handle vstart >= vl case gracefully, with the benefit of
setting env->vstart = 0 during the process.
Remove all 'over' conditionals and let the helper set env->vstart = 0
every time.
While we're at it, remove the (vl == 0) brconds from trans_rvbf16.c.inc
too since they're unneeded.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 12 ---
target/riscv/insn_trans/trans_rvv.c.inc | 117 ---------------------
target/riscv/insn_trans/trans_rvvk.c.inc | 18 ----
3 files changed, 147 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc
index 8ee99df3f3..a842e76a6b 100644
--- a/target/riscv/insn_trans/trans_rvbf16.c.inc
+++ b/target/riscv/insn_trans/trans_rvbf16.c.inc
@@ -71,11 +71,8 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
if (opfv_narrow_check(ctx, a) && (ctx->sew == MO_16)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
@@ -87,7 +84,6 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
ctx->cfg_ptr->vlenb, data,
gen_helper_vfncvtbf16_f_f_w);
mark_vs_dirty(ctx);
- gen_set_label(over);
return true;
}
return false;
@@ -100,11 +96,8 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
if (opfv_widen_check(ctx, a) && (ctx->sew == MO_16)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
@@ -116,7 +109,6 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
ctx->cfg_ptr->vlenb, data,
gen_helper_vfwcvtbf16_f_f_v);
mark_vs_dirty(ctx);
- gen_set_label(over);
return true;
}
return false;
@@ -130,11 +122,8 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
if (require_rvv(ctx) && vext_check_isa_ill(ctx) && (ctx->sew == MO_16) &&
vext_check_dss(ctx, a->rd, a->rs1, a->rs2, a->vm)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
gen_set_rm_chkfrm(ctx, RISCV_FRM_DYN);
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, ctx->lmul);
@@ -147,7 +136,6 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
ctx->cfg_ptr->vlenb, data,
gen_helper_vfwmaccbf16_vv);
mark_vs_dirty(ctx);
- gen_set_label(over);
return true;
}
return false;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 15ccebf3fc..58299d9bb8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -615,9 +615,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
TCGv base;
TCGv_i32 desc;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
base = get_gpr(s, rs1, EXT_NONE);
@@ -639,7 +636,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
fn(dest, mask, base, tcg_env, desc);
- gen_set_label(over);
return true;
}
@@ -781,9 +777,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
TCGv base, stride;
TCGv_i32 desc;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
base = get_gpr(s, rs1, EXT_NONE);
@@ -798,7 +791,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
fn(dest, mask, base, stride, tcg_env, desc);
- gen_set_label(over);
return true;
}
@@ -885,9 +877,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
TCGv base;
TCGv_i32 desc;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
index = tcg_temp_new_ptr();
@@ -903,7 +892,6 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
fn(dest, mask, base, index, tcg_env, desc);
- gen_set_label(over);
return true;
}
@@ -1023,9 +1011,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
TCGv base;
TCGv_i32 desc;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
base = get_gpr(s, rs1, EXT_NONE);
@@ -1038,7 +1023,6 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
fn(dest, mask, base, tcg_env, desc);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
@@ -1079,10 +1063,6 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
uint32_t width, gen_helper_ldst_whole *fn,
DisasContext *s)
{
- uint32_t evl = s->cfg_ptr->vlenb * nf / width;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
-
TCGv_ptr dest;
TCGv base;
TCGv_i32 desc;
@@ -1099,8 +1079,6 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
fn(dest, base, tcg_env, desc);
- gen_set_label(over);
-
return true;
}
@@ -1174,10 +1152,6 @@ static inline bool
do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
gen_helper_gvec_4_ptr *fn)
{
- TCGLabel *over = gen_new_label();
-
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-
if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
gvec_fn(s->sew, vreg_ofs(s, a->rd),
vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1),
@@ -1195,7 +1169,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
s->cfg_ptr->vlenb, data, fn);
}
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
@@ -1227,9 +1200,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
TCGv_i32 desc;
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
@@ -1250,7 +1220,6 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
fn(dest, mask, src1, src2, tcg_env, desc);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
@@ -1389,9 +1358,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
TCGv_i32 desc;
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
@@ -1412,7 +1378,6 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
fn(dest, mask, src1, src2, tcg_env, desc);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
@@ -1474,8 +1439,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
{
if (checkfn(s, a)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -1488,7 +1451,6 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
s->cfg_ptr->vlenb,
data, fn);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -1550,8 +1512,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
{
if (opiwv_widen_check(s, a)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -1563,7 +1523,6 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fn);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -1622,8 +1581,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
gen_helper_gvec_4_ptr *fn, DisasContext *s)
{
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -1634,7 +1591,6 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fn);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
@@ -1813,8 +1769,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_h, \
gen_helper_##NAME##_w, \
}; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -1827,7 +1781,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
s->cfg_ptr->vlenb, data, \
fns[s->sew]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -2024,14 +1977,11 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
};
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data,
fns[s->sew]);
- gen_set_label(over);
}
mark_vs_dirty(s);
return true;
@@ -2047,8 +1997,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
/* vmv.v.x has rs2 = 0 and vm = 1 */
vext_check_ss(s, a->rd, 0, 1)) {
TCGv s1;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
s1 = get_gpr(s, a->rs1, EXT_SIGN);
@@ -2081,7 +2029,6 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
}
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -2108,8 +2055,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
gen_helper_vmv_v_x_b, gen_helper_vmv_v_x_h,
gen_helper_vmv_v_x_w, gen_helper_vmv_v_x_d,
};
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
s1 = tcg_constant_i64(simm);
dest = tcg_temp_new_ptr();
@@ -2119,7 +2064,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
fns[s->sew](dest, s1, tcg_env, desc);
mark_vs_dirty(s);
- gen_set_label(over);
}
return true;
}
@@ -2254,9 +2198,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_w, \
gen_helper_##NAME##_d, \
}; \
- TCGLabel *over = gen_new_label(); \
gen_set_rm(s, RISCV_FRM_DYN); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -2271,7 +2213,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -2289,9 +2230,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
TCGv_i32 desc;
TCGv_i64 t1;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
-
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
src2 = tcg_temp_new_ptr();
@@ -2309,7 +2247,6 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
fn(dest, mask, t1, src2, tcg_env, desc);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
@@ -2372,9 +2309,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
static gen_helper_gvec_4_ptr * const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- TCGLabel *over = gen_new_label(); \
gen_set_rm(s, RISCV_FRM_DYN); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);\
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -2387,7 +2322,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -2446,9 +2380,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
static gen_helper_gvec_4_ptr * const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
}; \
- TCGLabel *over = gen_new_label(); \
gen_set_rm(s, RISCV_FRM_DYN); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -2461,7 +2393,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -2563,9 +2494,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
{
if (checkfn(s, a)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
gen_set_rm_chkfrm(s, rm);
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -2576,7 +2505,6 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fn);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -2675,8 +2603,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
gen_helper_vmv_v_x_w,
gen_helper_vmv_v_x_d,
};
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
t1 = tcg_temp_new_i64();
/* NaN-box f[rs1] */
@@ -2690,7 +2616,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
fns[s->sew - 1](dest, t1, tcg_env, desc);
mark_vs_dirty(s);
- gen_set_label(over);
}
return true;
}
@@ -2752,9 +2677,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##HELPER##_h, \
gen_helper_##HELPER##_w, \
}; \
- TCGLabel *over = gen_new_label(); \
gen_set_rm_chkfrm(s, FRM); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -2766,7 +2689,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -2803,9 +2725,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##NAME##_h, \
gen_helper_##NAME##_w, \
}; \
- TCGLabel *over = gen_new_label(); \
gen_set_rm(s, RISCV_FRM_DYN); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -2817,7 +2737,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, data, \
fns[s->sew]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -2870,9 +2789,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##HELPER##_h, \
gen_helper_##HELPER##_w, \
}; \
- TCGLabel *over = gen_new_label(); \
gen_set_rm_chkfrm(s, FRM); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -2884,7 +2801,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -2919,9 +2835,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
gen_helper_##HELPER##_h, \
gen_helper_##HELPER##_w, \
}; \
- TCGLabel *over = gen_new_label(); \
gen_set_rm_chkfrm(s, FRM); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -2933,7 +2847,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, data, \
fns[s->sew]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -3010,8 +2923,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
vext_check_isa_ill(s)) { \
uint32_t data = 0; \
gen_helper_gvec_4_ptr *fn = gen_helper_##NAME; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = \
@@ -3022,7 +2933,6 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, fn); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -3110,8 +3020,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->vstart_eq_zero) { \
uint32_t data = 0; \
gen_helper_gvec_3_ptr *fn = gen_helper_##NAME; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -3124,7 +3032,6 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, \
data, fn); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -3150,8 +3057,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
require_align(a->rd, s->lmul) &&
s->vstart_eq_zero) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -3166,7 +3071,6 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fns[s->sew]);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -3180,8 +3084,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
require_align(a->rd, s->lmul) &&
require_vm(a->vm, a->rd)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
@@ -3196,7 +3098,6 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
s->cfg_ptr->vlenb,
data, fns[s->sew]);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -3365,9 +3266,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
/* This instruction ignores LMUL and vector register groups */
TCGv_i64 t1;
TCGv s1;
- TCGLabel *over = gen_new_label();
-
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
t1 = tcg_temp_new_i64();
@@ -3379,7 +3277,6 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
tcg_gen_ext_tl_i64(t1, s1);
vec_element_storei(s, a->rd, 0, t1);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -3421,10 +3318,6 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
/* The instructions ignore LMUL and vector register group. */
TCGv_i64 t1;
- TCGLabel *over = gen_new_label();
-
- /* if vstart >= vl, skip vector register write back */
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
/* NaN-box f[rs1] */
t1 = tcg_temp_new_i64();
@@ -3432,7 +3325,6 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
vec_element_storei(s, a->rd, 0, t1);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -3603,8 +3495,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
gen_helper_vcompress_vm_b, gen_helper_vcompress_vm_h,
gen_helper_vcompress_vm_w, gen_helper_vcompress_vm_d,
};
- TCGLabel *over = gen_new_label();
- tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
@@ -3614,7 +3504,6 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
s->cfg_ptr->vlenb, data,
fns[s->sew]);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -3637,12 +3526,9 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
vreg_ofs(s, a->rs2), maxsz, maxsz); \
mark_vs_dirty(s); \
} else { \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
mark_vs_dirty(s); \
- gen_set_label(over); \
} \
return true; \
} \
@@ -3671,8 +3557,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
{
uint32_t data = 0;
gen_helper_gvec_3_ptr *fn;
- TCGLabel *over = gen_new_label();
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
static gen_helper_gvec_3_ptr * const fns[6][4] = {
{
@@ -3717,7 +3601,6 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
s->cfg_ptr->vlenb, data, fn);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
index a5cdd1b67f..6d640e4596 100644
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
@@ -164,8 +164,6 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
gen_helper_##NAME##_w, \
gen_helper_##NAME##_d, \
}; \
- TCGLabel *over = gen_new_label(); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
@@ -177,7 +175,6 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, \
data, fns[s->sew]); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -249,14 +246,12 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
TCGv_ptr rd_v, rs2_v; \
TCGv_i32 desc, egs; \
uint32_t data = 0; \
- TCGLabel *over = gen_new_label(); \
\
if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
/* save opcode for unwinding in case we throw an exception */ \
decode_save_opc(s); \
egs = tcg_constant_i32(EGS); \
gen_helper_egs_check(egs, tcg_env); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
} \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -272,7 +267,6 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
gen_helper_##NAME(rd_v, rs2_v, tcg_env, desc); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -325,14 +319,12 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
TCGv_ptr rd_v, rs2_v; \
TCGv_i32 uimm_v, desc, egs; \
uint32_t data = 0; \
- TCGLabel *over = gen_new_label(); \
\
if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
/* save opcode for unwinding in case we throw an exception */ \
decode_save_opc(s); \
egs = tcg_constant_i32(EGS); \
gen_helper_egs_check(egs, tcg_env); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
} \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -350,7 +342,6 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
gen_helper_##NAME(rd_v, rs2_v, uimm_v, tcg_env, desc); \
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -394,7 +385,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
{ \
if (CHECK(s, a)) { \
uint32_t data = 0; \
- TCGLabel *over = gen_new_label(); \
TCGv_i32 egs; \
\
if (!s->vstart_eq_zero || !s->vl_eq_vlmax) { \
@@ -402,7 +392,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
decode_save_opc(s); \
egs = tcg_constant_i32(EGS); \
gen_helper_egs_check(egs, tcg_env); \
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
} \
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
@@ -417,7 +406,6 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
data, gen_helper_##NAME); \
\
mark_vs_dirty(s); \
- gen_set_label(over); \
return true; \
} \
return false; \
@@ -448,7 +436,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
{
if (vsha_check(s, a)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
TCGv_i32 egs;
if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
@@ -456,7 +443,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
decode_save_opc(s);
egs = tcg_constant_i32(ZVKNH_EGS);
gen_helper_egs_check(egs, tcg_env);
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
}
data = FIELD_DP32(data, VDATA, VM, a->vm);
@@ -472,7 +458,6 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
@@ -482,7 +467,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
{
if (vsha_check(s, a)) {
uint32_t data = 0;
- TCGLabel *over = gen_new_label();
TCGv_i32 egs;
if (!s->vstart_eq_zero || !s->vl_eq_vlmax) {
@@ -490,7 +474,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
decode_save_opc(s);
egs = tcg_constant_i32(ZVKNH_EGS);
gen_helper_egs_check(egs, tcg_env);
- tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
}
data = FIELD_DP32(data, VDATA, VM, a->vm);
@@ -506,7 +489,6 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv);
mark_vs_dirty(s);
- gen_set_label(over);
return true;
}
return false;
--
2.43.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v5 4/7] target/riscv/translate.c: remove 'cpu_vstart' global
2024-02-21 2:22 [PATCH v5 0/7] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
` (2 preceding siblings ...)
2024-02-21 2:22 ` [PATCH v5 3/7] target/riscv: remove 'over' brconds from vector trans Daniel Henrique Barboza
@ 2024-02-21 2:22 ` Daniel Henrique Barboza
2024-02-21 2:41 ` Richard Henderson
2024-02-21 2:22 ` [PATCH v5 5/7] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX() Daniel Henrique Barboza
` (3 subsequent siblings)
7 siblings, 1 reply; 11+ messages in thread
From: Daniel Henrique Barboza @ 2024-02-21 2:22 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
The global is unused after recent changes.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 177418b2b9..f2f0593830 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -38,7 +38,7 @@
#undef HELPER_H
/* global register indices */
-static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
+static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl;
static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
static TCGv load_res;
static TCGv load_val;
@@ -1321,8 +1321,6 @@ void riscv_translate_init(void)
cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc");
cpu_vl = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "vl");
- cpu_vstart = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vstart),
- "vstart");
load_res = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_res),
"load_res");
load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val),
--
2.43.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v5 4/7] target/riscv/translate.c: remove 'cpu_vstart' global
2024-02-21 2:22 ` [PATCH v5 4/7] target/riscv/translate.c: remove 'cpu_vstart' global Daniel Henrique Barboza
@ 2024-02-21 2:41 ` Richard Henderson
0 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2024-02-21 2:41 UTC (permalink / raw)
To: Daniel Henrique Barboza, qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, max.chou
On 2/20/24 16:22, Daniel Henrique Barboza wrote:
> The global is unused after recent changes.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/translate.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Does this leave exactly one use of cpu_vl, in do_vsetvl()?
If so, it would be worth removing that too, replacing the single use with an explicit load
from env.
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 5/7] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
2024-02-21 2:22 [PATCH v5 0/7] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
` (3 preceding siblings ...)
2024-02-21 2:22 ` [PATCH v5 4/7] target/riscv/translate.c: remove 'cpu_vstart' global Daniel Henrique Barboza
@ 2024-02-21 2:22 ` Daniel Henrique Barboza
2024-02-21 2:22 ` [PATCH v5 6/7] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls Daniel Henrique Barboza
` (2 subsequent siblings)
7 siblings, 0 replies; 11+ messages in thread
From: Daniel Henrique Barboza @ 2024-02-21 2:22 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
The helper isn't setting env->vstart = 0 after its execution, as it is
expected from every vector instruction that completes successfully.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/vector_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 84cec73eb2..cc7290a1bb 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4782,6 +4782,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \
} \
*((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \
} \
+ env->vstart = 0; \
/* set tail elements to 1s */ \
vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); \
}
--
2.43.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v5 6/7] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
2024-02-21 2:22 [PATCH v5 0/7] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
` (4 preceding siblings ...)
2024-02-21 2:22 ` [PATCH v5 5/7] target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX() Daniel Henrique Barboza
@ 2024-02-21 2:22 ` Daniel Henrique Barboza
2024-02-21 2:22 ` [PATCH v5 7/7] target/riscv: Clear vstart_qe_zero flag Daniel Henrique Barboza
2024-02-21 21:24 ` [PATCH v5 0/7] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
7 siblings, 0 replies; 11+ messages in thread
From: Daniel Henrique Barboza @ 2024-02-21 2:22 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Daniel Henrique Barboza
trans_vmv_v_i , trans_vfmv_v_f and the trans_##NAME macro from
GEN_VMV_WHOLE_TRANS() are calling mark_vs_dirty() in both branches of
their 'ifs'. conditionals.
Call it just once in the end like other functions are doing.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 58299d9bb8..8c9a0246ef 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2044,7 +2044,6 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
if (s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
tcg_gen_gvec_dup_imm(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), simm);
- mark_vs_dirty(s);
} else {
TCGv_i32 desc;
TCGv_i64 s1;
@@ -2062,9 +2061,8 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
s->cfg_ptr->vlenb, data));
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
fns[s->sew](dest, s1, tcg_env, desc);
-
- mark_vs_dirty(s);
}
+ mark_vs_dirty(s);
return true;
}
return false;
@@ -2591,7 +2589,6 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), t1);
- mark_vs_dirty(s);
} else {
TCGv_ptr dest;
TCGv_i32 desc;
@@ -2614,9 +2611,8 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
fns[s->sew - 1](dest, t1, tcg_env, desc);
-
- mark_vs_dirty(s);
}
+ mark_vs_dirty(s);
return true;
}
return false;
@@ -3524,12 +3520,11 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
if (s->vstart_eq_zero) { \
tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), \
vreg_ofs(s, a->rs2), maxsz, maxsz); \
- mark_vs_dirty(s); \
} else { \
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
- mark_vs_dirty(s); \
} \
+ mark_vs_dirty(s); \
return true; \
} \
return false; \
--
2.43.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v5 7/7] target/riscv: Clear vstart_qe_zero flag
2024-02-21 2:22 [PATCH v5 0/7] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
` (5 preceding siblings ...)
2024-02-21 2:22 ` [PATCH v5 6/7] trans_rvv.c.inc: remove redundant mark_vs_dirty() calls Daniel Henrique Barboza
@ 2024-02-21 2:22 ` Daniel Henrique Barboza
2024-02-21 21:24 ` [PATCH v5 0/7] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
7 siblings, 0 replies; 11+ messages in thread
From: Daniel Henrique Barboza @ 2024-02-21 2:22 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou, Ivan Klokov,
Daniel Henrique Barboza
From: Ivan Klokov <ivan.klokov@syntacore.com>
The vstart_qe_zero flag is set at the beginning of the translation
phase from the env->vstart variable. During the execution phase all
functions will set env->vstart = 0 after a successful execution,
but the vstart_eq_zero flag remains the same as at the start of the
block. This will wrongly cause SIGILLs in translations that requires
env->vstart = 0 and might be reading vstart_eq_zero = false.
This patch adds a new finalize_rvv_inst() helper that is called at the
end of each vector instruction that will both update vstart_eq_zero and
do a mark_vs_dirty().
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1976
Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvbf16.c.inc | 6 +-
target/riscv/insn_trans/trans_rvv.c.inc | 78 ++++++++++++----------
target/riscv/insn_trans/trans_rvvk.c.inc | 12 ++--
target/riscv/translate.c | 6 ++
4 files changed, 56 insertions(+), 46 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvbf16.c.inc b/target/riscv/insn_trans/trans_rvbf16.c.inc
index a842e76a6b..0a9cd1ec31 100644
--- a/target/riscv/insn_trans/trans_rvbf16.c.inc
+++ b/target/riscv/insn_trans/trans_rvbf16.c.inc
@@ -83,7 +83,7 @@ static bool trans_vfncvtbf16_f_f_w(DisasContext *ctx, arg_vfncvtbf16_f_f_w *a)
ctx->cfg_ptr->vlenb,
ctx->cfg_ptr->vlenb, data,
gen_helper_vfncvtbf16_f_f_w);
- mark_vs_dirty(ctx);
+ finalize_rvv_inst(ctx);
return true;
}
return false;
@@ -108,7 +108,7 @@ static bool trans_vfwcvtbf16_f_f_v(DisasContext *ctx, arg_vfwcvtbf16_f_f_v *a)
ctx->cfg_ptr->vlenb,
ctx->cfg_ptr->vlenb, data,
gen_helper_vfwcvtbf16_f_f_v);
- mark_vs_dirty(ctx);
+ finalize_rvv_inst(ctx);
return true;
}
return false;
@@ -135,7 +135,7 @@ static bool trans_vfwmaccbf16_vv(DisasContext *ctx, arg_vfwmaccbf16_vv *a)
ctx->cfg_ptr->vlenb,
ctx->cfg_ptr->vlenb, data,
gen_helper_vfwmaccbf16_vv);
- mark_vs_dirty(ctx);
+ finalize_rvv_inst(ctx);
return true;
}
return false;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 8c9a0246ef..069ddfd477 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -167,7 +167,7 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
gen_helper_vsetvl(dst, tcg_env, s1, s2);
gen_set_gpr(s, rd, dst);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
gen_update_pc(s, s->cur_insn_len);
lookup_and_goto_ptr(s);
@@ -187,7 +187,7 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
gen_helper_vsetvl(dst, tcg_env, s1, s2);
gen_set_gpr(s, rd, dst);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
gen_update_pc(s, s->cur_insn_len);
lookup_and_goto_ptr(s);
s->base.is_jmp = DISAS_NORETURN;
@@ -636,6 +636,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, uint32_t data,
fn(dest, mask, base, tcg_env, desc);
+ finalize_rvv_inst(s);
return true;
}
@@ -791,6 +792,7 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1, uint32_t rs2,
fn(dest, mask, base, stride, tcg_env, desc);
+ finalize_rvv_inst(s);
return true;
}
@@ -892,6 +894,7 @@ static bool ldst_index_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
fn(dest, mask, base, index, tcg_env, desc);
+ finalize_rvv_inst(s);
return true;
}
@@ -1022,7 +1025,7 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
fn(dest, mask, base, tcg_env, desc);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
@@ -1079,6 +1082,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
fn(dest, base, tcg_env, desc);
+ finalize_rvv_inst(s);
return true;
}
@@ -1168,7 +1172,7 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fn);
}
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
@@ -1219,7 +1223,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1, uint32_t vs2, uint32_t vm,
fn(dest, mask, src1, src2, tcg_env, desc);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
@@ -1244,7 +1248,7 @@ do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
src1, MAXSZ(s), MAXSZ(s));
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
@@ -1377,7 +1381,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm, uint32_t vs2, uint32_t vm,
fn(dest, mask, src1, src2, tcg_env, desc);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
@@ -1391,7 +1395,7 @@ do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s));
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s, imm_mode);
@@ -1450,7 +1454,7 @@ static bool do_opivv_widen(DisasContext *s, arg_rmrr *a,
tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb,
data, fn);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -1522,7 +1526,7 @@ static bool do_opiwv_widen(DisasContext *s, arg_rmrr *a,
vreg_ofs(s, a->rs2),
tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fn);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -1590,7 +1594,7 @@ static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1),
vreg_ofs(s, vs2), tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fn);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
@@ -1723,7 +1727,7 @@ do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
src1, MAXSZ(s), MAXSZ(s));
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fn, s);
@@ -1780,7 +1784,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, \
fns[s->sew]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -1983,7 +1987,7 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
s->cfg_ptr->vlenb, data,
fns[s->sew]);
}
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -2028,7 +2032,7 @@ static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
fns[s->sew](dest, s1_i64, tcg_env, desc);
}
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -2062,7 +2066,7 @@ static bool trans_vmv_v_i(DisasContext *s, arg_vmv_v_i *a)
tcg_gen_addi_ptr(dest, tcg_env, vreg_ofs(s, a->rd));
fns[s->sew](dest, s1, tcg_env, desc);
}
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -2210,7 +2214,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -2244,7 +2248,7 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1, uint32_t vs2,
fn(dest, mask, t1, src2, tcg_env, desc);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
@@ -2319,7 +2323,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -2390,7 +2394,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -2502,7 +2506,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
vreg_ofs(s, a->rs2), tcg_env,
s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fn);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -2612,7 +2616,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
fns[s->sew - 1](dest, t1, tcg_env, desc);
}
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -2684,7 +2688,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -2732,7 +2736,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, \
fns[s->sew]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -2796,7 +2800,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, \
fns[s->sew - 1]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -2842,7 +2846,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, \
fns[s->sew]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -2928,7 +2932,7 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \
vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, data, fn); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -3027,7 +3031,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
tcg_env, s->cfg_ptr->vlenb, \
s->cfg_ptr->vlenb, \
data, fn); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -3066,7 +3070,7 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
vreg_ofs(s, a->rs2), tcg_env,
s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fns[s->sew]);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -3093,7 +3097,7 @@ static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb,
data, fns[s->sew]);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -3272,7 +3276,7 @@ static bool trans_vmv_s_x(DisasContext *s, arg_vmv_s_x *a)
s1 = get_gpr(s, a->rs1, EXT_NONE);
tcg_gen_ext_tl_i64(t1, s1);
vec_element_storei(s, a->rd, 0, t1);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -3320,7 +3324,7 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_s_f *a)
do_nanbox(s, t1, cpu_fpr[a->rs1]);
vec_element_storei(s, a->rd, 0, t1);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -3426,7 +3430,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), dest);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
} else {
static gen_helper_opivx * const fns[4] = {
gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
@@ -3454,7 +3458,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
endian_ofs(s, a->rs2, a->rs1),
MAXSZ(s), MAXSZ(s));
}
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
} else {
static gen_helper_opivx * const fns[4] = {
gen_helper_vrgather_vx_b, gen_helper_vrgather_vx_h,
@@ -3499,7 +3503,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
tcg_env, s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data,
fns[s->sew]);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -3524,7 +3528,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
tcg_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
} \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -3595,7 +3599,7 @@ static bool int_ext_op(DisasContext *s, arg_rmr *a, uint8_t seq)
s->cfg_ptr->vlenb,
s->cfg_ptr->vlenb, data, fn);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc
index 6d640e4596..ae1f40174a 100644
--- a/target/riscv/insn_trans/trans_rvvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvvk.c.inc
@@ -174,7 +174,7 @@ GEN_OPIVX_GVEC_TRANS_CHECK(vandn_vx, andcs, zvkb_vx_check)
vreg_ofs(s, a->rs2), tcg_env, \
s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, \
data, fns[s->sew]); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -266,7 +266,7 @@ GEN_OPIVI_WIDEN_TRANS(vwsll_vi, IMM_ZX, vwsll_vx, vwsll_vx_check)
tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd)); \
tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
gen_helper_##NAME(rd_v, rs2_v, tcg_env, desc); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -341,7 +341,7 @@ GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs, ZVKNED_EGS)
tcg_gen_addi_ptr(rd_v, tcg_env, vreg_ofs(s, a->rd)); \
tcg_gen_addi_ptr(rs2_v, tcg_env, vreg_ofs(s, a->rs2)); \
gen_helper_##NAME(rd_v, rs2_v, uimm_v, tcg_env, desc); \
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -405,7 +405,7 @@ GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check, ZVKNED_EGS)
s->cfg_ptr->vlenb, s->cfg_ptr->vlenb, \
data, gen_helper_##NAME); \
\
- mark_vs_dirty(s); \
+ finalize_rvv_inst(s); \
return true; \
} \
return false; \
@@ -457,7 +457,7 @@ static bool trans_vsha2cl_vv(DisasContext *s, arg_rmrr *a)
s->sew == MO_32 ?
gen_helper_vsha2cl32_vv : gen_helper_vsha2cl64_vv);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
@@ -488,7 +488,7 @@ static bool trans_vsha2ch_vv(DisasContext *s, arg_rmrr *a)
s->sew == MO_32 ?
gen_helper_vsha2ch32_vv : gen_helper_vsha2ch64_vv);
- mark_vs_dirty(s);
+ finalize_rvv_inst(s);
return true;
}
return false;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f2f0593830..735052b907 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -674,6 +674,12 @@ static void mark_vs_dirty(DisasContext *ctx)
static inline void mark_vs_dirty(DisasContext *ctx) { }
#endif
+static void finalize_rvv_inst(DisasContext *ctx)
+{
+ mark_vs_dirty(ctx);
+ ctx->vstart_eq_zero = true;
+}
+
static void gen_set_rm(DisasContext *ctx, int rm)
{
if (ctx->frm == rm) {
--
2.43.2
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v5 0/7] riscv: set vstart_eq_zero on mark_vs_dirty
2024-02-21 2:22 [PATCH v5 0/7] riscv: set vstart_eq_zero on mark_vs_dirty Daniel Henrique Barboza
` (6 preceding siblings ...)
2024-02-21 2:22 ` [PATCH v5 7/7] target/riscv: Clear vstart_qe_zero flag Daniel Henrique Barboza
@ 2024-02-21 21:24 ` Daniel Henrique Barboza
7 siblings, 0 replies; 11+ messages in thread
From: Daniel Henrique Barboza @ 2024-02-21 21:24 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, alistair.francis, bmeng, liwei1518, zhiwei_liu,
palmer, richard.henderson, max.chou
Richard,
On 2/20/24 23:22, Daniel Henrique Barboza wrote:
> Hi,
>
> In this new version we removed the remaining brconds() from
> trans_rvbf16.c.inc like Richard suggested in patch 3. Richard, I kept
> your ack in that patch.
>
> This change caused the 'cpu_vstart' global to be unused. A new patch (4)
> was added to remove it.
>
> Series based on alistair/riscv-to-apply.next.
>
> Patches missing acks: patch 4.
I missed your acks from v4 in patches 1 and 2 . I'll add them back in the next
version.
Thanks,
Daniel
>
> Changes from v4:
> - patch 3:
> - remove vstart >= vl and vl = 0 brconds from trans_fvbf16.c.inc
> - patch 4 (new):
> - remove cpu_vstart
> - v4 link: https://lore.kernel.org/qemu-riscv/20240220222510.209448-1-dbarboza@ventanamicro.com/
>
>
> Daniel Henrique Barboza (6):
> trans_rvv.c.inc: mark_vs_dirty() before loads and stores
> trans_rvv.c.inc: remove 'is_store' bool from load/store fns
> target/riscv: remove 'over' brconds from vector trans
> target/riscv/translate.c: remove 'cpu_vstart' global
> target/riscv/vector_helper.c: set vstart = 0 in GEN_VEXT_VSLIDEUP_VX()
> trans_rvv.c.inc: remove redundant mark_vs_dirty() calls
>
> Ivan Klokov (1):
> target/riscv: Clear vstart_qe_zero flag
>
> target/riscv/insn_trans/trans_rvbf16.c.inc | 18 +-
> target/riscv/insn_trans/trans_rvv.c.inc | 292 ++++++---------------
> target/riscv/insn_trans/trans_rvvk.c.inc | 30 +--
> target/riscv/translate.c | 10 +-
> target/riscv/vector_helper.c | 1 +
> 5 files changed, 100 insertions(+), 251 deletions(-)
>
^ permalink raw reply [flat|nested] 11+ messages in thread