Re: [PATCH v10 2/8] ppc/pnv: Introduce Power11 PowerNV machine

[Mike Kowal <kowal@linux.ibm.com>]

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On 9/25/2025 12:30 PM, Aditya Gupta wrote:
> The Powernv11 machine doesn't have XIVE & PHBs as of now
>
> XIVE2 interface and PHB5 added in later patches to Powernv11 machine
>
> Also add mention of Power11 to powernv documentation
>
> Note: A difference from P10's and P11's machine_class_init is, in P11
> different number of PHBs cannot be used on the command line, ie. the
> following line does NOT exist in pnv_machine_power11_class_init, which
> existed in case of Power10:
>
>      machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);

Reviewed-by: Michael Kowal<kowal@linux.ibm.com>


> Reviewed-by: Cédric Le Goater<clg@redhat.com>
> Signed-off-by: Aditya Gupta<adityag@linux.ibm.com>
> ---
>   docs/system/ppc/powernv.rst |  9 +++++----
>   hw/ppc/pnv.c                | 34 ++++++++++++++++++++++++++++++++++
>   2 files changed, 39 insertions(+), 4 deletions(-)
>
> diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst
> index f3ec2cc69c0d..5154794cc8cd 100644
> --- a/docs/system/ppc/powernv.rst
> +++ b/docs/system/ppc/powernv.rst
> @@ -1,5 +1,5 @@
> -PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``)
> -==================================================================
> +PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``, ``powernv11``)
> +================================================================================
>   
>   PowerNV (as Non-Virtualized) is the "bare metal" platform using the
>   OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can
> @@ -15,11 +15,12 @@ beyond the scope of what QEMU addresses today.
>   Supported devices
>   -----------------
>   
> - * Multi processor support for POWER8, POWER8NVL and POWER9.
> + * Multi processor support for POWER8, POWER8NVL, POWER9, Power10 and Power11.
>    * XSCOM, serial communication sideband bus to configure chiplets.
>    * Simple LPC Controller.
>    * Processor Service Interface (PSI) Controller.
> - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10).
> + * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10 &
> +   Power11).
>    * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
>    * Simple OCC is an on-chip micro-controller used for power management tasks.
>    * iBT device to handle BMC communication, with the internal BMC simulator
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 77136091bbca..423954ba7e0c 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -3235,6 +3235,35 @@ static void pnv_machine_p10_rainier_class_init(ObjectClass *oc,
>       pmc->i2c_init = pnv_rainier_i2c_init;
>   }
>   
> +static void pnv_machine_power11_class_init(ObjectClass *oc, const void *data)
> +{
> +    MachineClass *mc = MACHINE_CLASS(oc);
> +    PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
> +    static const char compat[] = "qemu,powernv11\0ibm,powernv";
> +
> +    pmc->compat = compat;
> +    pmc->compat_size = sizeof(compat);
> +    pmc->max_smt_threads = 4;
> +    pmc->has_lpar_per_thread = true;
> +    pmc->quirk_tb_big_core = true;
> +    pmc->dt_power_mgt = pnv_dt_power_mgt;
> +
> +    mc->desc = "IBM PowerNV (Non-Virtualized) Power11";
> +    mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power11_v2.0");
> +
> +    object_class_property_add_bool(oc, "big-core",
> +                                   pnv_machine_get_big_core,
> +                                   pnv_machine_set_big_core);
> +    object_class_property_set_description(oc, "big-core",
> +                              "Use big-core (aka fused-core) mode");
> +
> +    object_class_property_add_bool(oc, "lpar-per-core",
> +                                   pnv_machine_get_lpar_per_core,
> +                                   pnv_machine_set_lpar_per_core);
> +    object_class_property_set_description(oc, "lpar-per-core",
> +                              "Use 1 LPAR per core mode");
> +}
> +
>   static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
>   {
>       CPUPPCState *env = cpu_env(cs);
> @@ -3348,6 +3377,11 @@ static void pnv_machine_class_init(ObjectClass *oc, const void *data)
>       }
>   
>   static const TypeInfo types[] = {
> +    {
> +        .name          = MACHINE_TYPE_NAME("powernv11"),
> +        .parent        = TYPE_PNV_MACHINE,
> +        .class_init    = pnv_machine_power11_class_init,
> +    },
>       {
>           .name          = MACHINE_TYPE_NAME("powernv10-rainier"),
>           .parent        = MACHINE_TYPE_NAME("powernv10"),

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