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Tue, 25 Feb 2025 12:57:07 -0800 (PST) Received: from [192.168.1.67] ([38.39.164.180]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2230a000536sm18664045ad.45.2025.02.25.12.57.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Feb 2025 12:57:07 -0800 (PST) Message-ID: <829e9fd0-2d0f-45e6-ab89-d933d344cfe2@linaro.org> Date: Tue, 25 Feb 2025 12:57:06 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] hw/misc/npcm_clk: fix buffer-overflow To: Peter Maydell Cc: qemu-devel@nongnu.org, titusr@google.com, hskinnemoen@google.com, wuhaotsh@google.com, qemu-arm@nongnu.org, Tyrone Ting References: <20250224205053.104959-1-pierrick.bouvier@linaro.org> Content-Language: en-US From: Pierrick Bouvier In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/25/25 05:41, Peter Maydell wrote: > On Mon, 24 Feb 2025 at 20:51, Pierrick Bouvier > wrote: >> >> Regression introduced by cf76c4 >> (hw/misc: Add nr_regs and cold_reset_values to NPCM CLK) >> >> cold_reset_values has a different size, depending on device used >> (NPCM7xx vs NPCM8xx). However, s->regs has a fixed size, which matches >> NPCM8xx. Thus, when initializing a NPCM7xx, we go past cold_reset_values >> ending. > > >> diff --git a/hw/misc/npcm_clk.c b/hw/misc/npcm_clk.c >> index d1f29759d59..0e85974cf96 100644 >> --- a/hw/misc/npcm_clk.c >> +++ b/hw/misc/npcm_clk.c >> @@ -964,8 +964,9 @@ static void npcm_clk_enter_reset(Object *obj, ResetType type) >> NPCMCLKState *s = NPCM_CLK(obj); >> NPCMCLKClass *c = NPCM_CLK_GET_CLASS(s); >> >> - g_assert(sizeof(s->regs) >= c->nr_regs * sizeof(uint32_t)); >> - memcpy(s->regs, c->cold_reset_values, sizeof(s->regs)); >> + size_t sizeof_regs = c->nr_regs * sizeof(uint32_t); >> + g_assert(sizeof(s->regs) >= sizeof_regs); >> + memcpy(s->regs, c->cold_reset_values, sizeof_regs); >> s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); >> npcm7xx_clk_update_all_clocks(s); >> /* > > Whoops, thanks for catching this. Applied to target-arm.next, thanks. > > (Looking more closely at the cold_reset_values handling > in npcm_gcr.c, that looks not quite right in a different > way; I'll send a reply to that patch email about that.) > It may be a hole in our CI right now. Would that be interesting for CI to run all tests (check-functional + check w/o functional) with both ubsan and asan? > -- PMM