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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id e21-20020a656795000000b00502f017657dsm560501pgr.83.2023.02.22.12.27.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 22 Feb 2023 12:27:15 -0800 (PST) Message-ID: <82e90bc7-8883-62f2-a6a1-9b90e032c667@linaro.org> Date: Wed, 22 Feb 2023 10:27:11 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH v2 1/7] target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection Content-Language: en-US To: Aaron Lindsay , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Vincent Dehors , =?UTF-8?Q?Alex_Benn=c3=a9e?= , Peter Maydell References: <20230222193544.3392713-1-aaron@os.amperecomputing.com> <20230222193544.3392713-2-aaron@os.amperecomputing.com> From: Richard Henderson In-Reply-To: <20230222193544.3392713-2-aaron@os.amperecomputing.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x641.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.102, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/22/23 09:35, Aaron Lindsay wrote: > +static inline bool isar_feature_aa64_pauth_arch_qarma3(const ARMISARegisters *id) > +{ > + /* > + * Return true if pauth is enabled with the architected QARMA3 algorithm. > + * QEMU will always set APA3+GPA3 to the same value. > + */ This language isn't quite right, since GPA3 only defines values 0 and 1. Perhaps "to the same result"? > +static inline uint8_t isar_feature_pauth_get_features(const ARMISARegisters *id) 'int' is a better generic result, as 'uint8_t' is 'unsigned char' to the debugger and generally printed as such. > + if (isar_feature_aa64_pauth_arch_qarma5(id)) > + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA); > + else if (isar_feature_aa64_pauth_arch_qarma3(id)) > + return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3); > + else > + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API); Braces with if+else, always. That said, exactly one of these fields is allowed to be non-zero, so we can just unconditionally OR them all together. > +static inline bool isar_feature_aa64_pauth_epac(const ARMISARegisters *id) > +{ > + /* > + * Note that unlike most AArch64 features, EPAC is treated (in the ARM > + * psedocode, at least) as not being implemented by larger values of this > + * field. Our usage of '>=' rather than '==' here causes our implementation > + * of PAC logic to diverge slightly from ARM pseudocode. > + */ I find this comment scary -- "diverge slightly"? All I need is once sentence to indicate how this is mitigated (by testing pauth2 first where required?), or "See function_foo" (where there is more commentary), or something. > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 72b37b7cf1..448ebf8301 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -8028,11 +8028,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) > .access = PL1_R, .type = ARM_CP_CONST, > .accessfn = access_aa64_tid3, > .resetvalue = cpu->isar.id_aa64isar1 }, > - { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64, > + { .name = "ID_AA64ISAR2_EL1", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2, > .access = PL1_R, .type = ARM_CP_CONST, > .accessfn = access_aa64_tid3, > - .resetvalue = 0 }, > + .resetvalue = cpu->isar.id_aa64isar2 }, All the code adding aa64isar2 should be a separate patch. You've missed initializing it in kvm_arm_get_host_cpu_features and hvf_arm_get_host_cpu_features. r~