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Tue, 26 Oct 2021 10:39:04 -0700 (PDT) Subject: Re: [PATCH v2] hvf: arm: Ignore cache operations on MMIO To: Alexander Graf References: <13a13852-4fb4-a0f8-6740-354c8054aed1@linaro.org> <27B816F7-3670-428C-AA42-95BC7DD635CC@csgraf.de> From: Richard Henderson Message-ID: <8373048b-e930-6c69-54cd-aca33338cb76@linaro.org> Date: Tue, 26 Oct 2021 10:39:01 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <27B816F7-3670-428C-AA42-95BC7DD635CC@csgraf.de> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.215, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kettenis@openbsd.org, =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Cameron Esfahani , qemu-devel@nongnu.org, Roman Bolshakov , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/26/21 9:38 AM, Alexander Graf wrote: >> On 10/26/21 12:12 AM, Alexander Graf wrote: >>> + if (cm) { >>> + /* We don't cache MMIO regions */ >>> + advance_pc = true; >>> + break; >>> + } >>> + >>> assert(isv); >> >> The assert should come first. If the "iss valid" bit is not set, then nothing else in the word is defined. >> >> Otherwise, >> Reviewed-by: Richard Henderson > > Yes, but isv=0 for cm=1. And even in other isv=0 situations most other fields are valid (post-idx provides the correct va/pa too for example). > > Does cm=1 really give you isv=1 on other hardware? Ah hah. From 0487G.a, page D13-3191: # For other faults reported in ESR_EL2, ISV is 0 except # for the following stage 2 aborts... (which incidentally sounds like documenting around a historic chip bug, since both EL1 and EL3 do get ISV set). And of course HVF would be passing along the EL2 version, being the hypervisor. I guess the assert can stand where it is, because everything below should be one of those "following stage 2 aborts". The only thing that could be improved is a bit of commentary there at the assert. Reviewed-by: Richard Henderson r~