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From: Weiwei Li <liweiwei@iscas.ac.cn>
To: Kito Cheng <kito.cheng@sifive.com>,
	alistair.francis@wdc.com, palmer@dabbelt.com,
	frank.chang@sifive.com, qemu-devel@nongnu.org,
	qemu-riscv@nongnu.org, liweiwei@iscas.ac.cn,
	richard.henderson@linaro.org
Subject: Re: [PATCH 2/2] target/riscv: Implement dump content of vector register
Date: Sat, 9 Jul 2022 17:09:32 +0800	[thread overview]
Message-ID: <83dc5fba-f1e7-bf1c-060b-41daff4aacd0@iscas.ac.cn> (raw)
In-Reply-To: <20220708085736.94546-2-kito.cheng@sifive.com>


在 2022/7/8 下午4:57, Kito Cheng 写道:
> Implement -d cpu,vu to dump content of vector register.
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> ---
>   target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++
>   1 file changed, 31 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c1b96da7da..97b289d277 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -72,6 +72,15 @@ const char * const riscv_fpr_regnames[] = {
>     "f30/ft10", "f31/ft11"
>   };
>   
> +const char * const riscv_vr_regnames[] = {
> +  "v0",  "v1",  "v2",  "v3",  "v4",  "v5",
> +  "v6",  "v7",  "v8",  "v9",  "v10", "v11",
> +  "v12", "v13", "v14", "v15", "v16", "v17",
> +  "v18", "v19", "v20", "v21", "v22", "v23",
> +  "v24", "v25", "v26", "v27", "v28", "v29",
> +  "v30", "v31"
> +};
> +
>   static const char * const riscv_excp_names[] = {
>       "misaligned_fetch",
>       "fault_fetch",
> @@ -375,6 +384,28 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
>               }
>           }
>       }
> +    if (flags & CPU_DUMP_VU) {
> +        int vlen = cpu->cfg.vlen;
> +        int n_chunk = vlen / 64;
> +        if (vlen == 32) {
> +            for (i = 0; i < 32; i++) {
> +                qemu_fprintf(f, "0x%08" PRIx64 "\n", env->vreg[i]);
> +            }

Seems forget to dump the riscv_vr_regnames here.

Just another question: whether is it necessary to dump the vector 
related csrs too?

Regards,

Weiwei Li

> +        } else {
> +            for (i = 0; i < 32; i++) {
> +                qemu_fprintf(f, " %-8s ",
> +                             riscv_vr_regnames[i]);
> +
> +                int vec_reg_offset = i * vlen / 64;
> +                qemu_fprintf(f, "0x");
> +                for (int j = n_chunk - 1; j >= 0; --j) {
> +                    qemu_fprintf(f, "%016" PRIx64,
> +                                 env->vreg[vec_reg_offset + j]);
> +                }
> +                qemu_fprintf(f, "\n");
> +            }
> +        }
> +    }
>   }
>   
>   static void riscv_cpu_set_pc(CPUState *cs, vaddr value)



  reply	other threads:[~2022-07-09  9:13 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-08  8:57 [PATCH 1/2] util/log: Add vu to dump content of vector unit Kito Cheng
2022-07-08  8:57 ` [PATCH 2/2] target/riscv: Implement dump content of vector register Kito Cheng
2022-07-09  9:09   ` Weiwei Li [this message]
2022-07-11  8:15 ` [PATCH 1/2] util/log: Add vu to dump content of vector unit Frank Chang
2022-07-11 11:53 ` Víctor Colombo

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