From: Aravinda Prasad <aravinda@linux.vnet.ibm.com>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: paulus@ozlabs.org, qemu-ppc@nongnu.org, aik@au1.ibm.com,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v8 4/6] target/ppc: Build rtas error log upon an MCE
Date: Mon, 13 May 2019 10:30:12 +0530 [thread overview]
Message-ID: <8404cefd-cc74-0df4-a863-04572e827eff@linux.vnet.ibm.com> (raw)
In-Reply-To: <20190510095201.GA5030@umbus.fritz.box>
On Friday 10 May 2019 03:22 PM, David Gibson wrote:
> On Fri, May 10, 2019 at 12:35:13PM +0530, Aravinda Prasad wrote:
>>
>>
>> On Friday 10 May 2019 12:12 PM, David Gibson wrote:
>>> On Mon, Apr 22, 2019 at 12:33:26PM +0530, Aravinda Prasad wrote:
[...]
>>>> + /* Save gpr[3] in the guest endian mode */
>>>> + if ((*pcc->interrupts_big_endian)(cpu)) {
>>>> + env->gpr[3] = cpu_to_be64(rtas_addr + RTAS_ERRLOG_OFFSET);
>>>
>>> I don't think this is right. AIUI env->gpr[] are all stored in *host*
>>> endianness (for ease of doing arithmetic).
>>
>> env-gpr[3] is later used by guest to fetch the RTAS log. My guess is
>> that we will not do an endianness change of all the gprs during a switch
>> from host to guest (that will be costly).
>
> There's no need to "change endianness". In TCG the host needs to do
> arithmetic on the values and so they are in host endian. With KVM the
> env values are only synchronized when we enter/exit KVM and they're
> going to registers, not memory and so have no endianness.
Ah.. ok.
>
>> But let me cross check.
>>
>>>
>>>> + } else {
>>>> + env->gpr[3] = cpu_to_le64(rtas_addr + RTAS_ERRLOG_OFFSET);
>>>> + }
>>>> +
>>>> + env->nip = spapr->guest_machine_check_addr;
>>>> +}
>>>> +
>>>> void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered)
>>>> {
>>>> SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
>>>> @@ -640,6 +881,10 @@ void spapr_mce_req_event(PowerPCCPU *cpu, bool recovered)
>>>> }
>>>> }
>>>> spapr->mc_status = cpu->vcpu_id;
>>>> +
>>>> + spapr_mce_dispatch_elog(cpu, recovered);
>>>> +
>>>> + return;
>>>> }
>>>>
>>>> static void check_exception(PowerPCCPU *cpu, SpaprMachineState *spapr,
>>>> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
>>>> index f7204d0..03f34bf 100644
>>>> --- a/include/hw/ppc/spapr.h
>>>> +++ b/include/hw/ppc/spapr.h
>>>> @@ -661,6 +661,9 @@ target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
>>>> #define DIAGNOSTICS_RUN_MODE_IMMEDIATE 2
>>>> #define DIAGNOSTICS_RUN_MODE_PERIODIC 3
>>>>
>>>> +/* Offset from rtas-base where error log is placed */
>>>> +#define RTAS_ERRLOG_OFFSET 0x25
>>>
>>> Is this offset PAPR defined, or chosen here? Using an entirely
>>> unaliged (odd) address seems a very strange choice.
>>
>> This is not PAPR defined. I will make it 0x30. Or do you prefer any
>> other offset?
>
> 0x30 should be fine.
ok..
>
--
Regards,
Aravinda
next prev parent reply other threads:[~2019-05-13 5:01 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-22 7:02 [Qemu-devel] [PATCH v8 0/6] target-ppc/spapr: Add FWNMI support in QEMU for PowerKVM guests Aravinda Prasad
2019-04-22 7:02 ` Aravinda Prasad
2019-04-22 7:02 ` [Qemu-devel] [PATCH v8 1/6] ppc: spapr: Handle "ibm, nmi-register" and "ibm, nmi-interlock" RTAS calls Aravinda Prasad
2019-04-22 7:02 ` Aravinda Prasad
2019-04-23 6:45 ` David Gibson
2019-04-23 6:45 ` David Gibson
2019-04-25 4:56 ` Aravinda Prasad
2019-04-25 4:56 ` Aravinda Prasad
2019-05-10 9:06 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
2019-05-10 9:54 ` David Gibson
2019-05-10 14:33 ` Greg Kurz
2019-05-13 4:57 ` Aravinda Prasad
2019-05-13 4:53 ` Aravinda Prasad
2019-04-22 7:03 ` [Qemu-devel] [PATCH v8 2/6] Wrapper function to wait on condition for the main loop mutex Aravinda Prasad
2019-04-22 7:03 ` Aravinda Prasad
2019-04-23 6:47 ` David Gibson
2019-04-23 6:47 ` David Gibson
2019-05-10 13:14 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
2019-04-22 7:03 ` [Qemu-devel] [PATCH v8 3/6] target/ppc: Handle NMI guest exit Aravinda Prasad
2019-04-22 7:03 ` Aravinda Prasad
2019-04-23 6:53 ` David Gibson
2019-04-23 6:53 ` David Gibson
2019-04-24 4:50 ` [Qemu-devel] [Qemu-ppc] " Aravinda Prasad
2019-04-24 4:50 ` Aravinda Prasad
2019-05-10 6:37 ` David Gibson
2019-05-10 6:58 ` Aravinda Prasad
2019-05-10 16:25 ` Greg Kurz
2019-05-13 5:40 ` Aravinda Prasad
2019-05-13 5:56 ` David Gibson
2019-04-22 7:03 ` [Qemu-devel] [PATCH v8 4/6] target/ppc: Build rtas error log upon an MCE Aravinda Prasad
2019-04-22 7:03 ` Aravinda Prasad
2019-04-23 14:38 ` Fabiano Rosas
2019-04-23 14:38 ` Fabiano Rosas
2019-04-24 4:51 ` [Qemu-devel] [Qemu-ppc] " Aravinda Prasad
2019-04-24 4:51 ` Aravinda Prasad
2019-05-10 6:42 ` [Qemu-devel] " David Gibson
2019-05-10 7:05 ` Aravinda Prasad
2019-05-10 9:52 ` David Gibson
2019-05-13 5:00 ` Aravinda Prasad [this message]
2019-05-13 11:30 ` [Qemu-devel] [Qemu-ppc] " Greg Kurz
2019-05-14 0:08 ` David Gibson
2019-05-14 4:26 ` Aravinda Prasad
2019-05-14 4:40 ` David Gibson
2019-05-14 5:06 ` Aravinda Prasad
2019-05-16 1:47 ` David Gibson
2019-05-16 4:54 ` Aravinda Prasad
2019-04-22 7:03 ` [Qemu-devel] [PATCH v8 5/6] ppc: spapr: Enable FWNMI capability Aravinda Prasad
2019-04-22 7:03 ` Aravinda Prasad
2019-05-10 6:46 ` David Gibson
2019-05-10 7:15 ` [Qemu-devel] [Qemu-ppc] " Aravinda Prasad
2019-05-10 9:53 ` David Gibson
2019-05-13 10:30 ` Aravinda Prasad
2019-05-14 4:47 ` David Gibson
2019-05-14 5:32 ` Aravinda Prasad
2019-05-16 1:45 ` David Gibson
2019-05-16 4:59 ` Aravinda Prasad
2019-04-22 7:03 ` [Qemu-devel] [PATCH v8 6/6] migration: Block migration while handling machine check Aravinda Prasad
2019-04-22 7:03 ` Aravinda Prasad
2019-05-10 6:51 ` David Gibson
2019-05-10 7:16 ` Aravinda Prasad
2019-05-29 5:46 ` [Qemu-devel] [Qemu-ppc] " Aravinda Prasad
2019-05-16 10:54 ` Greg Kurz
2019-05-16 10:59 ` Aravinda Prasad
2019-05-16 14:17 ` Dr. David Alan Gilbert
2019-05-20 5:57 ` Aravinda Prasad
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