* [PATCH 01/13] aspeed: ast27x0: Map unimplemented devices in SoC memory
2025-03-13 5:40 [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine Steven Lee via
@ 2025-03-13 5:40 ` Steven Lee via
2025-03-25 17:30 ` Cédric Le Goater
2025-03-13 5:40 ` [PATCH 02/13] aspeed: ast27x0: Correct hex notation for device addresses Steven Lee via
` (12 subsequent siblings)
13 siblings, 1 reply; 26+ messages in thread
From: Steven Lee via @ 2025-03-13 5:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
Maps following unimplemented devices in SoC memory
- dpmcu
- iomem
- iomem0
- iomem1
- ltpi
Iomem, Iomem0 and Iomem1 include unimplemented controllers in the
memory ranges 0x0 - 0x1000000, 0x120000000 - 0x121000000 and
0x14000000 - 0x141000000.
For instance:
- USB hub at 0x12010000
- eSPI at 0x14C5000
- PWM at 0x140C0000
DPMCU stands for Display Port MCU controller. LTPI is used to connect
to AST1700.
AST1700 is an I/O expander that supports the DC-SCM 2.1 LTPI protocol.
It provides AST2700 with additional GPIO, UART, I3C, and other
interfaces.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: Iea6c11651c40e341a395b6dbb81975ea2639aebd
---
include/hw/arm/aspeed_soc.h | 6 +++++
hw/arm/aspeed_ast27x0.c | 51 ++++++++++++++++++++++++++++++++-----
2 files changed, 50 insertions(+), 7 deletions(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index f899356ed9..c46ec6302d 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -90,6 +90,8 @@ struct AspeedSoCState {
SerialMM uart[ASPEED_UARTS_NUM];
Clock *sysclk;
UnimplementedDeviceState iomem;
+ UnimplementedDeviceState iomem0;
+ UnimplementedDeviceState iomem1;
UnimplementedDeviceState video;
UnimplementedDeviceState emmc_boot_controller;
UnimplementedDeviceState dpmcu;
@@ -97,6 +99,7 @@ struct AspeedSoCState {
UnimplementedDeviceState espi;
UnimplementedDeviceState udc;
UnimplementedDeviceState sgpiom;
+ UnimplementedDeviceState ltpi;
UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
AspeedAPB2OPBState fsi[2];
};
@@ -171,6 +174,9 @@ const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
enum {
ASPEED_DEV_SPI_BOOT,
ASPEED_DEV_IOMEM,
+ ASPEED_DEV_IOMEM0,
+ ASPEED_DEV_IOMEM1,
+ ASPEED_DEV_LTPI,
ASPEED_DEV_UART0,
ASPEED_DEV_UART1,
ASPEED_DEV_UART2,
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index dce7255a2c..a3fe2582f8 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -23,8 +23,16 @@
#include "qobject/qlist.h"
#include "qemu/log.h"
+#define AST2700_SOC_IO_SIZE 0x01000000
+#define AST2700_SOC_IOMEM_SIZE 0x01000000
+#define AST2700_SOC_DPMCU_SIZE 0x00040000
+#define AST2700_SOC_LTPI_SIZE 0x01000000
+
static const hwaddr aspeed_soc_ast2700_memmap[] = {
+ [ASPEED_DEV_IOMEM] = 0x00000000,
[ASPEED_DEV_SRAM] = 0x10000000,
+ [ASPEED_DEV_DPMCU] = 0x11000000,
+ [ASPEED_DEV_IOMEM0] = 0x12000000,
[ASPEED_DEV_HACE] = 0x12070000,
[ASPEED_DEV_EMMC] = 0x12090000,
[ASPEED_DEV_INTC] = 0x12100000,
@@ -36,6 +44,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_TIMER1] = 0x12C10000,
[ASPEED_DEV_SLI] = 0x12C17000,
[ASPEED_DEV_UART4] = 0X12C1A000,
+ [ASPEED_DEV_IOMEM1] = 0x14000000,
[ASPEED_DEV_FMC] = 0x14000000,
[ASPEED_DEV_SPI0] = 0x14010000,
[ASPEED_DEV_SPI1] = 0x14020000,
@@ -68,6 +77,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_UART12] = 0X14C33B00,
[ASPEED_DEV_WDT] = 0x14C37000,
[ASPEED_DEV_SPI_BOOT] = 0x100000000,
+ [ASPEED_DEV_LTPI] = 0x300000000,
[ASPEED_DEV_SDRAM] = 0x400000000,
};
@@ -491,6 +501,16 @@ static void aspeed_soc_ast2700_init(Object *obj)
snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
object_initialize_child(obj, "hace", &s->hace, typename);
+ object_initialize_child(obj, "dpmcu", &s->dpmcu,
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "ltpi", &s->ltpi,
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "iomem", &s->iomem,
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "iomem0", &s->iomem0,
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "iomem1", &s->iomem1,
+ TYPE_UNIMPLEMENTED_DEVICE);
}
/*
@@ -526,8 +546,10 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(gicbusdev, errp)) {
return false;
}
- sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]);
- sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]);
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 0,
+ sc->memmap[ASPEED_GIC_DIST]);
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 1,
+ sc->memmap[ASPEED_GIC_REDIST]);
for (i = 0; i < sc->num_cpus; i++) {
DeviceState *cpudev = DEVICE(&a->cpu[i]);
@@ -876,11 +898,26 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
- create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
- create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
- create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);
- create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000);
- create_unimplemented_device("ast2700.io", 0x0, 0x4000000);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu),
+ "aspeed.dpmcu",
+ sc->memmap[ASPEED_DEV_DPMCU],
+ AST2700_SOC_DPMCU_SIZE);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->ltpi),
+ "aspeed.ltpi",
+ sc->memmap[ASPEED_DEV_LTPI],
+ AST2700_SOC_LTPI_SIZE);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem),
+ "aspeed.io",
+ sc->memmap[ASPEED_DEV_IOMEM],
+ AST2700_SOC_IO_SIZE);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem0),
+ "aspeed.iomem0",
+ sc->memmap[ASPEED_DEV_IOMEM0],
+ AST2700_SOC_IOMEM_SIZE);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem1),
+ "aspeed.iomem1",
+ sc->memmap[ASPEED_DEV_IOMEM1],
+ AST2700_SOC_IOMEM_SIZE);
}
static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, void *data)
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 01/13] aspeed: ast27x0: Map unimplemented devices in SoC memory
2025-03-13 5:40 ` [PATCH 01/13] aspeed: ast27x0: Map unimplemented devices in SoC memory Steven Lee via
@ 2025-03-25 17:30 ` Cédric Le Goater
0 siblings, 0 replies; 26+ messages in thread
From: Cédric Le Goater @ 2025-03-25 17:30 UTC (permalink / raw)
To: Steven Lee, Peter Maydell, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
Hello Steven,
On 3/13/25 06:40, Steven Lee wrote:
> Maps following unimplemented devices in SoC memory
> - dpmcu
> - iomem
> - iomem0
> - iomem1
> - ltpi
>
> Iomem, Iomem0 and Iomem1 include unimplemented controllers in the
> memory ranges 0x0 - 0x1000000, 0x120000000 - 0x121000000 and
> 0x14000000 - 0x141000000.
>
> For instance:
> - USB hub at 0x12010000
> - eSPI at 0x14C5000
> - PWM at 0x140C0000
>
> DPMCU stands for Display Port MCU controller. LTPI is used to connect
> to AST1700.
> AST1700 is an I/O expander that supports the DC-SCM 2.1 LTPI protocol.
> It provides AST2700 with additional GPIO, UART, I3C, and other
> interfaces.
For your awareness, I keep in the aspeed branch [1] a series
adding I3C support. It was sent by Google in 2023 [2]. In case
you are interested to upstream.
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
[1] https://github.com/legoater/qemu/commits/aspeed-10.0
[2] https://lore.kernel.org/qemu-devel/20230331010131.1412571-1-komlodi@google.com/
>
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> Change-Id: Iea6c11651c40e341a395b6dbb81975ea2639aebd
> ---
> include/hw/arm/aspeed_soc.h | 6 +++++
> hw/arm/aspeed_ast27x0.c | 51 ++++++++++++++++++++++++++++++++-----
> 2 files changed, 50 insertions(+), 7 deletions(-)
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index f899356ed9..c46ec6302d 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -90,6 +90,8 @@ struct AspeedSoCState {
> SerialMM uart[ASPEED_UARTS_NUM];
> Clock *sysclk;
> UnimplementedDeviceState iomem;
> + UnimplementedDeviceState iomem0;
> + UnimplementedDeviceState iomem1;
> UnimplementedDeviceState video;
> UnimplementedDeviceState emmc_boot_controller;
> UnimplementedDeviceState dpmcu;
> @@ -97,6 +99,7 @@ struct AspeedSoCState {
> UnimplementedDeviceState espi;
> UnimplementedDeviceState udc;
> UnimplementedDeviceState sgpiom;
> + UnimplementedDeviceState ltpi;
> UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
> AspeedAPB2OPBState fsi[2];
> };
> @@ -171,6 +174,9 @@ const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
> enum {
> ASPEED_DEV_SPI_BOOT,
> ASPEED_DEV_IOMEM,
> + ASPEED_DEV_IOMEM0,
> + ASPEED_DEV_IOMEM1,
> + ASPEED_DEV_LTPI,
> ASPEED_DEV_UART0,
> ASPEED_DEV_UART1,
> ASPEED_DEV_UART2,
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index dce7255a2c..a3fe2582f8 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -23,8 +23,16 @@
> #include "qobject/qlist.h"
> #include "qemu/log.h"
>
> +#define AST2700_SOC_IO_SIZE 0x01000000
> +#define AST2700_SOC_IOMEM_SIZE 0x01000000
> +#define AST2700_SOC_DPMCU_SIZE 0x00040000
> +#define AST2700_SOC_LTPI_SIZE 0x01000000
> +
> static const hwaddr aspeed_soc_ast2700_memmap[] = {
> + [ASPEED_DEV_IOMEM] = 0x00000000,
> [ASPEED_DEV_SRAM] = 0x10000000,
> + [ASPEED_DEV_DPMCU] = 0x11000000,
> + [ASPEED_DEV_IOMEM0] = 0x12000000,
> [ASPEED_DEV_HACE] = 0x12070000,
> [ASPEED_DEV_EMMC] = 0x12090000,
> [ASPEED_DEV_INTC] = 0x12100000,
> @@ -36,6 +44,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_TIMER1] = 0x12C10000,
> [ASPEED_DEV_SLI] = 0x12C17000,
> [ASPEED_DEV_UART4] = 0X12C1A000,
> + [ASPEED_DEV_IOMEM1] = 0x14000000,
> [ASPEED_DEV_FMC] = 0x14000000,
> [ASPEED_DEV_SPI0] = 0x14010000,
> [ASPEED_DEV_SPI1] = 0x14020000,
> @@ -68,6 +77,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_UART12] = 0X14C33B00,
> [ASPEED_DEV_WDT] = 0x14C37000,
> [ASPEED_DEV_SPI_BOOT] = 0x100000000,
> + [ASPEED_DEV_LTPI] = 0x300000000,
> [ASPEED_DEV_SDRAM] = 0x400000000,
> };
>
> @@ -491,6 +501,16 @@ static void aspeed_soc_ast2700_init(Object *obj)
>
> snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
> object_initialize_child(obj, "hace", &s->hace, typename);
> + object_initialize_child(obj, "dpmcu", &s->dpmcu,
> + TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "ltpi", &s->ltpi,
> + TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "iomem", &s->iomem,
> + TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "iomem0", &s->iomem0,
> + TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "iomem1", &s->iomem1,
> + TYPE_UNIMPLEMENTED_DEVICE);
> }
>
> /*
> @@ -526,8 +546,10 @@ static bool aspeed_soc_ast2700_gic_realize(DeviceState *dev, Error **errp)
> if (!sysbus_realize(gicbusdev, errp)) {
> return false;
> }
> - sysbus_mmio_map(gicbusdev, 0, sc->memmap[ASPEED_GIC_DIST]);
> - sysbus_mmio_map(gicbusdev, 1, sc->memmap[ASPEED_GIC_REDIST]);
> + aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 0,
> + sc->memmap[ASPEED_GIC_DIST]);
> + aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->gic), 1,
> + sc->memmap[ASPEED_GIC_REDIST]);
>
> for (i = 0; i < sc->num_cpus; i++) {
> DeviceState *cpudev = DEVICE(&a->cpu[i]);
> @@ -876,11 +898,26 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
> aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
>
> - create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000);
> - create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000);
> - create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000);
> - create_unimplemented_device("ast2700.ltpi", 0x30000000, 0x1000000);
> - create_unimplemented_device("ast2700.io", 0x0, 0x4000000);
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu),
> + "aspeed.dpmcu",
> + sc->memmap[ASPEED_DEV_DPMCU],
> + AST2700_SOC_DPMCU_SIZE);
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->ltpi),
> + "aspeed.ltpi",
> + sc->memmap[ASPEED_DEV_LTPI],
> + AST2700_SOC_LTPI_SIZE);
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem),
> + "aspeed.io",
> + sc->memmap[ASPEED_DEV_IOMEM],
> + AST2700_SOC_IO_SIZE);
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem0),
> + "aspeed.iomem0",
> + sc->memmap[ASPEED_DEV_IOMEM0],
> + AST2700_SOC_IOMEM_SIZE);
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem1),
> + "aspeed.iomem1",
> + sc->memmap[ASPEED_DEV_IOMEM1],
> + AST2700_SOC_IOMEM_SIZE);
> }
>
> static void aspeed_soc_ast2700a0_class_init(ObjectClass *oc, void *data)
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 02/13] aspeed: ast27x0: Correct hex notation for device addresses
2025-03-13 5:40 [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine Steven Lee via
2025-03-13 5:40 ` [PATCH 01/13] aspeed: ast27x0: Map unimplemented devices in SoC memory Steven Lee via
@ 2025-03-13 5:40 ` Steven Lee via
2025-03-25 17:31 ` Cédric Le Goater
2025-03-13 5:40 ` [PATCH 03/13] hw/intc/aspeed: Add support for AST2700 SSP INTC Steven Lee via
` (11 subsequent siblings)
13 siblings, 1 reply; 26+ messages in thread
From: Steven Lee via @ 2025-03-13 5:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
Corrected the hexadecimal notation for several device addresses in the
aspeed_soc_ast2700_memmap array by changing the uppercase 'X' to
lowercase 'x'.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: I45426e18ea8e68d7ccdf9b60c4ea235c4da33cc3
---
hw/arm/aspeed_ast27x0.c | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
index a3fe2582f8..b4e4c5e4b6 100644
--- a/hw/arm/aspeed_ast27x0.c
+++ b/hw/arm/aspeed_ast27x0.c
@@ -43,7 +43,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_RTC] = 0x12C0F000,
[ASPEED_DEV_TIMER1] = 0x12C10000,
[ASPEED_DEV_SLI] = 0x12C17000,
- [ASPEED_DEV_UART4] = 0X12C1A000,
+ [ASPEED_DEV_UART4] = 0x12C1A000,
[ASPEED_DEV_IOMEM1] = 0x14000000,
[ASPEED_DEV_FMC] = 0x14000000,
[ASPEED_DEV_SPI0] = 0x14010000,
@@ -62,19 +62,19 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
[ASPEED_DEV_I2C] = 0x14C0F000,
[ASPEED_DEV_INTCIO] = 0x14C18000,
[ASPEED_DEV_SLIIO] = 0x14C1E000,
- [ASPEED_DEV_VUART] = 0X14C30000,
- [ASPEED_DEV_UART0] = 0X14C33000,
- [ASPEED_DEV_UART1] = 0X14C33100,
- [ASPEED_DEV_UART2] = 0X14C33200,
- [ASPEED_DEV_UART3] = 0X14C33300,
- [ASPEED_DEV_UART5] = 0X14C33400,
- [ASPEED_DEV_UART6] = 0X14C33500,
- [ASPEED_DEV_UART7] = 0X14C33600,
- [ASPEED_DEV_UART8] = 0X14C33700,
- [ASPEED_DEV_UART9] = 0X14C33800,
- [ASPEED_DEV_UART10] = 0X14C33900,
- [ASPEED_DEV_UART11] = 0X14C33A00,
- [ASPEED_DEV_UART12] = 0X14C33B00,
+ [ASPEED_DEV_VUART] = 0x14C30000,
+ [ASPEED_DEV_UART0] = 0x14C33000,
+ [ASPEED_DEV_UART1] = 0x14C33100,
+ [ASPEED_DEV_UART2] = 0x14C33200,
+ [ASPEED_DEV_UART3] = 0x14C33300,
+ [ASPEED_DEV_UART5] = 0x14C33400,
+ [ASPEED_DEV_UART6] = 0x14C33500,
+ [ASPEED_DEV_UART7] = 0x14C33600,
+ [ASPEED_DEV_UART8] = 0x14C33700,
+ [ASPEED_DEV_UART9] = 0x14C33800,
+ [ASPEED_DEV_UART10] = 0x14C33900,
+ [ASPEED_DEV_UART11] = 0x14C33A00,
+ [ASPEED_DEV_UART12] = 0x14C33B00,
[ASPEED_DEV_WDT] = 0x14C37000,
[ASPEED_DEV_SPI_BOOT] = 0x100000000,
[ASPEED_DEV_LTPI] = 0x300000000,
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 02/13] aspeed: ast27x0: Correct hex notation for device addresses
2025-03-13 5:40 ` [PATCH 02/13] aspeed: ast27x0: Correct hex notation for device addresses Steven Lee via
@ 2025-03-25 17:31 ` Cédric Le Goater
0 siblings, 0 replies; 26+ messages in thread
From: Cédric Le Goater @ 2025-03-25 17:31 UTC (permalink / raw)
To: Steven Lee, Peter Maydell, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
On 3/13/25 06:40, Steven Lee wrote:
> Corrected the hexadecimal notation for several device addresses in the
> aspeed_soc_ast2700_memmap array by changing the uppercase 'X' to
> lowercase 'x'.
>
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> Change-Id: I45426e18ea8e68d7ccdf9b60c4ea235c4da33cc3
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> hw/arm/aspeed_ast27x0.c | 28 ++++++++++++++--------------> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index a3fe2582f8..b4e4c5e4b6 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -43,7 +43,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_RTC] = 0x12C0F000,
> [ASPEED_DEV_TIMER1] = 0x12C10000,
> [ASPEED_DEV_SLI] = 0x12C17000,
> - [ASPEED_DEV_UART4] = 0X12C1A000,
> + [ASPEED_DEV_UART4] = 0x12C1A000,
> [ASPEED_DEV_IOMEM1] = 0x14000000,
> [ASPEED_DEV_FMC] = 0x14000000,
> [ASPEED_DEV_SPI0] = 0x14010000,
> @@ -62,19 +62,19 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = {
> [ASPEED_DEV_I2C] = 0x14C0F000,
> [ASPEED_DEV_INTCIO] = 0x14C18000,
> [ASPEED_DEV_SLIIO] = 0x14C1E000,
> - [ASPEED_DEV_VUART] = 0X14C30000,
> - [ASPEED_DEV_UART0] = 0X14C33000,
> - [ASPEED_DEV_UART1] = 0X14C33100,
> - [ASPEED_DEV_UART2] = 0X14C33200,
> - [ASPEED_DEV_UART3] = 0X14C33300,
> - [ASPEED_DEV_UART5] = 0X14C33400,
> - [ASPEED_DEV_UART6] = 0X14C33500,
> - [ASPEED_DEV_UART7] = 0X14C33600,
> - [ASPEED_DEV_UART8] = 0X14C33700,
> - [ASPEED_DEV_UART9] = 0X14C33800,
> - [ASPEED_DEV_UART10] = 0X14C33900,
> - [ASPEED_DEV_UART11] = 0X14C33A00,
> - [ASPEED_DEV_UART12] = 0X14C33B00,
> + [ASPEED_DEV_VUART] = 0x14C30000,
> + [ASPEED_DEV_UART0] = 0x14C33000,
> + [ASPEED_DEV_UART1] = 0x14C33100,
> + [ASPEED_DEV_UART2] = 0x14C33200,
> + [ASPEED_DEV_UART3] = 0x14C33300,
> + [ASPEED_DEV_UART5] = 0x14C33400,
> + [ASPEED_DEV_UART6] = 0x14C33500,
> + [ASPEED_DEV_UART7] = 0x14C33600,
> + [ASPEED_DEV_UART8] = 0x14C33700,
> + [ASPEED_DEV_UART9] = 0x14C33800,
> + [ASPEED_DEV_UART10] = 0x14C33900,
> + [ASPEED_DEV_UART11] = 0x14C33A00,
> + [ASPEED_DEV_UART12] = 0x14C33B00,
> [ASPEED_DEV_WDT] = 0x14C37000,
> [ASPEED_DEV_SPI_BOOT] = 0x100000000,
> [ASPEED_DEV_LTPI] = 0x300000000,
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 03/13] hw/intc/aspeed: Add support for AST2700 SSP INTC
2025-03-13 5:40 [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine Steven Lee via
2025-03-13 5:40 ` [PATCH 01/13] aspeed: ast27x0: Map unimplemented devices in SoC memory Steven Lee via
2025-03-13 5:40 ` [PATCH 02/13] aspeed: ast27x0: Correct hex notation for device addresses Steven Lee via
@ 2025-03-13 5:40 ` Steven Lee via
2025-04-07 15:12 ` Cédric Le Goater
2025-03-13 5:40 ` [PATCH 04/13] hw/intc/aspeed: Add support for AST2700 TSP INTC Steven Lee via
` (10 subsequent siblings)
13 siblings, 1 reply; 26+ messages in thread
From: Steven Lee via @ 2025-03-13 5:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
- Define new types for ast2700ssp INTC and INTCIO
- Add register definitions for SSP INTC and INTCIO
- Implement write handlers for SSP INTC and INTCIO
- Register new types in aspeed_intc_register_types
The design of the SSP INTC and INTCIO controllers is similar to
AST2700, with the following differences:
- AST2700
Support GICINT128 to GICINT136 in INTC
The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196
- AST2700-ssp
Support SSPINT128 to SSPINT136 in INTC
The INTCIO SSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> SSPINT 160
Bit 1 -> SSPINT 161
Bit 2 -> SSPINT 162
Bit 3 -> SSPINT 163
Bit 4 -> SSPINT 164
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: I5329767b21c0e982d3afcb87c7d1690cc04ce2ef
---
include/hw/intc/aspeed_intc.h | 3 +
hw/intc/aspeed_intc.c | 211 ++++++++++++++++++++++++++++++++++
2 files changed, 214 insertions(+)
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 3727ba24be..746f159bf3 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -15,6 +15,9 @@
#define TYPE_ASPEED_INTC "aspeed.intc"
#define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
#define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
+#define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
+#define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp"
+
OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
#define ASPEED_INTC_MAX_INPINS 10
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 3fd417084f..1f8b4d4d36 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -62,6 +62,50 @@ REG32(GICINT196_STATUS, 0x44)
REG32(GICINT197_EN, 0x50)
REG32(GICINT197_STATUS, 0x54)
+/*
+ * SSP INTC Registers
+ */
+REG32(SSPINT128_EN, 0x2000)
+REG32(SSPINT128_STATUS, 0x2004)
+REG32(SSPINT129_EN, 0x2100)
+REG32(SSPINT129_STATUS, 0x2104)
+REG32(SSPINT130_EN, 0x2200)
+REG32(SSPINT130_STATUS, 0x2204)
+REG32(SSPINT131_EN, 0x2300)
+REG32(SSPINT131_STATUS, 0x2304)
+REG32(SSPINT132_EN, 0x2400)
+REG32(SSPINT132_STATUS, 0x2404)
+REG32(SSPINT133_EN, 0x2500)
+REG32(SSPINT133_STATUS, 0x2504)
+REG32(SSPINT134_EN, 0x2600)
+REG32(SSPINT134_STATUS, 0x2604)
+REG32(SSPINT135_EN, 0x2700)
+REG32(SSPINT135_STATUS, 0x2704)
+REG32(SSPINT136_EN, 0x2800)
+REG32(SSPINT136_STATUS, 0x2804)
+REG32(SSPINT137_EN, 0x2900)
+REG32(SSPINT137_STATUS, 0x2904)
+REG32(SSPINT138_EN, 0x2A00)
+REG32(SSPINT138_STATUS, 0x2A04)
+REG32(SSPINT160_169_EN, 0x2B00)
+REG32(SSPINT160_169_STATUS, 0x2B04)
+
+/*
+ * SSP INTCIO Registers
+ */
+REG32(SSPINT160_EN, 0x180)
+REG32(SSPINT160_STATUS, 0x184)
+REG32(SSPINT161_EN, 0x190)
+REG32(SSPINT161_STATUS, 0x194)
+REG32(SSPINT162_EN, 0x1A0)
+REG32(SSPINT162_STATUS, 0x1A4)
+REG32(SSPINT163_EN, 0x1B0)
+REG32(SSPINT163_STATUS, 0x1B4)
+REG32(SSPINT164_EN, 0x1C0)
+REG32(SSPINT164_STATUS, 0x1C4)
+REG32(SSPINT165_EN, 0x1D0)
+REG32(SSPINT165_STATUS, 0x1D4)
+
static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
uint32_t reg)
{
@@ -452,6 +496,50 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
return;
}
+static void aspeed_ssp_intc_write(void *opaque, hwaddr offset, uint64_t data,
+ unsigned size)
+{
+ AspeedINTCState *s = ASPEED_INTC(opaque);
+ const char *name = object_get_typename(OBJECT(s));
+ uint32_t reg = offset >> 2;
+
+ trace_aspeed_intc_write(name, offset, size, data);
+
+ switch (reg) {
+ case R_SSPINT128_EN:
+ case R_SSPINT129_EN:
+ case R_SSPINT130_EN:
+ case R_SSPINT131_EN:
+ case R_SSPINT132_EN:
+ case R_SSPINT133_EN:
+ case R_SSPINT134_EN:
+ case R_SSPINT135_EN:
+ case R_SSPINT136_EN:
+ case R_SSPINT160_169_EN:
+ aspeed_intc_enable_handler(s, offset, data);
+ break;
+ case R_SSPINT128_STATUS:
+ case R_SSPINT129_STATUS:
+ case R_SSPINT130_STATUS:
+ case R_SSPINT131_STATUS:
+ case R_SSPINT132_STATUS:
+ case R_SSPINT133_STATUS:
+ case R_SSPINT134_STATUS:
+ case R_SSPINT135_STATUS:
+ case R_SSPINT136_STATUS:
+ aspeed_intc_status_handler(s, offset, data);
+ break;
+ case R_SSPINT160_169_STATUS:
+ aspeed_intc_status_handler_multi_outpins(s, offset, data);
+ break;
+ default:
+ s->regs[reg] = data;
+ break;
+ }
+
+ return;
+}
+
static uint64_t aspeed_intcio_read(void *opaque, hwaddr offset,
unsigned int size)
{
@@ -500,6 +588,39 @@ static void aspeed_intcio_write(void *opaque, hwaddr offset, uint64_t data,
return;
}
+static void aspeed_ssp_intcio_write(void *opaque, hwaddr offset, uint64_t data,
+ unsigned size)
+{
+ AspeedINTCState *s = ASPEED_INTC(opaque);
+ const char *name = object_get_typename(OBJECT(s));
+ uint32_t reg = offset >> 2;
+
+ trace_aspeed_intc_write(name, offset, size, data);
+
+ switch (reg) {
+ case R_SSPINT160_EN:
+ case R_SSPINT161_EN:
+ case R_SSPINT162_EN:
+ case R_SSPINT163_EN:
+ case R_SSPINT164_EN:
+ case R_SSPINT165_EN:
+ aspeed_intc_enable_handler(s, offset, data);
+ break;
+ case R_SSPINT160_STATUS:
+ case R_SSPINT161_STATUS:
+ case R_SSPINT162_STATUS:
+ case R_SSPINT163_STATUS:
+ case R_SSPINT164_STATUS:
+ case R_SSPINT165_STATUS:
+ aspeed_intc_status_handler(s, offset, data);
+ break;
+ default:
+ s->regs[reg] = data;
+ break;
+ }
+
+ return;
+}
static const MemoryRegionOps aspeed_intc_ops = {
.read = aspeed_intc_read,
@@ -521,6 +642,26 @@ static const MemoryRegionOps aspeed_intcio_ops = {
}
};
+static const MemoryRegionOps aspeed_ssp_intc_ops = {
+ .read = aspeed_intc_read,
+ .write = aspeed_ssp_intc_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
+
+static const MemoryRegionOps aspeed_ssp_intcio_ops = {
+ .read = aspeed_intcio_read,
+ .write = aspeed_ssp_intcio_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
+
static void aspeed_intc_instance_init(Object *obj)
{
AspeedINTCState *s = ASPEED_INTC(obj);
@@ -678,11 +819,81 @@ static const TypeInfo aspeed_2700_intcio_info = {
.class_init = aspeed_2700_intcio_class_init,
};
+static AspeedINTCIRQ aspeed_2700ssp_intc_irqs[ASPEED_INTC_MAX_INPINS] = {
+ {0, 0, 10, R_SSPINT160_169_EN, R_SSPINT160_169_STATUS},
+ {1, 10, 1, R_SSPINT128_EN, R_SSPINT128_STATUS},
+ {2, 11, 1, R_SSPINT129_EN, R_SSPINT129_STATUS},
+ {3, 12, 1, R_SSPINT130_EN, R_SSPINT130_STATUS},
+ {4, 13, 1, R_SSPINT131_EN, R_SSPINT131_STATUS},
+ {5, 14, 1, R_SSPINT132_EN, R_SSPINT132_STATUS},
+ {6, 15, 1, R_SSPINT133_EN, R_SSPINT133_STATUS},
+ {7, 16, 1, R_SSPINT134_EN, R_SSPINT134_STATUS},
+ {8, 17, 1, R_SSPINT135_EN, R_SSPINT135_STATUS},
+ {9, 18, 1, R_SSPINT136_EN, R_SSPINT136_STATUS},
+};
+
+static void aspeed_2700ssp_intc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
+
+ dc->desc = "ASPEED 2700 SSP INTC Controller";
+ aic->num_lines = 32;
+ aic->num_inpins = 10;
+ aic->num_outpins = 19;
+ aic->mem_size = 0x4000;
+ aic->nr_regs = 0x2B08 >> 2;
+ aic->reg_offset = 0x0;
+ aic->reg_ops = &aspeed_ssp_intc_ops;
+ aic->irq_table = aspeed_2700ssp_intc_irqs;
+ aic->irq_table_count = ARRAY_SIZE(aspeed_2700ssp_intc_irqs);
+}
+
+static const TypeInfo aspeed_2700ssp_intc_info = {
+ .name = TYPE_ASPEED_2700SSP_INTC,
+ .parent = TYPE_ASPEED_INTC,
+ .class_init = aspeed_2700ssp_intc_class_init,
+};
+
+static AspeedINTCIRQ aspeed_2700ssp_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
+ {0, 0, 1, R_SSPINT160_EN, R_SSPINT160_STATUS},
+ {1, 1, 1, R_SSPINT161_EN, R_SSPINT161_STATUS},
+ {2, 2, 1, R_SSPINT162_EN, R_SSPINT162_STATUS},
+ {3, 3, 1, R_SSPINT163_EN, R_SSPINT163_STATUS},
+ {4, 4, 1, R_SSPINT164_EN, R_SSPINT164_STATUS},
+ {5, 5, 1, R_SSPINT165_EN, R_SSPINT165_STATUS},
+};
+
+static void aspeed_2700ssp_intcio_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
+
+ dc->desc = "ASPEED 2700 SSP INTC IO Controller";
+ aic->num_lines = 32;
+ aic->num_inpins = 6;
+ aic->num_outpins = 6;
+ aic->mem_size = 0x400;
+ aic->nr_regs = 0x1d8 >> 2;
+ aic->reg_offset = 0;
+ aic->reg_ops = &aspeed_ssp_intcio_ops;
+ aic->irq_table = aspeed_2700ssp_intcio_irqs;
+ aic->irq_table_count = ARRAY_SIZE(aspeed_2700ssp_intcio_irqs);
+}
+
+static const TypeInfo aspeed_2700ssp_intcio_info = {
+ .name = TYPE_ASPEED_2700SSP_INTCIO,
+ .parent = TYPE_ASPEED_INTC,
+ .class_init = aspeed_2700ssp_intcio_class_init,
+};
+
static void aspeed_intc_register_types(void)
{
type_register_static(&aspeed_intc_info);
type_register_static(&aspeed_2700_intc_info);
type_register_static(&aspeed_2700_intcio_info);
+ type_register_static(&aspeed_2700ssp_intc_info);
+ type_register_static(&aspeed_2700ssp_intcio_info);
}
type_init(aspeed_intc_register_types);
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 03/13] hw/intc/aspeed: Add support for AST2700 SSP INTC
2025-03-13 5:40 ` [PATCH 03/13] hw/intc/aspeed: Add support for AST2700 SSP INTC Steven Lee via
@ 2025-04-07 15:12 ` Cédric Le Goater
0 siblings, 0 replies; 26+ messages in thread
From: Cédric Le Goater @ 2025-04-07 15:12 UTC (permalink / raw)
To: Steven Lee, Peter Maydell, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
On 3/13/25 06:40, Steven Lee wrote:
> - Define new types for ast2700ssp INTC and INTCIO
> - Add register definitions for SSP INTC and INTCIO
> - Implement write handlers for SSP INTC and INTCIO
> - Register new types in aspeed_intc_register_types
>
> The design of the SSP INTC and INTCIO controllers is similar to
> AST2700, with the following differences:
>
> - AST2700
> Support GICINT128 to GICINT136 in INTC
> The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
> Bit 0 -> GIC 192
> Bit 1 -> GIC 193
> Bit 2 -> GIC 194
> Bit 3 -> GIC 195
> Bit 4 -> GIC 196
>
> - AST2700-ssp
> Support SSPINT128 to SSPINT136 in INTC
> The INTCIO SSPINT_160_169 has 10 output pins, mapped as follows:
> Bit 0 -> SSPINT 160
> Bit 1 -> SSPINT 161
> Bit 2 -> SSPINT 162
> Bit 3 -> SSPINT 163
> Bit 4 -> SSPINT 164
>
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> Change-Id: I5329767b21c0e982d3afcb87c7d1690cc04ce2ef
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> include/hw/intc/aspeed_intc.h | 3 +
> hw/intc/aspeed_intc.c | 211 ++++++++++++++++++++++++++++++++++
> 2 files changed, 214 insertions(+)
>
> diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
> index 3727ba24be..746f159bf3 100644
> --- a/include/hw/intc/aspeed_intc.h
> +++ b/include/hw/intc/aspeed_intc.h
> @@ -15,6 +15,9 @@
> #define TYPE_ASPEED_INTC "aspeed.intc"
> #define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
> #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
> +#define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
> +#define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp"
> +
> OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
>
> #define ASPEED_INTC_MAX_INPINS 10
> diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
> index 3fd417084f..1f8b4d4d36 100644
> --- a/hw/intc/aspeed_intc.c
> +++ b/hw/intc/aspeed_intc.c
> @@ -62,6 +62,50 @@ REG32(GICINT196_STATUS, 0x44)
> REG32(GICINT197_EN, 0x50)
> REG32(GICINT197_STATUS, 0x54)
>
> +/*
> + * SSP INTC Registers
> + */
> +REG32(SSPINT128_EN, 0x2000)
> +REG32(SSPINT128_STATUS, 0x2004)
> +REG32(SSPINT129_EN, 0x2100)
> +REG32(SSPINT129_STATUS, 0x2104)
> +REG32(SSPINT130_EN, 0x2200)
> +REG32(SSPINT130_STATUS, 0x2204)
> +REG32(SSPINT131_EN, 0x2300)
> +REG32(SSPINT131_STATUS, 0x2304)
> +REG32(SSPINT132_EN, 0x2400)
> +REG32(SSPINT132_STATUS, 0x2404)
> +REG32(SSPINT133_EN, 0x2500)
> +REG32(SSPINT133_STATUS, 0x2504)
> +REG32(SSPINT134_EN, 0x2600)
> +REG32(SSPINT134_STATUS, 0x2604)
> +REG32(SSPINT135_EN, 0x2700)
> +REG32(SSPINT135_STATUS, 0x2704)
> +REG32(SSPINT136_EN, 0x2800)
> +REG32(SSPINT136_STATUS, 0x2804)
> +REG32(SSPINT137_EN, 0x2900)
> +REG32(SSPINT137_STATUS, 0x2904)
> +REG32(SSPINT138_EN, 0x2A00)
> +REG32(SSPINT138_STATUS, 0x2A04)
> +REG32(SSPINT160_169_EN, 0x2B00)
> +REG32(SSPINT160_169_STATUS, 0x2B04)
> +
> +/*
> + * SSP INTCIO Registers
> + */
> +REG32(SSPINT160_EN, 0x180)
> +REG32(SSPINT160_STATUS, 0x184)
> +REG32(SSPINT161_EN, 0x190)
> +REG32(SSPINT161_STATUS, 0x194)
> +REG32(SSPINT162_EN, 0x1A0)
> +REG32(SSPINT162_STATUS, 0x1A4)
> +REG32(SSPINT163_EN, 0x1B0)
> +REG32(SSPINT163_STATUS, 0x1B4)
> +REG32(SSPINT164_EN, 0x1C0)
> +REG32(SSPINT164_STATUS, 0x1C4)
> +REG32(SSPINT165_EN, 0x1D0)
> +REG32(SSPINT165_STATUS, 0x1D4)
> +
> static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
> uint32_t reg)
> {
> @@ -452,6 +496,50 @@ static void aspeed_intc_write(void *opaque, hwaddr offset, uint64_t data,
> return;
> }
>
> +static void aspeed_ssp_intc_write(void *opaque, hwaddr offset, uint64_t data,
> + unsigned size)
> +{
> + AspeedINTCState *s = ASPEED_INTC(opaque);
> + const char *name = object_get_typename(OBJECT(s));
> + uint32_t reg = offset >> 2;
> +
> + trace_aspeed_intc_write(name, offset, size, data);
> +
> + switch (reg) {
> + case R_SSPINT128_EN:
> + case R_SSPINT129_EN:
> + case R_SSPINT130_EN:
> + case R_SSPINT131_EN:
> + case R_SSPINT132_EN:
> + case R_SSPINT133_EN:
> + case R_SSPINT134_EN:
> + case R_SSPINT135_EN:
> + case R_SSPINT136_EN:
> + case R_SSPINT160_169_EN:
> + aspeed_intc_enable_handler(s, offset, data);
> + break;
> + case R_SSPINT128_STATUS:
> + case R_SSPINT129_STATUS:
> + case R_SSPINT130_STATUS:
> + case R_SSPINT131_STATUS:
> + case R_SSPINT132_STATUS:
> + case R_SSPINT133_STATUS:
> + case R_SSPINT134_STATUS:
> + case R_SSPINT135_STATUS:
> + case R_SSPINT136_STATUS:
> + aspeed_intc_status_handler(s, offset, data);
> + break;
> + case R_SSPINT160_169_STATUS:
> + aspeed_intc_status_handler_multi_outpins(s, offset, data);
> + break;
> + default:
> + s->regs[reg] = data;
> + break;
> + }
> +
> + return;
> +}
> +
> static uint64_t aspeed_intcio_read(void *opaque, hwaddr offset,
> unsigned int size)
> {
> @@ -500,6 +588,39 @@ static void aspeed_intcio_write(void *opaque, hwaddr offset, uint64_t data,
> return;
> }
>
> +static void aspeed_ssp_intcio_write(void *opaque, hwaddr offset, uint64_t data,
> + unsigned size)
> +{
> + AspeedINTCState *s = ASPEED_INTC(opaque);
> + const char *name = object_get_typename(OBJECT(s));
> + uint32_t reg = offset >> 2;
> +
> + trace_aspeed_intc_write(name, offset, size, data);
> +
> + switch (reg) {
> + case R_SSPINT160_EN:
> + case R_SSPINT161_EN:
> + case R_SSPINT162_EN:
> + case R_SSPINT163_EN:
> + case R_SSPINT164_EN:
> + case R_SSPINT165_EN:
> + aspeed_intc_enable_handler(s, offset, data);
> + break;
> + case R_SSPINT160_STATUS:
> + case R_SSPINT161_STATUS:
> + case R_SSPINT162_STATUS:
> + case R_SSPINT163_STATUS:
> + case R_SSPINT164_STATUS:
> + case R_SSPINT165_STATUS:
> + aspeed_intc_status_handler(s, offset, data);
> + break;
> + default:
> + s->regs[reg] = data;
> + break;
> + }
> +
> + return;
> +}
>
> static const MemoryRegionOps aspeed_intc_ops = {
> .read = aspeed_intc_read,
> @@ -521,6 +642,26 @@ static const MemoryRegionOps aspeed_intcio_ops = {
> }
> };
>
> +static const MemoryRegionOps aspeed_ssp_intc_ops = {
> + .read = aspeed_intc_read,
> + .write = aspeed_ssp_intc_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + }
> +};
> +
> +static const MemoryRegionOps aspeed_ssp_intcio_ops = {
> + .read = aspeed_intcio_read,
> + .write = aspeed_ssp_intcio_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + }
> +};
> +
> static void aspeed_intc_instance_init(Object *obj)
> {
> AspeedINTCState *s = ASPEED_INTC(obj);
> @@ -678,11 +819,81 @@ static const TypeInfo aspeed_2700_intcio_info = {
> .class_init = aspeed_2700_intcio_class_init,
> };
>
> +static AspeedINTCIRQ aspeed_2700ssp_intc_irqs[ASPEED_INTC_MAX_INPINS] = {
> + {0, 0, 10, R_SSPINT160_169_EN, R_SSPINT160_169_STATUS},
> + {1, 10, 1, R_SSPINT128_EN, R_SSPINT128_STATUS},
> + {2, 11, 1, R_SSPINT129_EN, R_SSPINT129_STATUS},
> + {3, 12, 1, R_SSPINT130_EN, R_SSPINT130_STATUS},
> + {4, 13, 1, R_SSPINT131_EN, R_SSPINT131_STATUS},
> + {5, 14, 1, R_SSPINT132_EN, R_SSPINT132_STATUS},
> + {6, 15, 1, R_SSPINT133_EN, R_SSPINT133_STATUS},
> + {7, 16, 1, R_SSPINT134_EN, R_SSPINT134_STATUS},
> + {8, 17, 1, R_SSPINT135_EN, R_SSPINT135_STATUS},
> + {9, 18, 1, R_SSPINT136_EN, R_SSPINT136_STATUS},
> +};
> +
> +static void aspeed_2700ssp_intc_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
> +
> + dc->desc = "ASPEED 2700 SSP INTC Controller";
> + aic->num_lines = 32;
> + aic->num_inpins = 10;
> + aic->num_outpins = 19;
> + aic->mem_size = 0x4000;
> + aic->nr_regs = 0x2B08 >> 2;
> + aic->reg_offset = 0x0;
> + aic->reg_ops = &aspeed_ssp_intc_ops;
> + aic->irq_table = aspeed_2700ssp_intc_irqs;
> + aic->irq_table_count = ARRAY_SIZE(aspeed_2700ssp_intc_irqs);
> +}
> +
> +static const TypeInfo aspeed_2700ssp_intc_info = {
> + .name = TYPE_ASPEED_2700SSP_INTC,
> + .parent = TYPE_ASPEED_INTC,
> + .class_init = aspeed_2700ssp_intc_class_init,
> +};
> +
> +static AspeedINTCIRQ aspeed_2700ssp_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
> + {0, 0, 1, R_SSPINT160_EN, R_SSPINT160_STATUS},
> + {1, 1, 1, R_SSPINT161_EN, R_SSPINT161_STATUS},
> + {2, 2, 1, R_SSPINT162_EN, R_SSPINT162_STATUS},
> + {3, 3, 1, R_SSPINT163_EN, R_SSPINT163_STATUS},
> + {4, 4, 1, R_SSPINT164_EN, R_SSPINT164_STATUS},
> + {5, 5, 1, R_SSPINT165_EN, R_SSPINT165_STATUS},
> +};
> +
> +static void aspeed_2700ssp_intcio_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
> +
> + dc->desc = "ASPEED 2700 SSP INTC IO Controller";
> + aic->num_lines = 32;
> + aic->num_inpins = 6;
> + aic->num_outpins = 6;
> + aic->mem_size = 0x400;
> + aic->nr_regs = 0x1d8 >> 2;
> + aic->reg_offset = 0;
> + aic->reg_ops = &aspeed_ssp_intcio_ops;
> + aic->irq_table = aspeed_2700ssp_intcio_irqs;
> + aic->irq_table_count = ARRAY_SIZE(aspeed_2700ssp_intcio_irqs);
> +}
> +
> +static const TypeInfo aspeed_2700ssp_intcio_info = {
> + .name = TYPE_ASPEED_2700SSP_INTCIO,
> + .parent = TYPE_ASPEED_INTC,
> + .class_init = aspeed_2700ssp_intcio_class_init,
> +};
> +
> static void aspeed_intc_register_types(void)
> {
> type_register_static(&aspeed_intc_info);
> type_register_static(&aspeed_2700_intc_info);
> type_register_static(&aspeed_2700_intcio_info);
> + type_register_static(&aspeed_2700ssp_intc_info);
> + type_register_static(&aspeed_2700ssp_intcio_info);
> }
>
> type_init(aspeed_intc_register_types);
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 04/13] hw/intc/aspeed: Add support for AST2700 TSP INTC
2025-03-13 5:40 [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine Steven Lee via
` (2 preceding siblings ...)
2025-03-13 5:40 ` [PATCH 03/13] hw/intc/aspeed: Add support for AST2700 SSP INTC Steven Lee via
@ 2025-03-13 5:40 ` Steven Lee via
2025-04-07 15:14 ` Cédric Le Goater
2025-03-13 5:40 ` [PATCH 05/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC Steven Lee via
` (9 subsequent siblings)
13 siblings, 1 reply; 26+ messages in thread
From: Steven Lee via @ 2025-03-13 5:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
- Define new types for ast2700tsp INTC and INTCIO
- Add register definitions for TSP INTC and INTCIO
- Implement write handlers for TSP INTC and INTCIO
- Register new types in aspeed_intc_register_types
The design of the TSP INTC and INTCIO controllers is similar to
AST2700, with the following differences:
- AST2700
Support GICINT128 to GICINT136 in INTC
The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196
- AST2700-tsp
Support TSPINT128 to TSPINT136 in INTC
The INTCIO TSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> TSPINT 160
Bit 1 -> TSPINT 161
Bit 2 -> TSPINT 162
Bit 3 -> TSPINT 163
Bit 4 -> TSPINT 164
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: I9e71a8aac400c0cdbd5b78073d0ada79d12a1350
---
include/hw/intc/aspeed_intc.h | 2 +
hw/intc/aspeed_intc.c | 213 ++++++++++++++++++++++++++++++++++
2 files changed, 215 insertions(+)
diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
index 746f159bf3..51288384a5 100644
--- a/include/hw/intc/aspeed_intc.h
+++ b/include/hw/intc/aspeed_intc.h
@@ -17,6 +17,8 @@
#define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
#define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
#define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp"
+#define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp"
+#define TYPE_ASPEED_2700TSP_INTCIO TYPE_ASPEED_INTC "io-ast2700tsp"
OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
index 1f8b4d4d36..9e3bee993f 100644
--- a/hw/intc/aspeed_intc.c
+++ b/hw/intc/aspeed_intc.c
@@ -106,6 +106,51 @@ REG32(SSPINT164_STATUS, 0x1C4)
REG32(SSPINT165_EN, 0x1D0)
REG32(SSPINT165_STATUS, 0x1D4)
+/*
+ * TSP INTC Registers
+ */
+REG32(TSPINT128_EN, 0x3000)
+REG32(TSPINT128_STATUS, 0x3004)
+REG32(TSPINT129_EN, 0x3100)
+REG32(TSPINT129_STATUS, 0x3104)
+REG32(TSPINT130_EN, 0x3200)
+REG32(TSPINT130_STATUS, 0x3204)
+REG32(TSPINT131_EN, 0x3300)
+REG32(TSPINT131_STATUS, 0x3304)
+REG32(TSPINT132_EN, 0x3400)
+REG32(TSPINT132_STATUS, 0x3404)
+REG32(TSPINT133_EN, 0x3500)
+REG32(TSPINT133_STATUS, 0x3504)
+REG32(TSPINT134_EN, 0x3600)
+REG32(TSPINT134_STATUS, 0x3604)
+REG32(TSPINT135_EN, 0x3700)
+REG32(TSPINT135_STATUS, 0x3704)
+REG32(TSPINT136_EN, 0x3800)
+REG32(TSPINT136_STATUS, 0x3804)
+REG32(TSPINT137_EN, 0x3900)
+REG32(TSPINT137_STATUS, 0x3904)
+REG32(TSPINT138_EN, 0x3A00)
+REG32(TSPINT138_STATUS, 0x3A04)
+REG32(TSPINT160_169_EN, 0x3B00)
+REG32(TSPINT160_169_STATUS, 0x3B04)
+
+/*
+ * TSP INTCIO Registers
+ */
+
+REG32(TSPINT160_EN, 0x200)
+REG32(TSPINT160_STATUS, 0x204)
+REG32(TSPINT161_EN, 0x210)
+REG32(TSPINT161_STATUS, 0x214)
+REG32(TSPINT162_EN, 0x220)
+REG32(TSPINT162_STATUS, 0x224)
+REG32(TSPINT163_EN, 0x230)
+REG32(TSPINT163_STATUS, 0x234)
+REG32(TSPINT164_EN, 0x240)
+REG32(TSPINT164_STATUS, 0x244)
+REG32(TSPINT165_EN, 0x250)
+REG32(TSPINT165_STATUS, 0x254)
+
static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
uint32_t reg)
{
@@ -540,6 +585,50 @@ static void aspeed_ssp_intc_write(void *opaque, hwaddr offset, uint64_t data,
return;
}
+static void aspeed_tsp_intc_write(void *opaque, hwaddr offset, uint64_t data,
+ unsigned size)
+{
+ AspeedINTCState *s = ASPEED_INTC(opaque);
+ const char *name = object_get_typename(OBJECT(s));
+ uint32_t reg = offset >> 2;
+
+ trace_aspeed_intc_write(name, offset, size, data);
+
+ switch (reg) {
+ case R_TSPINT128_EN:
+ case R_TSPINT129_EN:
+ case R_TSPINT130_EN:
+ case R_TSPINT131_EN:
+ case R_TSPINT132_EN:
+ case R_TSPINT133_EN:
+ case R_TSPINT134_EN:
+ case R_TSPINT135_EN:
+ case R_TSPINT136_EN:
+ case R_TSPINT160_169_EN:
+ aspeed_intc_enable_handler(s, offset, data);
+ break;
+ case R_TSPINT128_STATUS:
+ case R_TSPINT129_STATUS:
+ case R_TSPINT130_STATUS:
+ case R_TSPINT131_STATUS:
+ case R_TSPINT132_STATUS:
+ case R_TSPINT133_STATUS:
+ case R_TSPINT134_STATUS:
+ case R_TSPINT135_STATUS:
+ case R_TSPINT136_STATUS:
+ aspeed_intc_status_handler(s, offset, data);
+ break;
+ case R_TSPINT160_169_STATUS:
+ aspeed_intc_status_handler_multi_outpins(s, offset, data);
+ break;
+ default:
+ s->regs[reg] = data;
+ break;
+ }
+
+ return;
+}
+
static uint64_t aspeed_intcio_read(void *opaque, hwaddr offset,
unsigned int size)
{
@@ -622,6 +711,40 @@ static void aspeed_ssp_intcio_write(void *opaque, hwaddr offset, uint64_t data,
return;
}
+static void aspeed_tsp_intcio_write(void *opaque, hwaddr offset, uint64_t data,
+ unsigned size)
+{
+ AspeedINTCState *s = ASPEED_INTC(opaque);
+ const char *name = object_get_typename(OBJECT(s));
+ uint32_t reg = offset >> 2;
+
+ trace_aspeed_intc_write(name, offset, size, data);
+
+ switch (reg) {
+ case R_TSPINT160_EN:
+ case R_TSPINT161_EN:
+ case R_TSPINT162_EN:
+ case R_TSPINT163_EN:
+ case R_TSPINT164_EN:
+ case R_TSPINT165_EN:
+ aspeed_intc_enable_handler(s, offset, data);
+ break;
+ case R_TSPINT160_STATUS:
+ case R_TSPINT161_STATUS:
+ case R_TSPINT162_STATUS:
+ case R_TSPINT163_STATUS:
+ case R_TSPINT164_STATUS:
+ case R_TSPINT165_STATUS:
+ aspeed_intc_status_handler(s, offset, data);
+ break;
+ default:
+ s->regs[reg] = data;
+ break;
+ }
+
+ return;
+}
+
static const MemoryRegionOps aspeed_intc_ops = {
.read = aspeed_intc_read,
.write = aspeed_intc_write,
@@ -662,6 +785,26 @@ static const MemoryRegionOps aspeed_ssp_intcio_ops = {
}
};
+static const MemoryRegionOps aspeed_tsp_intc_ops = {
+ .read = aspeed_intc_read,
+ .write = aspeed_tsp_intc_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
+
+static const MemoryRegionOps aspeed_tsp_intcio_ops = {
+ .read = aspeed_intcio_read,
+ .write = aspeed_tsp_intcio_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
+
static void aspeed_intc_instance_init(Object *obj)
{
AspeedINTCState *s = ASPEED_INTC(obj);
@@ -887,6 +1030,74 @@ static const TypeInfo aspeed_2700ssp_intcio_info = {
.class_init = aspeed_2700ssp_intcio_class_init,
};
+static AspeedINTCIRQ aspeed_2700tsp_intc_irqs[ASPEED_INTC_MAX_INPINS] = {
+ {0, 0, 10, R_TSPINT160_169_EN, R_TSPINT160_169_STATUS},
+ {1, 10, 1, R_TSPINT128_EN, R_TSPINT128_STATUS},
+ {2, 11, 1, R_TSPINT129_EN, R_TSPINT129_STATUS},
+ {3, 12, 1, R_TSPINT130_EN, R_TSPINT130_STATUS},
+ {4, 13, 1, R_TSPINT131_EN, R_TSPINT131_STATUS},
+ {5, 14, 1, R_TSPINT132_EN, R_TSPINT132_STATUS},
+ {6, 15, 1, R_TSPINT133_EN, R_TSPINT133_STATUS},
+ {7, 16, 1, R_TSPINT134_EN, R_TSPINT134_STATUS},
+ {8, 17, 1, R_TSPINT135_EN, R_TSPINT135_STATUS},
+ {9, 18, 1, R_TSPINT136_EN, R_TSPINT136_STATUS},
+};
+
+static void aspeed_2700tsp_intc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
+
+ dc->desc = "ASPEED 2700 TSP INTC Controller";
+ aic->num_lines = 32;
+ aic->num_inpins = 10;
+ aic->num_outpins = 19;
+ aic->mem_size = 0x4000;
+ aic->nr_regs = 0x3B08 >> 2;
+ aic->reg_offset = 0;
+ aic->reg_ops = &aspeed_tsp_intc_ops;
+ aic->irq_table = aspeed_2700tsp_intc_irqs;
+ aic->irq_table_count = ARRAY_SIZE(aspeed_2700tsp_intc_irqs);
+}
+
+static const TypeInfo aspeed_2700tsp_intc_info = {
+ .name = TYPE_ASPEED_2700TSP_INTC,
+ .parent = TYPE_ASPEED_INTC,
+ .class_init = aspeed_2700tsp_intc_class_init,
+};
+
+static AspeedINTCIRQ aspeed_2700tsp_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
+ {0, 0, 1, R_TSPINT160_EN, R_TSPINT160_STATUS},
+ {1, 1, 1, R_TSPINT161_EN, R_TSPINT161_STATUS},
+ {2, 2, 1, R_TSPINT162_EN, R_TSPINT162_STATUS},
+ {3, 3, 1, R_TSPINT163_EN, R_TSPINT163_STATUS},
+ {4, 4, 1, R_TSPINT164_EN, R_TSPINT164_STATUS},
+ {5, 5, 1, R_TSPINT165_EN, R_TSPINT165_STATUS},
+};
+
+static void aspeed_2700tsp_intcio_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
+
+ dc->desc = "ASPEED 2700 TSP INTC IO Controller";
+ aic->num_lines = 32;
+ aic->num_inpins = 6;
+ aic->num_outpins = 6;
+ aic->mem_size = 0x400;
+ aic->nr_regs = 0x258 >> 2;
+ aic->reg_offset = 0x0;
+ aic->reg_ops = &aspeed_tsp_intcio_ops;
+ aic->irq_table = aspeed_2700tsp_intcio_irqs;
+ aic->irq_table_count = ARRAY_SIZE(aspeed_2700tsp_intcio_irqs);
+}
+
+static const TypeInfo aspeed_2700tsp_intcio_info = {
+ .name = TYPE_ASPEED_2700TSP_INTCIO,
+ .parent = TYPE_ASPEED_INTC,
+ .class_init = aspeed_2700tsp_intcio_class_init,
+};
+
static void aspeed_intc_register_types(void)
{
type_register_static(&aspeed_intc_info);
@@ -894,6 +1105,8 @@ static void aspeed_intc_register_types(void)
type_register_static(&aspeed_2700_intcio_info);
type_register_static(&aspeed_2700ssp_intc_info);
type_register_static(&aspeed_2700ssp_intcio_info);
+ type_register_static(&aspeed_2700tsp_intc_info);
+ type_register_static(&aspeed_2700tsp_intcio_info);
}
type_init(aspeed_intc_register_types);
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 04/13] hw/intc/aspeed: Add support for AST2700 TSP INTC
2025-03-13 5:40 ` [PATCH 04/13] hw/intc/aspeed: Add support for AST2700 TSP INTC Steven Lee via
@ 2025-04-07 15:14 ` Cédric Le Goater
0 siblings, 0 replies; 26+ messages in thread
From: Cédric Le Goater @ 2025-04-07 15:14 UTC (permalink / raw)
To: Steven Lee, Peter Maydell, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
On 3/13/25 06:40, Steven Lee wrote:
> - Define new types for ast2700tsp INTC and INTCIO
> - Add register definitions for TSP INTC and INTCIO
> - Implement write handlers for TSP INTC and INTCIO
> - Register new types in aspeed_intc_register_types
>
> The design of the TSP INTC and INTCIO controllers is similar to
> AST2700, with the following differences:
>
> - AST2700
> Support GICINT128 to GICINT136 in INTC
> The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
> Bit 0 -> GIC 192
> Bit 1 -> GIC 193
> Bit 2 -> GIC 194
> Bit 3 -> GIC 195
> Bit 4 -> GIC 196
>
> - AST2700-tsp
> Support TSPINT128 to TSPINT136 in INTC
> The INTCIO TSPINT_160_169 has 10 output pins, mapped as follows:
> Bit 0 -> TSPINT 160
> Bit 1 -> TSPINT 161
> Bit 2 -> TSPINT 162
> Bit 3 -> TSPINT 163
> Bit 4 -> TSPINT 164
>
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> Change-Id: I9e71a8aac400c0cdbd5b78073d0ada79d12a1350
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Thanks,
C.
> ---
> include/hw/intc/aspeed_intc.h | 2 +
> hw/intc/aspeed_intc.c | 213 ++++++++++++++++++++++++++++++++++
> 2 files changed, 215 insertions(+)
>
> diff --git a/include/hw/intc/aspeed_intc.h b/include/hw/intc/aspeed_intc.h
> index 746f159bf3..51288384a5 100644
> --- a/include/hw/intc/aspeed_intc.h
> +++ b/include/hw/intc/aspeed_intc.h
> @@ -17,6 +17,8 @@
> #define TYPE_ASPEED_2700_INTCIO TYPE_ASPEED_INTC "io-ast2700"
> #define TYPE_ASPEED_2700SSP_INTC TYPE_ASPEED_INTC "-ast2700ssp"
> #define TYPE_ASPEED_2700SSP_INTCIO TYPE_ASPEED_INTC "io-ast2700ssp"
> +#define TYPE_ASPEED_2700TSP_INTC TYPE_ASPEED_INTC "-ast2700tsp"
> +#define TYPE_ASPEED_2700TSP_INTCIO TYPE_ASPEED_INTC "io-ast2700tsp"
>
> OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
>
> diff --git a/hw/intc/aspeed_intc.c b/hw/intc/aspeed_intc.c
> index 1f8b4d4d36..9e3bee993f 100644
> --- a/hw/intc/aspeed_intc.c
> +++ b/hw/intc/aspeed_intc.c
> @@ -106,6 +106,51 @@ REG32(SSPINT164_STATUS, 0x1C4)
> REG32(SSPINT165_EN, 0x1D0)
> REG32(SSPINT165_STATUS, 0x1D4)
>
> +/*
> + * TSP INTC Registers
> + */
> +REG32(TSPINT128_EN, 0x3000)
> +REG32(TSPINT128_STATUS, 0x3004)
> +REG32(TSPINT129_EN, 0x3100)
> +REG32(TSPINT129_STATUS, 0x3104)
> +REG32(TSPINT130_EN, 0x3200)
> +REG32(TSPINT130_STATUS, 0x3204)
> +REG32(TSPINT131_EN, 0x3300)
> +REG32(TSPINT131_STATUS, 0x3304)
> +REG32(TSPINT132_EN, 0x3400)
> +REG32(TSPINT132_STATUS, 0x3404)
> +REG32(TSPINT133_EN, 0x3500)
> +REG32(TSPINT133_STATUS, 0x3504)
> +REG32(TSPINT134_EN, 0x3600)
> +REG32(TSPINT134_STATUS, 0x3604)
> +REG32(TSPINT135_EN, 0x3700)
> +REG32(TSPINT135_STATUS, 0x3704)
> +REG32(TSPINT136_EN, 0x3800)
> +REG32(TSPINT136_STATUS, 0x3804)
> +REG32(TSPINT137_EN, 0x3900)
> +REG32(TSPINT137_STATUS, 0x3904)
> +REG32(TSPINT138_EN, 0x3A00)
> +REG32(TSPINT138_STATUS, 0x3A04)
> +REG32(TSPINT160_169_EN, 0x3B00)
> +REG32(TSPINT160_169_STATUS, 0x3B04)
> +
> +/*
> + * TSP INTCIO Registers
> + */
> +
> +REG32(TSPINT160_EN, 0x200)
> +REG32(TSPINT160_STATUS, 0x204)
> +REG32(TSPINT161_EN, 0x210)
> +REG32(TSPINT161_STATUS, 0x214)
> +REG32(TSPINT162_EN, 0x220)
> +REG32(TSPINT162_STATUS, 0x224)
> +REG32(TSPINT163_EN, 0x230)
> +REG32(TSPINT163_STATUS, 0x234)
> +REG32(TSPINT164_EN, 0x240)
> +REG32(TSPINT164_STATUS, 0x244)
> +REG32(TSPINT165_EN, 0x250)
> +REG32(TSPINT165_STATUS, 0x254)
> +
> static const AspeedINTCIRQ *aspeed_intc_get_irq(AspeedINTCClass *aic,
> uint32_t reg)
> {
> @@ -540,6 +585,50 @@ static void aspeed_ssp_intc_write(void *opaque, hwaddr offset, uint64_t data,
> return;
> }
>
> +static void aspeed_tsp_intc_write(void *opaque, hwaddr offset, uint64_t data,
> + unsigned size)
> +{
> + AspeedINTCState *s = ASPEED_INTC(opaque);
> + const char *name = object_get_typename(OBJECT(s));
> + uint32_t reg = offset >> 2;
> +
> + trace_aspeed_intc_write(name, offset, size, data);
> +
> + switch (reg) {
> + case R_TSPINT128_EN:
> + case R_TSPINT129_EN:
> + case R_TSPINT130_EN:
> + case R_TSPINT131_EN:
> + case R_TSPINT132_EN:
> + case R_TSPINT133_EN:
> + case R_TSPINT134_EN:
> + case R_TSPINT135_EN:
> + case R_TSPINT136_EN:
> + case R_TSPINT160_169_EN:
> + aspeed_intc_enable_handler(s, offset, data);
> + break;
> + case R_TSPINT128_STATUS:
> + case R_TSPINT129_STATUS:
> + case R_TSPINT130_STATUS:
> + case R_TSPINT131_STATUS:
> + case R_TSPINT132_STATUS:
> + case R_TSPINT133_STATUS:
> + case R_TSPINT134_STATUS:
> + case R_TSPINT135_STATUS:
> + case R_TSPINT136_STATUS:
> + aspeed_intc_status_handler(s, offset, data);
> + break;
> + case R_TSPINT160_169_STATUS:
> + aspeed_intc_status_handler_multi_outpins(s, offset, data);
> + break;
> + default:
> + s->regs[reg] = data;
> + break;
> + }
> +
> + return;
> +}
> +
> static uint64_t aspeed_intcio_read(void *opaque, hwaddr offset,
> unsigned int size)
> {
> @@ -622,6 +711,40 @@ static void aspeed_ssp_intcio_write(void *opaque, hwaddr offset, uint64_t data,
> return;
> }
>
> +static void aspeed_tsp_intcio_write(void *opaque, hwaddr offset, uint64_t data,
> + unsigned size)
> +{
> + AspeedINTCState *s = ASPEED_INTC(opaque);
> + const char *name = object_get_typename(OBJECT(s));
> + uint32_t reg = offset >> 2;
> +
> + trace_aspeed_intc_write(name, offset, size, data);
> +
> + switch (reg) {
> + case R_TSPINT160_EN:
> + case R_TSPINT161_EN:
> + case R_TSPINT162_EN:
> + case R_TSPINT163_EN:
> + case R_TSPINT164_EN:
> + case R_TSPINT165_EN:
> + aspeed_intc_enable_handler(s, offset, data);
> + break;
> + case R_TSPINT160_STATUS:
> + case R_TSPINT161_STATUS:
> + case R_TSPINT162_STATUS:
> + case R_TSPINT163_STATUS:
> + case R_TSPINT164_STATUS:
> + case R_TSPINT165_STATUS:
> + aspeed_intc_status_handler(s, offset, data);
> + break;
> + default:
> + s->regs[reg] = data;
> + break;
> + }
> +
> + return;
> +}
> +
> static const MemoryRegionOps aspeed_intc_ops = {
> .read = aspeed_intc_read,
> .write = aspeed_intc_write,
> @@ -662,6 +785,26 @@ static const MemoryRegionOps aspeed_ssp_intcio_ops = {
> }
> };
>
> +static const MemoryRegionOps aspeed_tsp_intc_ops = {
> + .read = aspeed_intc_read,
> + .write = aspeed_tsp_intc_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + }
> +};
> +
> +static const MemoryRegionOps aspeed_tsp_intcio_ops = {
> + .read = aspeed_intcio_read,
> + .write = aspeed_tsp_intcio_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
> + }
> +};
> +
> static void aspeed_intc_instance_init(Object *obj)
> {
> AspeedINTCState *s = ASPEED_INTC(obj);
> @@ -887,6 +1030,74 @@ static const TypeInfo aspeed_2700ssp_intcio_info = {
> .class_init = aspeed_2700ssp_intcio_class_init,
> };
>
> +static AspeedINTCIRQ aspeed_2700tsp_intc_irqs[ASPEED_INTC_MAX_INPINS] = {
> + {0, 0, 10, R_TSPINT160_169_EN, R_TSPINT160_169_STATUS},
> + {1, 10, 1, R_TSPINT128_EN, R_TSPINT128_STATUS},
> + {2, 11, 1, R_TSPINT129_EN, R_TSPINT129_STATUS},
> + {3, 12, 1, R_TSPINT130_EN, R_TSPINT130_STATUS},
> + {4, 13, 1, R_TSPINT131_EN, R_TSPINT131_STATUS},
> + {5, 14, 1, R_TSPINT132_EN, R_TSPINT132_STATUS},
> + {6, 15, 1, R_TSPINT133_EN, R_TSPINT133_STATUS},
> + {7, 16, 1, R_TSPINT134_EN, R_TSPINT134_STATUS},
> + {8, 17, 1, R_TSPINT135_EN, R_TSPINT135_STATUS},
> + {9, 18, 1, R_TSPINT136_EN, R_TSPINT136_STATUS},
> +};
> +
> +static void aspeed_2700tsp_intc_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
> +
> + dc->desc = "ASPEED 2700 TSP INTC Controller";
> + aic->num_lines = 32;
> + aic->num_inpins = 10;
> + aic->num_outpins = 19;
> + aic->mem_size = 0x4000;
> + aic->nr_regs = 0x3B08 >> 2;
> + aic->reg_offset = 0;
> + aic->reg_ops = &aspeed_tsp_intc_ops;
> + aic->irq_table = aspeed_2700tsp_intc_irqs;
> + aic->irq_table_count = ARRAY_SIZE(aspeed_2700tsp_intc_irqs);
> +}
> +
> +static const TypeInfo aspeed_2700tsp_intc_info = {
> + .name = TYPE_ASPEED_2700TSP_INTC,
> + .parent = TYPE_ASPEED_INTC,
> + .class_init = aspeed_2700tsp_intc_class_init,
> +};
> +
> +static AspeedINTCIRQ aspeed_2700tsp_intcio_irqs[ASPEED_INTC_MAX_INPINS] = {
> + {0, 0, 1, R_TSPINT160_EN, R_TSPINT160_STATUS},
> + {1, 1, 1, R_TSPINT161_EN, R_TSPINT161_STATUS},
> + {2, 2, 1, R_TSPINT162_EN, R_TSPINT162_STATUS},
> + {3, 3, 1, R_TSPINT163_EN, R_TSPINT163_STATUS},
> + {4, 4, 1, R_TSPINT164_EN, R_TSPINT164_STATUS},
> + {5, 5, 1, R_TSPINT165_EN, R_TSPINT165_STATUS},
> +};
> +
> +static void aspeed_2700tsp_intcio_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + AspeedINTCClass *aic = ASPEED_INTC_CLASS(klass);
> +
> + dc->desc = "ASPEED 2700 TSP INTC IO Controller";
> + aic->num_lines = 32;
> + aic->num_inpins = 6;
> + aic->num_outpins = 6;
> + aic->mem_size = 0x400;
> + aic->nr_regs = 0x258 >> 2;
> + aic->reg_offset = 0x0;
> + aic->reg_ops = &aspeed_tsp_intcio_ops;
> + aic->irq_table = aspeed_2700tsp_intcio_irqs;
> + aic->irq_table_count = ARRAY_SIZE(aspeed_2700tsp_intcio_irqs);
> +}
> +
> +static const TypeInfo aspeed_2700tsp_intcio_info = {
> + .name = TYPE_ASPEED_2700TSP_INTCIO,
> + .parent = TYPE_ASPEED_INTC,
> + .class_init = aspeed_2700tsp_intcio_class_init,
> +};
> +
> static void aspeed_intc_register_types(void)
> {
> type_register_static(&aspeed_intc_info);
> @@ -894,6 +1105,8 @@ static void aspeed_intc_register_types(void)
> type_register_static(&aspeed_2700_intcio_info);
> type_register_static(&aspeed_2700ssp_intc_info);
> type_register_static(&aspeed_2700ssp_intcio_info);
> + type_register_static(&aspeed_2700tsp_intc_info);
> + type_register_static(&aspeed_2700tsp_intcio_info);
> }
>
> type_init(aspeed_intc_register_types);
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 05/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC
2025-03-13 5:40 [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine Steven Lee via
` (3 preceding siblings ...)
2025-03-13 5:40 ` [PATCH 04/13] hw/intc/aspeed: Add support for AST2700 TSP INTC Steven Lee via
@ 2025-03-13 5:40 ` Steven Lee via
2025-04-07 15:16 ` Cédric Le Goater
2025-03-13 5:40 ` [PATCH 06/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 " Steven Lee via
` (8 subsequent siblings)
13 siblings, 1 reply; 26+ messages in thread
From: Steven Lee via @ 2025-03-13 5:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
AST2700 SSP(Secondary Service Processor) is a Cortex-M4 coprocessor
The patch adds support for SSP with following update:
- Introduce Aspeed27x0SSPSoCState structure in aspeed_soc.h
- Define memory map and IRQ map for AST27x0 A0 SSP SoC
- Implement initialization and realization functions
- Add support for UART, INTC, and SCU devices
- Map unimplemented devices for IPC and SCUIO
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: If83e752873af393f3b71249176454399de0be40f
---
include/hw/arm/aspeed_soc.h | 14 ++
hw/arm/aspeed_ast27x0-ssp.c | 309 ++++++++++++++++++++++++++++++++++++
hw/arm/meson.build | 1 +
3 files changed, 324 insertions(+)
create mode 100644 hw/arm/aspeed_ast27x0-ssp.c
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index c46ec6302d..83debb5e14 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -145,6 +145,18 @@ struct Aspeed10x0SoCState {
ARMv7MState armv7m;
};
+struct Aspeed27x0SSPSoCState {
+ AspeedSoCState parent;
+ AspeedINTCState intc[2];
+ UnimplementedDeviceState ipc[2];
+ UnimplementedDeviceState scuio;
+
+ ARMv7MState armv7m;
+};
+
+#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
+
#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
@@ -255,6 +267,8 @@ enum {
ASPEED_DEV_SLIIO,
ASPEED_GIC_DIST,
ASPEED_GIC_REDIST,
+ ASPEED_DEV_IPC0,
+ ASPEED_DEV_IPC1,
};
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
new file mode 100644
index 0000000000..88f27b9459
--- /dev/null
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -0,0 +1,309 @@
+/*
+ * ASPEED Ast27x0 SSP SoC
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "exec/address-spaces.h"
+#include "hw/qdev-clock.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+
+#define AST2700_SSP_RAM_SIZE (32 * MiB)
+
+static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
+ [ASPEED_DEV_SRAM] = 0x00000000,
+ [ASPEED_DEV_INTC] = 0x72100000,
+ [ASPEED_DEV_SCU] = 0x72C02000,
+ [ASPEED_DEV_SCUIO] = 0x74C02000,
+ [ASPEED_DEV_UART0] = 0x74C33000,
+ [ASPEED_DEV_UART1] = 0x74C33100,
+ [ASPEED_DEV_UART2] = 0x74C33200,
+ [ASPEED_DEV_UART3] = 0x74C33300,
+ [ASPEED_DEV_UART4] = 0x72C1A000,
+ [ASPEED_DEV_INTCIO] = 0x74C18000,
+ [ASPEED_DEV_IPC0] = 0x72C1C000,
+ [ASPEED_DEV_IPC1] = 0x74C39000,
+ [ASPEED_DEV_UART5] = 0x74C33400,
+ [ASPEED_DEV_UART6] = 0x74C33500,
+ [ASPEED_DEV_UART7] = 0x74C33600,
+ [ASPEED_DEV_UART8] = 0x74C33700,
+ [ASPEED_DEV_UART9] = 0x74C33800,
+ [ASPEED_DEV_UART10] = 0x74C33900,
+ [ASPEED_DEV_UART11] = 0x74C33A00,
+ [ASPEED_DEV_UART12] = 0x74C33B00,
+ [ASPEED_DEV_TIMER1] = 0x72C10000,
+};
+
+static const int aspeed_soc_ast27x0a0ssp_irqmap[] = {
+ [ASPEED_DEV_SCU] = 12,
+ [ASPEED_DEV_UART0] = 132,
+ [ASPEED_DEV_UART1] = 132,
+ [ASPEED_DEV_UART2] = 132,
+ [ASPEED_DEV_UART3] = 132,
+ [ASPEED_DEV_UART4] = 8,
+ [ASPEED_DEV_UART5] = 132,
+ [ASPEED_DEV_UART6] = 140,
+ [ASPEED_DEV_UART7] = 132,
+ [ASPEED_DEV_UART8] = 132,
+ [ASPEED_DEV_UART9] = 132,
+ [ASPEED_DEV_UART10] = 132,
+ [ASPEED_DEV_UART11] = 132,
+ [ASPEED_DEV_UART12] = 132,
+ [ASPEED_DEV_TIMER1] = 16,
+};
+
+/* SSPINT 164 */
+static const int ast2700_ssp132_ssp164_intcmap[] = {
+ [ASPEED_DEV_UART0] = 7,
+ [ASPEED_DEV_UART1] = 8,
+ [ASPEED_DEV_UART2] = 9,
+ [ASPEED_DEV_UART3] = 10,
+ [ASPEED_DEV_UART5] = 11,
+ [ASPEED_DEV_UART6] = 12,
+ [ASPEED_DEV_UART7] = 13,
+ [ASPEED_DEV_UART8] = 14,
+ [ASPEED_DEV_UART9] = 15,
+ [ASPEED_DEV_UART10] = 16,
+ [ASPEED_DEV_UART11] = 17,
+ [ASPEED_DEV_UART12] = 18,
+};
+
+struct nvic_intc_irq_info {
+ int irq;
+ int intc_idx;
+ int orgate_idx;
+ const int *ptr;
+};
+
+static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = {
+ {160, 1, 0, NULL},
+ {161, 1, 1, NULL},
+ {162, 1, 2, NULL},
+ {163, 1, 3, NULL},
+ {164, 1, 4, ast2700_ssp132_ssp164_intcmap},
+ {165, 1, 5, NULL},
+ {166, 1, 6, NULL},
+ {167, 1, 7, NULL},
+ {168, 1, 8, NULL},
+ {169, 1, 9, NULL},
+ {128, 0, 1, NULL},
+ {129, 0, 2, NULL},
+ {130, 0, 3, NULL},
+ {131, 0, 4, NULL},
+ {132, 0, 5, ast2700_ssp132_ssp164_intcmap},
+ {133, 0, 6, NULL},
+ {134, 0, 7, NULL},
+ {135, 0, 8, NULL},
+ {136, 0, 9, NULL},
+};
+
+static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedSoCState *s, int dev)
+{
+ Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(s);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+
+ int or_idx;
+ int idx;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ast2700_ssp_intcmap); i++) {
+ if (sc->irqmap[dev] == ast2700_ssp_intcmap[i].irq) {
+ assert(ast2700_ssp_intcmap[i].ptr);
+ or_idx = ast2700_ssp_intcmap[i].orgate_idx;
+ idx = ast2700_ssp_intcmap[i].intc_idx;
+ return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
+ ast2700_ssp_intcmap[i].ptr[dev]);
+ }
+ }
+
+ return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
+}
+
+static void aspeed_soc_ast27x0a0ssp_init(Object *obj)
+{
+ Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(obj);
+ AspeedSoCState *s = ASPEED_SOC(obj);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ char socname[8];
+ char typename[64];
+ int i;
+
+ if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
+ g_assert_not_reached();
+ }
+
+ object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
+
+ s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
+
+ snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
+ object_initialize_child(obj, "scu", &s->scu, typename);
+ qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
+
+ for (i = 0; i < sc->uarts_num; i++) {
+ object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
+ }
+
+ object_initialize_child(obj, "intc0", &a->intc[0],
+ TYPE_ASPEED_2700SSP_INTC);
+ object_initialize_child(obj, "intc1", &a->intc[1],
+ TYPE_ASPEED_2700SSP_INTCIO);
+
+ object_initialize_child(obj, "timerctrl", &s->timerctrl,
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "ipc0", &a->ipc[0],
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "ipc1", &a->ipc[1],
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "scuio", &a->scuio,
+ TYPE_UNIMPLEMENTED_DEVICE);
+}
+
+static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
+{
+ Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(dev_soc);
+ AspeedSoCState *s = ASPEED_SOC(dev_soc);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ DeviceState *armv7m;
+ Error *err = NULL;
+ g_autofree char *sram_name = NULL;
+ int i;
+
+ if (!clock_has_source(s->sysclk)) {
+ error_setg(errp, "sysclk clock must be wired up by the board code");
+ return;
+ }
+
+ /* AST27X0 SSP Core */
+ armv7m = DEVICE(&a->armv7m);
+ qdev_prop_set_uint32(armv7m, "num-irq", 256);
+ qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc));
+ qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
+ object_property_set_link(OBJECT(&a->armv7m), "memory",
+ OBJECT(s->memory), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
+
+ sram_name = g_strdup_printf("aspeed.dram.%d",
+ CPU(a->armv7m.cpu)->cpu_index);
+
+ if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
+ &err)) {
+ return;
+ }
+ memory_region_add_subregion(s->memory,
+ sc->memmap[ASPEED_DEV_SRAM],
+ &s->sram);
+
+ /* SCU */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
+
+ /* INTC */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
+ return;
+ }
+
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0,
+ sc->memmap[ASPEED_DEV_INTC]);
+
+ /* INTCIO */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) {
+ return;
+ }
+
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0,
+ sc->memmap[ASPEED_DEV_INTCIO]);
+
+ /* irq source orgates -> INTC0 */
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_inpins; i++) {
+ qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
+ qdev_get_gpio_in(DEVICE(&a->intc[0]), i));
+ }
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_outpins; i++) {
+ assert(i < ARRAY_SIZE(ast2700_ssp_intcmap));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
+ qdev_get_gpio_in(DEVICE(&a->armv7m),
+ ast2700_ssp_intcmap[i].irq));
+ }
+ /* irq source orgates -> INTCIO */
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_inpins; i++) {
+ qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0,
+ qdev_get_gpio_in(DEVICE(&a->intc[1]), i));
+ }
+ /* INTCIO -> INTC */
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_outpins; i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
+ qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
+ }
+ /* UART */
+ if (!aspeed_soc_uart_realize(s, errp)) {
+ return;
+ }
+
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->timerctrl),
+ "aspeed.timerctrl",
+ sc->memmap[ASPEED_DEV_TIMER1], 0x200);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[0]),
+ "aspeed.ipc0",
+ sc->memmap[ASPEED_DEV_IPC0], 0x1000);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[1]),
+ "aspeed.ipc1",
+ sc->memmap[ASPEED_DEV_IPC1], 0x1000);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->scuio),
+ "aspeed.scuio",
+ sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
+}
+
+static void aspeed_soc_ast27x0a0ssp_class_init(ObjectClass *klass, void *data)
+{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO: cortex-m4f */
+ NULL
+ };
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
+
+ /* Reason: The Aspeed SoC can only be instantiated from a board */
+ dc->user_creatable = false;
+ dc->realize = aspeed_soc_ast27x0ssp_realize;
+
+ sc->valid_cpu_types = valid_cpu_types;
+ sc->silicon_rev = AST2700_A0_SILICON_REV;
+ sc->sram_size = AST2700_SSP_RAM_SIZE;
+ sc->spis_num = 0;
+ sc->ehcis_num = 0;
+ sc->wdts_num = 0;
+ sc->macs_num = 0;
+ sc->uarts_num = 13;
+ sc->uarts_base = ASPEED_DEV_UART0;
+ sc->irqmap = aspeed_soc_ast27x0a0ssp_irqmap;
+ sc->memmap = aspeed_soc_ast27x0ssp_memmap;
+ sc->num_cpus = 1;
+ sc->get_irq = aspeed_soc_ast27x0ssp_get_irq;
+}
+
+static const TypeInfo aspeed_soc_ast27x0ssp_types[] = {
+ {
+ .name = TYPE_ASPEED27X0SSP_SOC,
+ .parent = TYPE_ASPEED_SOC,
+ .instance_size = sizeof(Aspeed27x0SSPSoCState),
+ .abstract = true,
+ }, {
+ .name = "ast2700ssp-a0",
+ .parent = TYPE_ASPEED27X0SSP_SOC,
+ .instance_init = aspeed_soc_ast27x0a0ssp_init,
+ .class_init = aspeed_soc_ast27x0a0ssp_class_init,
+ },
+};
+
+DEFINE_TYPES(aspeed_soc_ast27x0ssp_types)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index ac473ce7cd..aec0a0b98d 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -44,6 +44,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_soc_common.c',
'aspeed_ast2400.c',
'aspeed_ast2600.c',
+ 'aspeed_ast27x0-ssp.c',
'aspeed_ast10x0.c',
'aspeed_eeprom.c',
'fby35.c'))
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 05/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC
2025-03-13 5:40 ` [PATCH 05/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC Steven Lee via
@ 2025-04-07 15:16 ` Cédric Le Goater
2025-04-08 1:43 ` Steven Lee
0 siblings, 1 reply; 26+ messages in thread
From: Cédric Le Goater @ 2025-04-07 15:16 UTC (permalink / raw)
To: Steven Lee, Peter Maydell, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
On 3/13/25 06:40, Steven Lee wrote:
> AST2700 SSP(Secondary Service Processor) is a Cortex-M4 coprocessor
> The patch adds support for SSP with following update:
>
> - Introduce Aspeed27x0SSPSoCState structure in aspeed_soc.h
> - Define memory map and IRQ map for AST27x0 A0 SSP SoC
> - Implement initialization and realization functions
> - Add support for UART, INTC, and SCU devices
> - Map unimplemented devices for IPC and SCUIO
>
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> Change-Id: If83e752873af393f3b71249176454399de0be40f
I think we should just provide an A1 version of the models.
Thanks,
C.
> ---
> include/hw/arm/aspeed_soc.h | 14 ++
> hw/arm/aspeed_ast27x0-ssp.c | 309 ++++++++++++++++++++++++++++++++++++
> hw/arm/meson.build | 1 +
> 3 files changed, 324 insertions(+)
> create mode 100644 hw/arm/aspeed_ast27x0-ssp.c
>
> diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> index c46ec6302d..83debb5e14 100644
> --- a/include/hw/arm/aspeed_soc.h
> +++ b/include/hw/arm/aspeed_soc.h
> @@ -145,6 +145,18 @@ struct Aspeed10x0SoCState {
> ARMv7MState armv7m;
> };
>
> +struct Aspeed27x0SSPSoCState {
> + AspeedSoCState parent;
> + AspeedINTCState intc[2];
> + UnimplementedDeviceState ipc[2];
> + UnimplementedDeviceState scuio;
> +
> + ARMv7MState armv7m;
> +};
> +
> +#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
> +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
> +
> #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
> OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
>
> @@ -255,6 +267,8 @@ enum {
> ASPEED_DEV_SLIIO,
> ASPEED_GIC_DIST,
> ASPEED_GIC_REDIST,
> + ASPEED_DEV_IPC0,
> + ASPEED_DEV_IPC1,
> };
>
> qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
> diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
> new file mode 100644
> index 0000000000..88f27b9459
> --- /dev/null
> +++ b/hw/arm/aspeed_ast27x0-ssp.c
> @@ -0,0 +1,309 @@
> +/*
> + * ASPEED Ast27x0 SSP SoC
> + *
> + * Copyright (C) 2025 ASPEED Technology Inc.
> + *
> + * This code is licensed under the GPL version 2 or later. See
> + * the COPYING file in the top-level directory.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "exec/address-spaces.h"
> +#include "hw/qdev-clock.h"
> +#include "hw/misc/unimp.h"
> +#include "hw/arm/aspeed_soc.h"
> +
> +#define AST2700_SSP_RAM_SIZE (32 * MiB)
> +
> +static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
> + [ASPEED_DEV_SRAM] = 0x00000000,
> + [ASPEED_DEV_INTC] = 0x72100000,
> + [ASPEED_DEV_SCU] = 0x72C02000,
> + [ASPEED_DEV_SCUIO] = 0x74C02000,
> + [ASPEED_DEV_UART0] = 0x74C33000,
> + [ASPEED_DEV_UART1] = 0x74C33100,
> + [ASPEED_DEV_UART2] = 0x74C33200,
> + [ASPEED_DEV_UART3] = 0x74C33300,
> + [ASPEED_DEV_UART4] = 0x72C1A000,
> + [ASPEED_DEV_INTCIO] = 0x74C18000,
> + [ASPEED_DEV_IPC0] = 0x72C1C000,
> + [ASPEED_DEV_IPC1] = 0x74C39000,
> + [ASPEED_DEV_UART5] = 0x74C33400,
> + [ASPEED_DEV_UART6] = 0x74C33500,
> + [ASPEED_DEV_UART7] = 0x74C33600,
> + [ASPEED_DEV_UART8] = 0x74C33700,
> + [ASPEED_DEV_UART9] = 0x74C33800,
> + [ASPEED_DEV_UART10] = 0x74C33900,
> + [ASPEED_DEV_UART11] = 0x74C33A00,
> + [ASPEED_DEV_UART12] = 0x74C33B00,
> + [ASPEED_DEV_TIMER1] = 0x72C10000,
> +};
> +
> +static const int aspeed_soc_ast27x0a0ssp_irqmap[] = {
> + [ASPEED_DEV_SCU] = 12,
> + [ASPEED_DEV_UART0] = 132,
> + [ASPEED_DEV_UART1] = 132,
> + [ASPEED_DEV_UART2] = 132,
> + [ASPEED_DEV_UART3] = 132,
> + [ASPEED_DEV_UART4] = 8,
> + [ASPEED_DEV_UART5] = 132,
> + [ASPEED_DEV_UART6] = 140,
> + [ASPEED_DEV_UART7] = 132,
> + [ASPEED_DEV_UART8] = 132,
> + [ASPEED_DEV_UART9] = 132,
> + [ASPEED_DEV_UART10] = 132,
> + [ASPEED_DEV_UART11] = 132,
> + [ASPEED_DEV_UART12] = 132,
> + [ASPEED_DEV_TIMER1] = 16,
> +};
> +
> +/* SSPINT 164 */
> +static const int ast2700_ssp132_ssp164_intcmap[] = {
> + [ASPEED_DEV_UART0] = 7,
> + [ASPEED_DEV_UART1] = 8,
> + [ASPEED_DEV_UART2] = 9,
> + [ASPEED_DEV_UART3] = 10,
> + [ASPEED_DEV_UART5] = 11,
> + [ASPEED_DEV_UART6] = 12,
> + [ASPEED_DEV_UART7] = 13,
> + [ASPEED_DEV_UART8] = 14,
> + [ASPEED_DEV_UART9] = 15,
> + [ASPEED_DEV_UART10] = 16,
> + [ASPEED_DEV_UART11] = 17,
> + [ASPEED_DEV_UART12] = 18,
> +};
> +
> +struct nvic_intc_irq_info {
> + int irq;
> + int intc_idx;
> + int orgate_idx;
> + const int *ptr;
> +};
> +
> +static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = {
> + {160, 1, 0, NULL},
> + {161, 1, 1, NULL},
> + {162, 1, 2, NULL},
> + {163, 1, 3, NULL},
> + {164, 1, 4, ast2700_ssp132_ssp164_intcmap},
> + {165, 1, 5, NULL},
> + {166, 1, 6, NULL},
> + {167, 1, 7, NULL},
> + {168, 1, 8, NULL},
> + {169, 1, 9, NULL},
> + {128, 0, 1, NULL},
> + {129, 0, 2, NULL},
> + {130, 0, 3, NULL},
> + {131, 0, 4, NULL},
> + {132, 0, 5, ast2700_ssp132_ssp164_intcmap},
> + {133, 0, 6, NULL},
> + {134, 0, 7, NULL},
> + {135, 0, 8, NULL},
> + {136, 0, 9, NULL},
> +};
> +
> +static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedSoCState *s, int dev)
> +{
> + Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(s);
> + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> +
> + int or_idx;
> + int idx;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(ast2700_ssp_intcmap); i++) {
> + if (sc->irqmap[dev] == ast2700_ssp_intcmap[i].irq) {
> + assert(ast2700_ssp_intcmap[i].ptr);
> + or_idx = ast2700_ssp_intcmap[i].orgate_idx;
> + idx = ast2700_ssp_intcmap[i].intc_idx;
> + return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
> + ast2700_ssp_intcmap[i].ptr[dev]);
> + }
> + }
> +
> + return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
> +}
> +
> +static void aspeed_soc_ast27x0a0ssp_init(Object *obj)
> +{
> + Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(obj);
> + AspeedSoCState *s = ASPEED_SOC(obj);
> + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> + char socname[8];
> + char typename[64];
> + int i;
> +
> + if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
> + g_assert_not_reached();
> + }
> +
> + object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
> +
> + s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
> +
> + snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
> + object_initialize_child(obj, "scu", &s->scu, typename);
> + qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
> +
> + for (i = 0; i < sc->uarts_num; i++) {
> + object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
> + }
> +
> + object_initialize_child(obj, "intc0", &a->intc[0],
> + TYPE_ASPEED_2700SSP_INTC);
> + object_initialize_child(obj, "intc1", &a->intc[1],
> + TYPE_ASPEED_2700SSP_INTCIO);
> +
> + object_initialize_child(obj, "timerctrl", &s->timerctrl,
> + TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "ipc0", &a->ipc[0],
> + TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "ipc1", &a->ipc[1],
> + TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "scuio", &a->scuio,
> + TYPE_UNIMPLEMENTED_DEVICE);
> +}
> +
> +static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
> +{
> + Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(dev_soc);
> + AspeedSoCState *s = ASPEED_SOC(dev_soc);
> + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> + DeviceState *armv7m;
> + Error *err = NULL;
> + g_autofree char *sram_name = NULL;
> + int i;
> +
> + if (!clock_has_source(s->sysclk)) {
> + error_setg(errp, "sysclk clock must be wired up by the board code");
> + return;
> + }
> +
> + /* AST27X0 SSP Core */
> + armv7m = DEVICE(&a->armv7m);
> + qdev_prop_set_uint32(armv7m, "num-irq", 256);
> + qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc));
> + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
> + object_property_set_link(OBJECT(&a->armv7m), "memory",
> + OBJECT(s->memory), &error_abort);
> + sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
> +
> + sram_name = g_strdup_printf("aspeed.dram.%d",
> + CPU(a->armv7m.cpu)->cpu_index);
> +
> + if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
> + &err)) {
> + return;
> + }
> + memory_region_add_subregion(s->memory,
> + sc->memmap[ASPEED_DEV_SRAM],
> + &s->sram);
> +
> + /* SCU */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
> + return;
> + }
> + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
> +
> + /* INTC */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
> + return;
> + }
> +
> + aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0,
> + sc->memmap[ASPEED_DEV_INTC]);
> +
> + /* INTCIO */
> + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) {
> + return;
> + }
> +
> + aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0,
> + sc->memmap[ASPEED_DEV_INTCIO]);
> +
> + /* irq source orgates -> INTC0 */
> + for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_inpins; i++) {
> + qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
> + qdev_get_gpio_in(DEVICE(&a->intc[0]), i));
> + }
> + for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_outpins; i++) {
> + assert(i < ARRAY_SIZE(ast2700_ssp_intcmap));
> + sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
> + qdev_get_gpio_in(DEVICE(&a->armv7m),
> + ast2700_ssp_intcmap[i].irq));
> + }
> + /* irq source orgates -> INTCIO */
> + for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_inpins; i++) {
> + qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0,
> + qdev_get_gpio_in(DEVICE(&a->intc[1]), i));
> + }
> + /* INTCIO -> INTC */
> + for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_outpins; i++) {
> + sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
> + qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
> + }
> + /* UART */
> + if (!aspeed_soc_uart_realize(s, errp)) {
> + return;
> + }
> +
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->timerctrl),
> + "aspeed.timerctrl",
> + sc->memmap[ASPEED_DEV_TIMER1], 0x200);
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[0]),
> + "aspeed.ipc0",
> + sc->memmap[ASPEED_DEV_IPC0], 0x1000);
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[1]),
> + "aspeed.ipc1",
> + sc->memmap[ASPEED_DEV_IPC1], 0x1000);
> + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->scuio),
> + "aspeed.scuio",
> + sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
> +}
> +
> +static void aspeed_soc_ast27x0a0ssp_class_init(ObjectClass *klass, void *data)
> +{
> + static const char * const valid_cpu_types[] = {
> + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO: cortex-m4f */
> + NULL
> + };
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
> +
> + /* Reason: The Aspeed SoC can only be instantiated from a board */
> + dc->user_creatable = false;
> + dc->realize = aspeed_soc_ast27x0ssp_realize;
> +
> + sc->valid_cpu_types = valid_cpu_types;
> + sc->silicon_rev = AST2700_A0_SILICON_REV;
> + sc->sram_size = AST2700_SSP_RAM_SIZE;
> + sc->spis_num = 0;
> + sc->ehcis_num = 0;
> + sc->wdts_num = 0;
> + sc->macs_num = 0;
> + sc->uarts_num = 13;
> + sc->uarts_base = ASPEED_DEV_UART0;
> + sc->irqmap = aspeed_soc_ast27x0a0ssp_irqmap;
> + sc->memmap = aspeed_soc_ast27x0ssp_memmap;
> + sc->num_cpus = 1;
> + sc->get_irq = aspeed_soc_ast27x0ssp_get_irq;
> +}
> +
> +static const TypeInfo aspeed_soc_ast27x0ssp_types[] = {
> + {
> + .name = TYPE_ASPEED27X0SSP_SOC,
> + .parent = TYPE_ASPEED_SOC,
> + .instance_size = sizeof(Aspeed27x0SSPSoCState),
> + .abstract = true,
> + }, {
> + .name = "ast2700ssp-a0",
> + .parent = TYPE_ASPEED27X0SSP_SOC,
> + .instance_init = aspeed_soc_ast27x0a0ssp_init,
> + .class_init = aspeed_soc_ast27x0a0ssp_class_init,
> + },
> +};
> +
> +DEFINE_TYPES(aspeed_soc_ast27x0ssp_types)
> diff --git a/hw/arm/meson.build b/hw/arm/meson.build
> index ac473ce7cd..aec0a0b98d 100644
> --- a/hw/arm/meson.build
> +++ b/hw/arm/meson.build
> @@ -44,6 +44,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
> 'aspeed_soc_common.c',
> 'aspeed_ast2400.c',
> 'aspeed_ast2600.c',
> + 'aspeed_ast27x0-ssp.c',
> 'aspeed_ast10x0.c',
> 'aspeed_eeprom.c',
> 'fby35.c'))
^ permalink raw reply [flat|nested] 26+ messages in thread* RE: [PATCH 05/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC
2025-04-07 15:16 ` Cédric Le Goater
@ 2025-04-08 1:43 ` Steven Lee
0 siblings, 0 replies; 26+ messages in thread
From: Steven Lee @ 2025-04-08 1:43 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Monday, April 7, 2025 11:16 PM
> To: Steven Lee <steven_lee@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Troy Lee <leetroy@gmail.com>; Jamin Lin
> <jamin_lin@aspeedtech.com>; Andrew Jeffery
> <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH 05/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0
> SSP SoC
>
> On 3/13/25 06:40, Steven Lee wrote:
> > AST2700 SSP(Secondary Service Processor) is a Cortex-M4 coprocessor
> > The patch adds support for SSP with following update:
> >
> > - Introduce Aspeed27x0SSPSoCState structure in aspeed_soc.h
> > - Define memory map and IRQ map for AST27x0 A0 SSP SoC
> > - Implement initialization and realization functions
> > - Add support for UART, INTC, and SCU devices
> > - Map unimplemented devices for IPC and SCUIO
> >
> > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > Change-Id: If83e752873af393f3b71249176454399de0be40f
>
> I think we should just provide an A1 version of the models.
>
Hi Cédric,
Thanks for the review. Based on our internal discussion, I will remove A0 in the next patch.
Best regards,
Steven
> > ---
> > include/hw/arm/aspeed_soc.h | 14 ++
> > hw/arm/aspeed_ast27x0-ssp.c | 309
> ++++++++++++++++++++++++++++++++++++
> > hw/arm/meson.build | 1 +
> > 3 files changed, 324 insertions(+)
> > create mode 100644 hw/arm/aspeed_ast27x0-ssp.c
> >
> > diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
> > index c46ec6302d..83debb5e14 100644
> > --- a/include/hw/arm/aspeed_soc.h
> > +++ b/include/hw/arm/aspeed_soc.h
> > @@ -145,6 +145,18 @@ struct Aspeed10x0SoCState {
> > ARMv7MState armv7m;
> > };
> >
> > +struct Aspeed27x0SSPSoCState {
> > + AspeedSoCState parent;
> > + AspeedINTCState intc[2];
> > + UnimplementedDeviceState ipc[2];
> > + UnimplementedDeviceState scuio;
> > +
> > + ARMv7MState armv7m;
> > +};
> > +
> > +#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
> > +OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState,
> ASPEED27X0SSP_SOC)
> > +
> > #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
> > OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState,
> ASPEED10X0_SOC)
> >
> > @@ -255,6 +267,8 @@ enum {
> > ASPEED_DEV_SLIIO,
> > ASPEED_GIC_DIST,
> > ASPEED_GIC_REDIST,
> > + ASPEED_DEV_IPC0,
> > + ASPEED_DEV_IPC1,
> > };
> >
> > qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); diff --git
> > a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c new file
> > mode 100644 index 0000000000..88f27b9459
> > --- /dev/null
> > +++ b/hw/arm/aspeed_ast27x0-ssp.c
> > @@ -0,0 +1,309 @@
> > +/*
> > + * ASPEED Ast27x0 SSP SoC
> > + *
> > + * Copyright (C) 2025 ASPEED Technology Inc.
> > + *
> > + * This code is licensed under the GPL version 2 or later. See
> > + * the COPYING file in the top-level directory.
> > + *
> > + * SPDX-License-Identifier: GPL-2.0-or-later */
> > +
> > +#include "qemu/osdep.h"
> > +#include "qapi/error.h"
> > +#include "exec/address-spaces.h"
> > +#include "hw/qdev-clock.h"
> > +#include "hw/misc/unimp.h"
> > +#include "hw/arm/aspeed_soc.h"
> > +
> > +#define AST2700_SSP_RAM_SIZE (32 * MiB)
> > +
> > +static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
> > + [ASPEED_DEV_SRAM] = 0x00000000,
> > + [ASPEED_DEV_INTC] = 0x72100000,
> > + [ASPEED_DEV_SCU] = 0x72C02000,
> > + [ASPEED_DEV_SCUIO] = 0x74C02000,
> > + [ASPEED_DEV_UART0] = 0x74C33000,
> > + [ASPEED_DEV_UART1] = 0x74C33100,
> > + [ASPEED_DEV_UART2] = 0x74C33200,
> > + [ASPEED_DEV_UART3] = 0x74C33300,
> > + [ASPEED_DEV_UART4] = 0x72C1A000,
> > + [ASPEED_DEV_INTCIO] = 0x74C18000,
> > + [ASPEED_DEV_IPC0] = 0x72C1C000,
> > + [ASPEED_DEV_IPC1] = 0x74C39000,
> > + [ASPEED_DEV_UART5] = 0x74C33400,
> > + [ASPEED_DEV_UART6] = 0x74C33500,
> > + [ASPEED_DEV_UART7] = 0x74C33600,
> > + [ASPEED_DEV_UART8] = 0x74C33700,
> > + [ASPEED_DEV_UART9] = 0x74C33800,
> > + [ASPEED_DEV_UART10] = 0x74C33900,
> > + [ASPEED_DEV_UART11] = 0x74C33A00,
> > + [ASPEED_DEV_UART12] = 0x74C33B00,
> > + [ASPEED_DEV_TIMER1] = 0x72C10000,
> > +};
> > +
> > +static const int aspeed_soc_ast27x0a0ssp_irqmap[] = {
> > + [ASPEED_DEV_SCU] = 12,
> > + [ASPEED_DEV_UART0] = 132,
> > + [ASPEED_DEV_UART1] = 132,
> > + [ASPEED_DEV_UART2] = 132,
> > + [ASPEED_DEV_UART3] = 132,
> > + [ASPEED_DEV_UART4] = 8,
> > + [ASPEED_DEV_UART5] = 132,
> > + [ASPEED_DEV_UART6] = 140,
> > + [ASPEED_DEV_UART7] = 132,
> > + [ASPEED_DEV_UART8] = 132,
> > + [ASPEED_DEV_UART9] = 132,
> > + [ASPEED_DEV_UART10] = 132,
> > + [ASPEED_DEV_UART11] = 132,
> > + [ASPEED_DEV_UART12] = 132,
> > + [ASPEED_DEV_TIMER1] = 16,
> > +};
> > +
> > +/* SSPINT 164 */
> > +static const int ast2700_ssp132_ssp164_intcmap[] = {
> > + [ASPEED_DEV_UART0] = 7,
> > + [ASPEED_DEV_UART1] = 8,
> > + [ASPEED_DEV_UART2] = 9,
> > + [ASPEED_DEV_UART3] = 10,
> > + [ASPEED_DEV_UART5] = 11,
> > + [ASPEED_DEV_UART6] = 12,
> > + [ASPEED_DEV_UART7] = 13,
> > + [ASPEED_DEV_UART8] = 14,
> > + [ASPEED_DEV_UART9] = 15,
> > + [ASPEED_DEV_UART10] = 16,
> > + [ASPEED_DEV_UART11] = 17,
> > + [ASPEED_DEV_UART12] = 18,
> > +};
> > +
> > +struct nvic_intc_irq_info {
> > + int irq;
> > + int intc_idx;
> > + int orgate_idx;
> > + const int *ptr;
> > +};
> > +
> > +static struct nvic_intc_irq_info ast2700_ssp_intcmap[] = {
> > + {160, 1, 0, NULL},
> > + {161, 1, 1, NULL},
> > + {162, 1, 2, NULL},
> > + {163, 1, 3, NULL},
> > + {164, 1, 4, ast2700_ssp132_ssp164_intcmap},
> > + {165, 1, 5, NULL},
> > + {166, 1, 6, NULL},
> > + {167, 1, 7, NULL},
> > + {168, 1, 8, NULL},
> > + {169, 1, 9, NULL},
> > + {128, 0, 1, NULL},
> > + {129, 0, 2, NULL},
> > + {130, 0, 3, NULL},
> > + {131, 0, 4, NULL},
> > + {132, 0, 5, ast2700_ssp132_ssp164_intcmap},
> > + {133, 0, 6, NULL},
> > + {134, 0, 7, NULL},
> > + {135, 0, 8, NULL},
> > + {136, 0, 9, NULL},
> > +};
> > +
> > +static qemu_irq aspeed_soc_ast27x0ssp_get_irq(AspeedSoCState *s, int
> > +dev) {
> > + Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(s);
> > + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> > +
> > + int or_idx;
> > + int idx;
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(ast2700_ssp_intcmap); i++) {
> > + if (sc->irqmap[dev] == ast2700_ssp_intcmap[i].irq) {
> > + assert(ast2700_ssp_intcmap[i].ptr);
> > + or_idx = ast2700_ssp_intcmap[i].orgate_idx;
> > + idx = ast2700_ssp_intcmap[i].intc_idx;
> > + return
> qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
> > +
> ast2700_ssp_intcmap[i].ptr[dev]);
> > + }
> > + }
> > +
> > + return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]); }
> > +
> > +static void aspeed_soc_ast27x0a0ssp_init(Object *obj) {
> > + Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(obj);
> > + AspeedSoCState *s = ASPEED_SOC(obj);
> > + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> > + char socname[8];
> > + char typename[64];
> > + int i;
> > +
> > + if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
> > + g_assert_not_reached();
> > + }
> > +
> > + object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
> > +
> > + s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL,
> > + 0);
> > +
> > + snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
> > + object_initialize_child(obj, "scu", &s->scu, typename);
> > + qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
> > + sc->silicon_rev);
> > +
> > + for (i = 0; i < sc->uarts_num; i++) {
> > + object_initialize_child(obj, "uart[*]", &s->uart[i],
> TYPE_SERIAL_MM);
> > + }
> > +
> > + object_initialize_child(obj, "intc0", &a->intc[0],
> > + TYPE_ASPEED_2700SSP_INTC);
> > + object_initialize_child(obj, "intc1", &a->intc[1],
> > + TYPE_ASPEED_2700SSP_INTCIO);
> > +
> > + object_initialize_child(obj, "timerctrl", &s->timerctrl,
> > + TYPE_UNIMPLEMENTED_DEVICE);
> > + object_initialize_child(obj, "ipc0", &a->ipc[0],
> > + TYPE_UNIMPLEMENTED_DEVICE);
> > + object_initialize_child(obj, "ipc1", &a->ipc[1],
> > + TYPE_UNIMPLEMENTED_DEVICE);
> > + object_initialize_child(obj, "scuio", &a->scuio,
> > + TYPE_UNIMPLEMENTED_DEVICE); }
> > +
> > +static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error
> > +**errp) {
> > + Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(dev_soc);
> > + AspeedSoCState *s = ASPEED_SOC(dev_soc);
> > + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> > + DeviceState *armv7m;
> > + Error *err = NULL;
> > + g_autofree char *sram_name = NULL;
> > + int i;
> > +
> > + if (!clock_has_source(s->sysclk)) {
> > + error_setg(errp, "sysclk clock must be wired up by the board
> code");
> > + return;
> > + }
> > +
> > + /* AST27X0 SSP Core */
> > + armv7m = DEVICE(&a->armv7m);
> > + qdev_prop_set_uint32(armv7m, "num-irq", 256);
> > + qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc));
> > + qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
> > + object_property_set_link(OBJECT(&a->armv7m), "memory",
> > + OBJECT(s->memory), &error_abort);
> > + sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
> > +
> > + sram_name = g_strdup_printf("aspeed.dram.%d",
> > + CPU(a->armv7m.cpu)->cpu_index);
> > +
> > + if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name,
> sc->sram_size,
> > + &err)) {
> > + return;
> > + }
> > + memory_region_add_subregion(s->memory,
> > + sc->memmap[ASPEED_DEV_SRAM],
> > + &s->sram);
> > +
> > + /* SCU */
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
> > + return;
> > + }
> > + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0,
> > + sc->memmap[ASPEED_DEV_SCU]);
> > +
> > + /* INTC */
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
> > + return;
> > + }
> > +
> > + aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0,
> > + sc->memmap[ASPEED_DEV_INTC]);
> > +
> > + /* INTCIO */
> > + if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) {
> > + return;
> > + }
> > +
> > + aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0,
> > + sc->memmap[ASPEED_DEV_INTCIO]);
> > +
> > + /* irq source orgates -> INTC0 */
> > + for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_inpins; i++)
> {
> > + qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
> > + qdev_get_gpio_in(DEVICE(&a->intc[0]),
> i));
> > + }
> > + for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_outpins;
> i++) {
> > + assert(i < ARRAY_SIZE(ast2700_ssp_intcmap));
> > + sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
> > + qdev_get_gpio_in(DEVICE(&a->armv7m),
> > +
> ast2700_ssp_intcmap[i].irq));
> > + }
> > + /* irq source orgates -> INTCIO */
> > + for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_inpins; i++)
> {
> > + qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0,
> > + qdev_get_gpio_in(DEVICE(&a->intc[1]),
> i));
> > + }
> > + /* INTCIO -> INTC */
> > + for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_outpins;
> i++) {
> > + sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
> > +
> qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
> > + }
> > + /* UART */
> > + if (!aspeed_soc_uart_realize(s, errp)) {
> > + return;
> > + }
> > +
> > + aspeed_mmio_map_unimplemented(s,
> SYS_BUS_DEVICE(&s->timerctrl),
> > + "aspeed.timerctrl",
> > +
> sc->memmap[ASPEED_DEV_TIMER1], 0x200);
> > + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[0]),
> > + "aspeed.ipc0",
> > + sc->memmap[ASPEED_DEV_IPC0],
> 0x1000);
> > + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[1]),
> > + "aspeed.ipc1",
> > + sc->memmap[ASPEED_DEV_IPC1],
> 0x1000);
> > + aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->scuio),
> > + "aspeed.scuio",
> > +
> sc->memmap[ASPEED_DEV_SCUIO],
> > +0x1000); }
> > +
> > +static void aspeed_soc_ast27x0a0ssp_class_init(ObjectClass *klass,
> > +void *data) {
> > + static const char * const valid_cpu_types[] = {
> > + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO: cortex-m4f */
> > + NULL
> > + };
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
> > +
> > + /* Reason: The Aspeed SoC can only be instantiated from a board */
> > + dc->user_creatable = false;
> > + dc->realize = aspeed_soc_ast27x0ssp_realize;
> > +
> > + sc->valid_cpu_types = valid_cpu_types;
> > + sc->silicon_rev = AST2700_A0_SILICON_REV;
> > + sc->sram_size = AST2700_SSP_RAM_SIZE;
> > + sc->spis_num = 0;
> > + sc->ehcis_num = 0;
> > + sc->wdts_num = 0;
> > + sc->macs_num = 0;
> > + sc->uarts_num = 13;
> > + sc->uarts_base = ASPEED_DEV_UART0;
> > + sc->irqmap = aspeed_soc_ast27x0a0ssp_irqmap;
> > + sc->memmap = aspeed_soc_ast27x0ssp_memmap;
> > + sc->num_cpus = 1;
> > + sc->get_irq = aspeed_soc_ast27x0ssp_get_irq; }
> > +
> > +static const TypeInfo aspeed_soc_ast27x0ssp_types[] = {
> > + {
> > + .name = TYPE_ASPEED27X0SSP_SOC,
> > + .parent = TYPE_ASPEED_SOC,
> > + .instance_size = sizeof(Aspeed27x0SSPSoCState),
> > + .abstract = true,
> > + }, {
> > + .name = "ast2700ssp-a0",
> > + .parent = TYPE_ASPEED27X0SSP_SOC,
> > + .instance_init = aspeed_soc_ast27x0a0ssp_init,
> > + .class_init = aspeed_soc_ast27x0a0ssp_class_init,
> > + },
> > +};
> > +
> > +DEFINE_TYPES(aspeed_soc_ast27x0ssp_types)
> > diff --git a/hw/arm/meson.build b/hw/arm/meson.build index
> > ac473ce7cd..aec0a0b98d 100644
> > --- a/hw/arm/meson.build
> > +++ b/hw/arm/meson.build
> > @@ -44,6 +44,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true:
> files(
> > 'aspeed_soc_common.c',
> > 'aspeed_ast2400.c',
> > 'aspeed_ast2600.c',
> > + 'aspeed_ast27x0-ssp.c',
> > 'aspeed_ast10x0.c',
> > 'aspeed_eeprom.c',
> > 'fby35.c'))
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 06/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC
2025-03-13 5:40 [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine Steven Lee via
` (4 preceding siblings ...)
2025-03-13 5:40 ` [PATCH 05/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC Steven Lee via
@ 2025-03-13 5:40 ` Steven Lee via
2025-04-07 15:17 ` Cédric Le Goater
2025-03-13 5:40 ` [PATCH 07/13] hw/arm/aspeed_ast27x0-tsp: Introduce AST27x0 A0 TSP SoC Steven Lee via
` (7 subsequent siblings)
13 siblings, 1 reply; 26+ messages in thread
From: Steven Lee via @ 2025-03-13 5:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
The AST2700 SSP (Secondary Service Processor) is a Cortex-M4 coprocessor.
This patch adds support for A1 SSP with the following updates:
- Defined IRQ maps for AST27x0 A1 SSP SoC
- Implemented initialization functions
The IRQ mapping is similar to AST2700 CA35 SoC, featuring a two-level
interrupt controller.
Difference from AST2700:
- AST2700
- Support GICINT128 to GICINT136 in INTC
- The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196
- AST2700-ssp
- Support SSPINT128 to SSPINT136 in INTC
- The INTCIO SSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> SSPINT 160
Bit 1 -> SSPINT 161
Bit 2 -> SSPINT 162
Bit 3 -> SSPINT 163
Bit 4 -> SSPINT 164
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: Ic5121dd78c5dacf1ec4b4e791cc7bf476a8b608f
---
hw/arm/aspeed_ast27x0-ssp.c | 91 +++++++++++++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 88f27b9459..5553190a62 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -60,6 +60,24 @@ static const int aspeed_soc_ast27x0a0ssp_irqmap[] = {
[ASPEED_DEV_TIMER1] = 16,
};
+static const int aspeed_soc_ast27x0a1ssp_irqmap[] = {
+ [ASPEED_DEV_SCU] = 12,
+ [ASPEED_DEV_UART0] = 164,
+ [ASPEED_DEV_UART1] = 164,
+ [ASPEED_DEV_UART2] = 164,
+ [ASPEED_DEV_UART3] = 164,
+ [ASPEED_DEV_UART4] = 8,
+ [ASPEED_DEV_UART5] = 164,
+ [ASPEED_DEV_UART6] = 164,
+ [ASPEED_DEV_UART7] = 164,
+ [ASPEED_DEV_UART8] = 164,
+ [ASPEED_DEV_UART9] = 164,
+ [ASPEED_DEV_UART10] = 164,
+ [ASPEED_DEV_UART11] = 164,
+ [ASPEED_DEV_UART12] = 164,
+ [ASPEED_DEV_TIMER1] = 16,
+};
+
/* SSPINT 164 */
static const int ast2700_ssp132_ssp164_intcmap[] = {
[ASPEED_DEV_UART0] = 7,
@@ -167,6 +185,46 @@ static void aspeed_soc_ast27x0a0ssp_init(Object *obj)
TYPE_UNIMPLEMENTED_DEVICE);
}
+static void aspeed_soc_ast27x0a1ssp_init(Object *obj)
+{
+ Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(obj);
+ AspeedSoCState *s = ASPEED_SOC(obj);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ char socname[8];
+ char typename[64];
+ int i;
+
+ if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
+ g_assert_not_reached();
+ }
+
+ object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
+
+ s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
+
+ snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
+ object_initialize_child(obj, "scu", &s->scu, typename);
+ qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
+
+ for (i = 0; i < sc->uarts_num; i++) {
+ object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
+ }
+
+ object_initialize_child(obj, "intc0", &a->intc[0],
+ TYPE_ASPEED_2700SSP_INTC);
+ object_initialize_child(obj, "intc1", &a->intc[1],
+ TYPE_ASPEED_2700SSP_INTCIO);
+
+ object_initialize_child(obj, "timerctrl", &s->timerctrl,
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "ipc0", &a->ipc[0],
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "ipc1", &a->ipc[1],
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "scuio", &a->scuio,
+ TYPE_UNIMPLEMENTED_DEVICE);
+}
+
static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
{
Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(dev_soc);
@@ -292,6 +350,34 @@ static void aspeed_soc_ast27x0a0ssp_class_init(ObjectClass *klass, void *data)
sc->get_irq = aspeed_soc_ast27x0ssp_get_irq;
}
+static void aspeed_soc_ast27x0a1ssp_class_init(ObjectClass *klass, void *data)
+{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO: cortex-m4f */
+ NULL
+ };
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
+
+ /* Reason: The Aspeed SoC can only be instantiated from a board */
+ dc->user_creatable = false;
+ dc->realize = aspeed_soc_ast27x0ssp_realize;
+
+ sc->valid_cpu_types = valid_cpu_types;
+ sc->silicon_rev = AST2700_A1_SILICON_REV;
+ sc->sram_size = AST2700_SSP_RAM_SIZE;
+ sc->spis_num = 0;
+ sc->ehcis_num = 0;
+ sc->wdts_num = 0;
+ sc->macs_num = 0;
+ sc->uarts_num = 13;
+ sc->uarts_base = ASPEED_DEV_UART0;
+ sc->irqmap = aspeed_soc_ast27x0a1ssp_irqmap;
+ sc->memmap = aspeed_soc_ast27x0ssp_memmap;
+ sc->num_cpus = 1;
+ sc->get_irq = aspeed_soc_ast27x0ssp_get_irq;
+}
+
static const TypeInfo aspeed_soc_ast27x0ssp_types[] = {
{
.name = TYPE_ASPEED27X0SSP_SOC,
@@ -303,6 +389,11 @@ static const TypeInfo aspeed_soc_ast27x0ssp_types[] = {
.parent = TYPE_ASPEED27X0SSP_SOC,
.instance_init = aspeed_soc_ast27x0a0ssp_init,
.class_init = aspeed_soc_ast27x0a0ssp_class_init,
+ }, {
+ .name = "ast2700ssp-a1",
+ .parent = TYPE_ASPEED27X0SSP_SOC,
+ .instance_init = aspeed_soc_ast27x0a1ssp_init,
+ .class_init = aspeed_soc_ast27x0a1ssp_class_init,
},
};
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH 06/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC
2025-03-13 5:40 ` [PATCH 06/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 " Steven Lee via
@ 2025-04-07 15:17 ` Cédric Le Goater
2025-04-08 1:48 ` Steven Lee
0 siblings, 1 reply; 26+ messages in thread
From: Cédric Le Goater @ 2025-04-07 15:17 UTC (permalink / raw)
To: Steven Lee, Peter Maydell, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
On 3/13/25 06:40, Steven Lee wrote:
> The AST2700 SSP (Secondary Service Processor) is a Cortex-M4 coprocessor.
> This patch adds support for A1 SSP with the following updates:
>
> - Defined IRQ maps for AST27x0 A1 SSP SoC
> - Implemented initialization functions
>
> The IRQ mapping is similar to AST2700 CA35 SoC, featuring a two-level
> interrupt controller.
>
> Difference from AST2700:
>
> - AST2700
> - Support GICINT128 to GICINT136 in INTC
> - The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
> Bit 0 -> GIC 192
> Bit 1 -> GIC 193
> Bit 2 -> GIC 194
> Bit 3 -> GIC 195
> Bit 4 -> GIC 196
>
> - AST2700-ssp
> - Support SSPINT128 to SSPINT136 in INTC
> - The INTCIO SSPINT_160_169 has 10 output pins, mapped as follows:
> Bit 0 -> SSPINT 160
> Bit 1 -> SSPINT 161
> Bit 2 -> SSPINT 162
> Bit 3 -> SSPINT 163
> Bit 4 -> SSPINT 164
>
> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> Change-Id: Ic5121dd78c5dacf1ec4b4e791cc7bf476a8b608f
> ---
> hw/arm/aspeed_ast27x0-ssp.c | 91 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 91 insertions(+)
>
> diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
> index 88f27b9459..5553190a62 100644
> --- a/hw/arm/aspeed_ast27x0-ssp.c
> +++ b/hw/arm/aspeed_ast27x0-ssp.c
> @@ -60,6 +60,24 @@ static const int aspeed_soc_ast27x0a0ssp_irqmap[] = {
> [ASPEED_DEV_TIMER1] = 16,
> };
>
> +static const int aspeed_soc_ast27x0a1ssp_irqmap[] = {
> + [ASPEED_DEV_SCU] = 12,
> + [ASPEED_DEV_UART0] = 164,
> + [ASPEED_DEV_UART1] = 164,
> + [ASPEED_DEV_UART2] = 164,
> + [ASPEED_DEV_UART3] = 164,
> + [ASPEED_DEV_UART4] = 8,
> + [ASPEED_DEV_UART5] = 164,
> + [ASPEED_DEV_UART6] = 164,
> + [ASPEED_DEV_UART7] = 164,
> + [ASPEED_DEV_UART8] = 164,
> + [ASPEED_DEV_UART9] = 164,
> + [ASPEED_DEV_UART10] = 164,
> + [ASPEED_DEV_UART11] = 164,
> + [ASPEED_DEV_UART12] = 164,
> + [ASPEED_DEV_TIMER1] = 16,
> +};
> +
> /* SSPINT 164 */
> static const int ast2700_ssp132_ssp164_intcmap[] = {
> [ASPEED_DEV_UART0] = 7,
> @@ -167,6 +185,46 @@ static void aspeed_soc_ast27x0a0ssp_init(Object *obj)
> TYPE_UNIMPLEMENTED_DEVICE);
> }
>
> +static void aspeed_soc_ast27x0a1ssp_init(Object *obj)
> +{
> + Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(obj);
> + AspeedSoCState *s = ASPEED_SOC(obj);
> + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> + char socname[8];
> + char typename[64];
> + int i;
> +
> + if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
> + g_assert_not_reached();
> + }
> +
> + object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
> +
> + s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
> +
> + snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
> + object_initialize_child(obj, "scu", &s->scu, typename);
> + qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
> +
> + for (i = 0; i < sc->uarts_num; i++) {
> + object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
> + }
> +
> + object_initialize_child(obj, "intc0", &a->intc[0],
> + TYPE_ASPEED_2700SSP_INTC);
> + object_initialize_child(obj, "intc1", &a->intc[1],
> + TYPE_ASPEED_2700SSP_INTCIO);
> +
> + object_initialize_child(obj, "timerctrl", &s->timerctrl,
> + TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "ipc0", &a->ipc[0],
> + TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "ipc1", &a->ipc[1],
> + TYPE_UNIMPLEMENTED_DEVICE);
> + object_initialize_child(obj, "scuio", &a->scuio,
> + TYPE_UNIMPLEMENTED_DEVICE);
> +}
> +
> static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
> {
> Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(dev_soc);
> @@ -292,6 +350,34 @@ static void aspeed_soc_ast27x0a0ssp_class_init(ObjectClass *klass, void *data)
> sc->get_irq = aspeed_soc_ast27x0ssp_get_irq;
> }
>
> +static void aspeed_soc_ast27x0a1ssp_class_init(ObjectClass *klass, void *data)
> +{
> + static const char * const valid_cpu_types[] = {
> + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO: cortex-m4f */
> + NULL
> + };
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
> +
> + /* Reason: The Aspeed SoC can only be instantiated from a board */
> + dc->user_creatable = false;
> + dc->realize = aspeed_soc_ast27x0ssp_realize;
> +
> + sc->valid_cpu_types = valid_cpu_types;
> + sc->silicon_rev = AST2700_A1_SILICON_REV;
> + sc->sram_size = AST2700_SSP_RAM_SIZE;
> + sc->spis_num = 0;
> + sc->ehcis_num = 0;
> + sc->wdts_num = 0;
> + sc->macs_num = 0;
> + sc->uarts_num = 13;
> + sc->uarts_base = ASPEED_DEV_UART0;
> + sc->irqmap = aspeed_soc_ast27x0a1ssp_irqmap;
> + sc->memmap = aspeed_soc_ast27x0ssp_memmap;
> + sc->num_cpus = 1;
> + sc->get_irq = aspeed_soc_ast27x0ssp_get_irq;
> +}
> +
> static const TypeInfo aspeed_soc_ast27x0ssp_types[] = {
> {
> .name = TYPE_ASPEED27X0SSP_SOC,
> @@ -303,6 +389,11 @@ static const TypeInfo aspeed_soc_ast27x0ssp_types[] = {
> .parent = TYPE_ASPEED27X0SSP_SOC,
> .instance_init = aspeed_soc_ast27x0a0ssp_init,
> .class_init = aspeed_soc_ast27x0a0ssp_class_init,
> + }, {
> + .name = "ast2700ssp-a1",
> + .parent = TYPE_ASPEED27X0SSP_SOC,
I see you are relying the A0 definitions.
So what's so important in A0 ?
Thanks,
C.
> + .instance_init = aspeed_soc_ast27x0a1ssp_init,
> + .class_init = aspeed_soc_ast27x0a1ssp_class_init,
> },
> };
>
^ permalink raw reply [flat|nested] 26+ messages in thread* RE: [PATCH 06/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC
2025-04-07 15:17 ` Cédric Le Goater
@ 2025-04-08 1:48 ` Steven Lee
0 siblings, 0 replies; 26+ messages in thread
From: Steven Lee @ 2025-04-08 1:48 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Monday, April 7, 2025 11:18 PM
> To: Steven Lee <steven_lee@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Troy Lee <leetroy@gmail.com>; Jamin Lin
> <jamin_lin@aspeedtech.com>; Andrew Jeffery
> <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH 06/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1
> SSP SoC
>
> On 3/13/25 06:40, Steven Lee wrote:
> > The AST2700 SSP (Secondary Service Processor) is a Cortex-M4 coprocessor.
> > This patch adds support for A1 SSP with the following updates:
> >
> > - Defined IRQ maps for AST27x0 A1 SSP SoC
> > - Implemented initialization functions
> >
> > The IRQ mapping is similar to AST2700 CA35 SoC, featuring a two-level
> > interrupt controller.
> >
> > Difference from AST2700:
> >
> > - AST2700
> > - Support GICINT128 to GICINT136 in INTC
> > - The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
> > Bit 0 -> GIC 192
> > Bit 1 -> GIC 193
> > Bit 2 -> GIC 194
> > Bit 3 -> GIC 195
> > Bit 4 -> GIC 196
> >
> > - AST2700-ssp
> > - Support SSPINT128 to SSPINT136 in INTC
> > - The INTCIO SSPINT_160_169 has 10 output pins, mapped as
> follows:
> > Bit 0 -> SSPINT 160
> > Bit 1 -> SSPINT 161
> > Bit 2 -> SSPINT 162
> > Bit 3 -> SSPINT 163
> > Bit 4 -> SSPINT 164
> >
> > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
> > Change-Id: Ic5121dd78c5dacf1ec4b4e791cc7bf476a8b608f
> > ---
> > hw/arm/aspeed_ast27x0-ssp.c | 91
> +++++++++++++++++++++++++++++++++++++
> > 1 file changed, 91 insertions(+)
> >
> > diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
> > index 88f27b9459..5553190a62 100644
> > --- a/hw/arm/aspeed_ast27x0-ssp.c
> > +++ b/hw/arm/aspeed_ast27x0-ssp.c
> > @@ -60,6 +60,24 @@ static const int aspeed_soc_ast27x0a0ssp_irqmap[] = {
> > [ASPEED_DEV_TIMER1] = 16,
> > };
> >
> > +static const int aspeed_soc_ast27x0a1ssp_irqmap[] = {
> > + [ASPEED_DEV_SCU] = 12,
> > + [ASPEED_DEV_UART0] = 164,
> > + [ASPEED_DEV_UART1] = 164,
> > + [ASPEED_DEV_UART2] = 164,
> > + [ASPEED_DEV_UART3] = 164,
> > + [ASPEED_DEV_UART4] = 8,
> > + [ASPEED_DEV_UART5] = 164,
> > + [ASPEED_DEV_UART6] = 164,
> > + [ASPEED_DEV_UART7] = 164,
> > + [ASPEED_DEV_UART8] = 164,
> > + [ASPEED_DEV_UART9] = 164,
> > + [ASPEED_DEV_UART10] = 164,
> > + [ASPEED_DEV_UART11] = 164,
> > + [ASPEED_DEV_UART12] = 164,
> > + [ASPEED_DEV_TIMER1] = 16,
> > +};
> > +
> > /* SSPINT 164 */
> > static const int ast2700_ssp132_ssp164_intcmap[] = {
> > [ASPEED_DEV_UART0] = 7,
> > @@ -167,6 +185,46 @@ static void aspeed_soc_ast27x0a0ssp_init(Object
> *obj)
> > TYPE_UNIMPLEMENTED_DEVICE);
> > }
> >
> > +static void aspeed_soc_ast27x0a1ssp_init(Object *obj) {
> > + Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(obj);
> > + AspeedSoCState *s = ASPEED_SOC(obj);
> > + AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
> > + char socname[8];
> > + char typename[64];
> > + int i;
> > +
> > + if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
> > + g_assert_not_reached();
> > + }
> > +
> > + object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
> > +
> > + s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL,
> > + 0);
> > +
> > + snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
> > + object_initialize_child(obj, "scu", &s->scu, typename);
> > + qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
> > + sc->silicon_rev);
> > +
> > + for (i = 0; i < sc->uarts_num; i++) {
> > + object_initialize_child(obj, "uart[*]", &s->uart[i],
> TYPE_SERIAL_MM);
> > + }
> > +
> > + object_initialize_child(obj, "intc0", &a->intc[0],
> > + TYPE_ASPEED_2700SSP_INTC);
> > + object_initialize_child(obj, "intc1", &a->intc[1],
> > + TYPE_ASPEED_2700SSP_INTCIO);
> > +
> > + object_initialize_child(obj, "timerctrl", &s->timerctrl,
> > + TYPE_UNIMPLEMENTED_DEVICE);
> > + object_initialize_child(obj, "ipc0", &a->ipc[0],
> > + TYPE_UNIMPLEMENTED_DEVICE);
> > + object_initialize_child(obj, "ipc1", &a->ipc[1],
> > + TYPE_UNIMPLEMENTED_DEVICE);
> > + object_initialize_child(obj, "scuio", &a->scuio,
> > + TYPE_UNIMPLEMENTED_DEVICE); }
> > +
> > static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error
> **errp)
> > {
> > Aspeed27x0SSPSoCState *a = ASPEED27X0SSP_SOC(dev_soc); @@
> -292,6
> > +350,34 @@ static void aspeed_soc_ast27x0a0ssp_class_init(ObjectClass
> *klass, void *data)
> > sc->get_irq = aspeed_soc_ast27x0ssp_get_irq;
> > }
> >
> > +static void aspeed_soc_ast27x0a1ssp_class_init(ObjectClass *klass,
> > +void *data) {
> > + static const char * const valid_cpu_types[] = {
> > + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO: cortex-m4f */
> > + NULL
> > + };
> > + DeviceClass *dc = DEVICE_CLASS(klass);
> > + AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
> > +
> > + /* Reason: The Aspeed SoC can only be instantiated from a board */
> > + dc->user_creatable = false;
> > + dc->realize = aspeed_soc_ast27x0ssp_realize;
> > +
> > + sc->valid_cpu_types = valid_cpu_types;
> > + sc->silicon_rev = AST2700_A1_SILICON_REV;
> > + sc->sram_size = AST2700_SSP_RAM_SIZE;
> > + sc->spis_num = 0;
> > + sc->ehcis_num = 0;
> > + sc->wdts_num = 0;
> > + sc->macs_num = 0;
> > + sc->uarts_num = 13;
> > + sc->uarts_base = ASPEED_DEV_UART0;
> > + sc->irqmap = aspeed_soc_ast27x0a1ssp_irqmap;
> > + sc->memmap = aspeed_soc_ast27x0ssp_memmap;
> > + sc->num_cpus = 1;
> > + sc->get_irq = aspeed_soc_ast27x0ssp_get_irq; }
> > +
> > static const TypeInfo aspeed_soc_ast27x0ssp_types[] = {
> > {
> > .name = TYPE_ASPEED27X0SSP_SOC,
> > @@ -303,6 +389,11 @@ static const TypeInfo aspeed_soc_ast27x0ssp_types[]
> = {
> > .parent = TYPE_ASPEED27X0SSP_SOC,
> > .instance_init = aspeed_soc_ast27x0a0ssp_init,
> > .class_init = aspeed_soc_ast27x0a0ssp_class_init,
> > + }, {
> > + .name = "ast2700ssp-a1",
> > + .parent = TYPE_ASPEED27X0SSP_SOC,
>
> I see you are relying the A0 definitions.
>
> So what's so important in A0 ?
>
Hi Cédric,
I reused the initialization function since, aside from the IRQ mapping, there are no functional differences between the A0 and A1 versions.
Best Regards,
Steven
> > + .instance_init = aspeed_soc_ast27x0a1ssp_init,
> > + .class_init = aspeed_soc_ast27x0a1ssp_class_init,
> > },
> > };
> >
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH 07/13] hw/arm/aspeed_ast27x0-tsp: Introduce AST27x0 A0 TSP SoC
2025-03-13 5:40 [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine Steven Lee via
` (5 preceding siblings ...)
2025-03-13 5:40 ` [PATCH 06/13] hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 " Steven Lee via
@ 2025-03-13 5:40 ` Steven Lee via
2025-03-13 5:40 ` [PATCH 08/13] hw/arm/aspeed_ast27x0-tsp: Introduce AST27x0 A1 " Steven Lee via
` (6 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Steven Lee via @ 2025-03-13 5:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
AST2700 TSP(Tertiary Service Processor) is a Cortex-M4 coprocessor
The patch adds support for TSP with following update:
- Introduce Aspeed27x0TSPSoCState structure in aspeed_soc.h
- Define memory map and IRQ map for AST27x0 A0 TSP SoC
- Implement initialization and realization functions
- Add support for UART, INTC, and SCU devices
- Map unimplemented devices for IPC and SCUIO
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: I8ac6e79a2739c76b802a1dfd6c7a7ef357de60a6
---
include/hw/arm/aspeed_soc.h | 12 ++
hw/arm/aspeed_ast27x0-tsp.c | 309 ++++++++++++++++++++++++++++++++++++
hw/arm/meson.build | 1 +
3 files changed, 322 insertions(+)
create mode 100644 hw/arm/aspeed_ast27x0-tsp.c
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 83debb5e14..4369bf6548 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -157,6 +157,18 @@ struct Aspeed27x0SSPSoCState {
#define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
+struct Aspeed27x0TSPSoCState {
+ AspeedSoCState parent;
+ AspeedINTCState intc[2];
+ UnimplementedDeviceState ipc[2];
+ UnimplementedDeviceState scuio;
+
+ ARMv7MState armv7m;
+};
+
+#define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc"
+OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0TSPSoCState, ASPEED27X0TSP_SOC)
+
#define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
new file mode 100644
index 0000000000..ed14af3a6a
--- /dev/null
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -0,0 +1,309 @@
+/*
+ * ASPEED Ast27x0 TSP SoC
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "exec/address-spaces.h"
+#include "hw/qdev-clock.h"
+#include "hw/misc/unimp.h"
+#include "hw/arm/aspeed_soc.h"
+
+#define AST2700_TSP_RAM_SIZE (32 * MiB)
+
+static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
+ [ASPEED_DEV_SRAM] = 0x00000000,
+ [ASPEED_DEV_INTC] = 0x72100000,
+ [ASPEED_DEV_SCU] = 0x72C02000,
+ [ASPEED_DEV_SCUIO] = 0x74C02000,
+ [ASPEED_DEV_UART0] = 0x74C33000,
+ [ASPEED_DEV_UART1] = 0x74C33100,
+ [ASPEED_DEV_UART2] = 0x74C33200,
+ [ASPEED_DEV_UART3] = 0x74C33300,
+ [ASPEED_DEV_UART4] = 0x72C1A000,
+ [ASPEED_DEV_INTCIO] = 0x74C18000,
+ [ASPEED_DEV_IPC0] = 0x72C1C000,
+ [ASPEED_DEV_IPC1] = 0x74C39000,
+ [ASPEED_DEV_UART5] = 0x74C33400,
+ [ASPEED_DEV_UART6] = 0x74C33500,
+ [ASPEED_DEV_UART7] = 0x74C33600,
+ [ASPEED_DEV_UART8] = 0x74C33700,
+ [ASPEED_DEV_UART9] = 0x74C33800,
+ [ASPEED_DEV_UART10] = 0x74C33900,
+ [ASPEED_DEV_UART11] = 0x74C33A00,
+ [ASPEED_DEV_UART12] = 0x74C33B00,
+ [ASPEED_DEV_TIMER1] = 0x72C10000,
+};
+
+static const int aspeed_soc_ast27x0a0tsp_irqmap[] = {
+ [ASPEED_DEV_SCU] = 12,
+ [ASPEED_DEV_UART0] = 132,
+ [ASPEED_DEV_UART1] = 132,
+ [ASPEED_DEV_UART2] = 132,
+ [ASPEED_DEV_UART3] = 132,
+ [ASPEED_DEV_UART4] = 8,
+ [ASPEED_DEV_UART5] = 132,
+ [ASPEED_DEV_UART6] = 132,
+ [ASPEED_DEV_UART7] = 132,
+ [ASPEED_DEV_UART8] = 132,
+ [ASPEED_DEV_UART9] = 132,
+ [ASPEED_DEV_UART10] = 132,
+ [ASPEED_DEV_UART11] = 132,
+ [ASPEED_DEV_UART12] = 132,
+ [ASPEED_DEV_TIMER1] = 16,
+};
+
+/* TSPINT 164 */
+static const int ast2700_tsp132_tsp164_intcmap[] = {
+ [ASPEED_DEV_UART0] = 7,
+ [ASPEED_DEV_UART1] = 8,
+ [ASPEED_DEV_UART2] = 9,
+ [ASPEED_DEV_UART3] = 10,
+ [ASPEED_DEV_UART5] = 11,
+ [ASPEED_DEV_UART6] = 12,
+ [ASPEED_DEV_UART7] = 13,
+ [ASPEED_DEV_UART8] = 14,
+ [ASPEED_DEV_UART9] = 15,
+ [ASPEED_DEV_UART10] = 16,
+ [ASPEED_DEV_UART11] = 17,
+ [ASPEED_DEV_UART12] = 18,
+};
+
+struct nvic_intc_irq_info {
+ int irq;
+ int intc_idx;
+ int orgate_idx;
+ const int *ptr;
+};
+
+static struct nvic_intc_irq_info ast2700_tsp_intcmap[] = {
+ {160, 1, 0, NULL},
+ {161, 1, 1, NULL},
+ {162, 1, 2, NULL},
+ {163, 1, 3, NULL},
+ {164, 1, 4, ast2700_tsp132_tsp164_intcmap},
+ {165, 1, 5, NULL},
+ {166, 1, 6, NULL},
+ {167, 1, 7, NULL},
+ {168, 1, 8, NULL},
+ {169, 1, 9, NULL},
+ {128, 0, 1, NULL},
+ {129, 0, 2, NULL},
+ {130, 0, 3, NULL},
+ {131, 0, 4, NULL},
+ {132, 0, 5, ast2700_tsp132_tsp164_intcmap},
+ {133, 0, 6, NULL},
+ {134, 0, 7, NULL},
+ {135, 0, 8, NULL},
+ {136, 0, 9, NULL},
+};
+
+static qemu_irq aspeed_soc_ast27x0tsp_get_irq(AspeedSoCState *s, int dev)
+{
+ Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(s);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+
+ int or_idx;
+ int idx;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(ast2700_tsp_intcmap); i++) {
+ if (sc->irqmap[dev] == ast2700_tsp_intcmap[i].irq) {
+ assert(ast2700_tsp_intcmap[i].ptr);
+ or_idx = ast2700_tsp_intcmap[i].orgate_idx;
+ idx = ast2700_tsp_intcmap[i].intc_idx;
+ return qdev_get_gpio_in(DEVICE(&a->intc[idx].orgates[or_idx]),
+ ast2700_tsp_intcmap[i].ptr[dev]);
+ }
+ }
+
+ return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]);
+}
+
+static void aspeed_soc_ast27x0a0tsp_init(Object *obj)
+{
+ Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(obj);
+ AspeedSoCState *s = ASPEED_SOC(obj);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ char socname[8];
+ char typename[64];
+ int i;
+
+ if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
+ g_assert_not_reached();
+ }
+
+ object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
+
+ s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
+
+ snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
+ object_initialize_child(obj, "scu", &s->scu, typename);
+ qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
+
+ for (i = 0; i < sc->uarts_num; i++) {
+ object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
+ }
+
+ object_initialize_child(obj, "intc0", &a->intc[0],
+ TYPE_ASPEED_2700TSP_INTC);
+ object_initialize_child(obj, "intc1", &a->intc[1],
+ TYPE_ASPEED_2700TSP_INTCIO);
+
+ object_initialize_child(obj, "timerctrl", &s->timerctrl,
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "ipc0", &a->ipc[0],
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "ipc1", &a->ipc[1],
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "scuio", &a->scuio,
+ TYPE_UNIMPLEMENTED_DEVICE);
+}
+
+static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
+{
+ Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(dev_soc);
+ AspeedSoCState *s = ASPEED_SOC(dev_soc);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ DeviceState *armv7m;
+ Error *err = NULL;
+ g_autofree char *sram_name = NULL;
+ int i;
+
+ if (!clock_has_source(s->sysclk)) {
+ error_setg(errp, "sysclk clock must be wired up by the board code");
+ return;
+ }
+
+ /* AST27X0 TSP Core */
+ armv7m = DEVICE(&a->armv7m);
+ qdev_prop_set_uint32(armv7m, "num-irq", 256);
+ qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc));
+ qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
+ object_property_set_link(OBJECT(&a->armv7m), "memory",
+ OBJECT(s->memory), &error_abort);
+ sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
+
+ sram_name = g_strdup_printf("aspeed.dram.%d",
+ CPU(a->armv7m.cpu)->cpu_index);
+
+ if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size,
+ &err)) {
+ return;
+ }
+ memory_region_add_subregion(s->memory,
+ sc->memmap[ASPEED_DEV_SRAM],
+ &s->sram);
+
+ /* SCU */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
+ return;
+ }
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
+
+ /* INTC */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
+ return;
+ }
+
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[0]), 0,
+ sc->memmap[ASPEED_DEV_INTC]);
+
+ /* INTCIO */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[1]), errp)) {
+ return;
+ }
+
+ aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->intc[1]), 0,
+ sc->memmap[ASPEED_DEV_INTCIO]);
+
+ /* irq source orgates -> INTC */
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_inpins; i++) {
+ qdev_connect_gpio_out(DEVICE(&a->intc[0].orgates[i]), 0,
+ qdev_get_gpio_in(DEVICE(&a->intc[0]), i));
+ }
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[0])->num_outpins; i++) {
+ assert(i < ARRAY_SIZE(ast2700_tsp_intcmap));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[0]), i,
+ qdev_get_gpio_in(DEVICE(&a->armv7m),
+ ast2700_tsp_intcmap[i].irq));
+ }
+ /* irq source orgates -> INTC */
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_inpins; i++) {
+ qdev_connect_gpio_out(DEVICE(&a->intc[1].orgates[i]), 0,
+ qdev_get_gpio_in(DEVICE(&a->intc[1]), i));
+ }
+ /* INTCIO -> INTC */
+ for (i = 0; i < ASPEED_INTC_GET_CLASS(&a->intc[1])->num_outpins; i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
+ qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
+ }
+ /* UART */
+ if (!aspeed_soc_uart_realize(s, errp)) {
+ return;
+ }
+
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->timerctrl),
+ "aspeed.timerctrl",
+ sc->memmap[ASPEED_DEV_TIMER1], 0x200);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[0]),
+ "aspeed.ipc0",
+ sc->memmap[ASPEED_DEV_IPC0], 0x1000);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->ipc[1]),
+ "aspeed.ipc1",
+ sc->memmap[ASPEED_DEV_IPC1], 0x1000);
+ aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&a->scuio),
+ "aspeed.scuio",
+ sc->memmap[ASPEED_DEV_SCUIO], 0x1000);
+}
+
+static void aspeed_soc_ast27x0a0tsp_class_init(ObjectClass *klass, void *data)
+{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
+ NULL
+ };
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
+
+ /* Reason: The Aspeed SoC can only be instantiated from a board */
+ dc->user_creatable = false;
+ dc->realize = aspeed_soc_ast27x0tsp_realize;
+
+ sc->valid_cpu_types = valid_cpu_types;
+ sc->silicon_rev = AST2700_A0_SILICON_REV;
+ sc->sram_size = AST2700_TSP_RAM_SIZE;
+ sc->spis_num = 0;
+ sc->ehcis_num = 0;
+ sc->wdts_num = 0;
+ sc->macs_num = 0;
+ sc->uarts_num = 13;
+ sc->uarts_base = ASPEED_DEV_UART0;
+ sc->irqmap = aspeed_soc_ast27x0a0tsp_irqmap;
+ sc->memmap = aspeed_soc_ast27x0tsp_memmap;
+ sc->num_cpus = 1;
+ sc->get_irq = aspeed_soc_ast27x0tsp_get_irq;
+}
+
+static const TypeInfo aspeed_soc_ast27x0tsp_types[] = {
+ {
+ .name = TYPE_ASPEED27X0TSP_SOC,
+ .parent = TYPE_ASPEED_SOC,
+ .instance_size = sizeof(Aspeed27x0TSPSoCState),
+ .abstract = true,
+ }, {
+ .name = "ast2700tsp-a0",
+ .parent = TYPE_ASPEED27X0TSP_SOC,
+ .instance_init = aspeed_soc_ast27x0a0tsp_init,
+ .class_init = aspeed_soc_ast27x0a0tsp_class_init,
+ },
+};
+
+DEFINE_TYPES(aspeed_soc_ast27x0tsp_types)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index aec0a0b98d..ac6657d3ec 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -45,6 +45,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast2400.c',
'aspeed_ast2600.c',
'aspeed_ast27x0-ssp.c',
+ 'aspeed_ast27x0-tsp.c',
'aspeed_ast10x0.c',
'aspeed_eeprom.c',
'fby35.c'))
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 08/13] hw/arm/aspeed_ast27x0-tsp: Introduce AST27x0 A1 TSP SoC
2025-03-13 5:40 [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine Steven Lee via
` (6 preceding siblings ...)
2025-03-13 5:40 ` [PATCH 07/13] hw/arm/aspeed_ast27x0-tsp: Introduce AST27x0 A0 TSP SoC Steven Lee via
@ 2025-03-13 5:40 ` Steven Lee via
2025-03-13 5:40 ` [PATCH 09/13] hw/arm: Introduce ASPEED AST2700 a0 full core machine Steven Lee via
` (5 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Steven Lee via @ 2025-03-13 5:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
The AST2700 TSP (Tertiary Service Processor) is a Cortex-M4 coprocessor.
This patch adds support for A1 TSP with the following updates:
- Defined IRQ maps for AST27x0 A1 TSP SoC
- Implemented initialization functions
The IRQ mapping is similar to AST2700 CA35 SoC, featuring a two-level
interrupt controller.
Difference from AST2700:
- AST2700
- Support GICINT128 to GICINT136 in INTC
- The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196
- AST2700-tsp
- Support TSPINT128 to TSPINT136 in INTC
- The INTCIO TSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> TSPINT 160
Bit 1 -> TSPINT 161
Bit 2 -> TSPINT 162
Bit 3 -> TSPINT 163
Bit 4 -> TSPINT 164
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: Ia96cc94d10c26b77caf00dd1346565382474e937
---
hw/arm/aspeed_ast27x0-tsp.c | 91 +++++++++++++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index ed14af3a6a..26d4633216 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -60,6 +60,24 @@ static const int aspeed_soc_ast27x0a0tsp_irqmap[] = {
[ASPEED_DEV_TIMER1] = 16,
};
+static const int aspeed_soc_ast27x0a1tsp_irqmap[] = {
+ [ASPEED_DEV_SCU] = 12,
+ [ASPEED_DEV_UART0] = 164,
+ [ASPEED_DEV_UART1] = 164,
+ [ASPEED_DEV_UART2] = 164,
+ [ASPEED_DEV_UART3] = 164,
+ [ASPEED_DEV_UART4] = 8,
+ [ASPEED_DEV_UART5] = 164,
+ [ASPEED_DEV_UART6] = 164,
+ [ASPEED_DEV_UART7] = 164,
+ [ASPEED_DEV_UART8] = 164,
+ [ASPEED_DEV_UART9] = 164,
+ [ASPEED_DEV_UART10] = 164,
+ [ASPEED_DEV_UART11] = 164,
+ [ASPEED_DEV_UART12] = 164,
+ [ASPEED_DEV_TIMER1] = 16,
+};
+
/* TSPINT 164 */
static const int ast2700_tsp132_tsp164_intcmap[] = {
[ASPEED_DEV_UART0] = 7,
@@ -167,6 +185,46 @@ static void aspeed_soc_ast27x0a0tsp_init(Object *obj)
TYPE_UNIMPLEMENTED_DEVICE);
}
+static void aspeed_soc_ast27x0a1tsp_init(Object *obj)
+{
+ Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(obj);
+ AspeedSoCState *s = ASPEED_SOC(obj);
+ AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
+ char socname[8];
+ char typename[64];
+ int i;
+
+ if (sscanf(object_get_typename(obj), "%7s", socname) != 1) {
+ g_assert_not_reached();
+ }
+
+ object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
+
+ s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
+
+ snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
+ object_initialize_child(obj, "scu", &s->scu, typename);
+ qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
+
+ for (i = 0; i < sc->uarts_num; i++) {
+ object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
+ }
+
+ object_initialize_child(obj, "intc0", &a->intc[0],
+ TYPE_ASPEED_2700TSP_INTC);
+ object_initialize_child(obj, "intc1", &a->intc[1],
+ TYPE_ASPEED_2700TSP_INTCIO);
+
+ object_initialize_child(obj, "timerctrl", &s->timerctrl,
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "ipc0", &a->ipc[0],
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "ipc1", &a->ipc[1],
+ TYPE_UNIMPLEMENTED_DEVICE);
+ object_initialize_child(obj, "scuio", &a->scuio,
+ TYPE_UNIMPLEMENTED_DEVICE);
+}
+
static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
{
Aspeed27x0TSPSoCState *a = ASPEED27X0TSP_SOC(dev_soc);
@@ -292,6 +350,34 @@ static void aspeed_soc_ast27x0a0tsp_class_init(ObjectClass *klass, void *data)
sc->get_irq = aspeed_soc_ast27x0tsp_get_irq;
}
+static void aspeed_soc_ast27x0a1tsp_class_init(ObjectClass *klass, void *data)
+{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
+ NULL
+ };
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc);
+
+ /* Reason: The Aspeed SoC can only be instantiated from a board */
+ dc->user_creatable = false;
+ dc->realize = aspeed_soc_ast27x0tsp_realize;
+
+ sc->valid_cpu_types = valid_cpu_types;
+ sc->silicon_rev = AST2700_A1_SILICON_REV;
+ sc->sram_size = AST2700_TSP_RAM_SIZE;
+ sc->spis_num = 0;
+ sc->ehcis_num = 0;
+ sc->wdts_num = 0;
+ sc->macs_num = 0;
+ sc->uarts_num = 13;
+ sc->uarts_base = ASPEED_DEV_UART0;
+ sc->irqmap = aspeed_soc_ast27x0a1tsp_irqmap;
+ sc->memmap = aspeed_soc_ast27x0tsp_memmap;
+ sc->num_cpus = 1;
+ sc->get_irq = aspeed_soc_ast27x0tsp_get_irq;
+}
+
static const TypeInfo aspeed_soc_ast27x0tsp_types[] = {
{
.name = TYPE_ASPEED27X0TSP_SOC,
@@ -303,6 +389,11 @@ static const TypeInfo aspeed_soc_ast27x0tsp_types[] = {
.parent = TYPE_ASPEED27X0TSP_SOC,
.instance_init = aspeed_soc_ast27x0a0tsp_init,
.class_init = aspeed_soc_ast27x0a0tsp_class_init,
+ }, {
+ .name = "ast2700tsp-a1",
+ .parent = TYPE_ASPEED27X0TSP_SOC,
+ .instance_init = aspeed_soc_ast27x0a1tsp_init,
+ .class_init = aspeed_soc_ast27x0a1tsp_class_init,
},
};
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 09/13] hw/arm: Introduce ASPEED AST2700 a0 full core machine
2025-03-13 5:40 [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine Steven Lee via
` (7 preceding siblings ...)
2025-03-13 5:40 ` [PATCH 08/13] hw/arm/aspeed_ast27x0-tsp: Introduce AST27x0 A1 " Steven Lee via
@ 2025-03-13 5:40 ` Steven Lee via
2025-03-13 5:40 ` [PATCH 10/13] hw/arm: Introduce ASPEED AST2700 a1 " Steven Lee via
` (4 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Steven Lee via @ 2025-03-13 5:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
This commit introduces support for the ASPEED AST2700 full core
machine. It includes the initialization of CA35, SSP, and TSP components
with their respective memory regions and clocks. The new file
aspeed_ast27x0-fc.c defines the machine type "ast2700fc-a0" and its
initialization functions. Additionally, the meson.build file is updated
to include the new source file for the ASPEED SoC configuration.
Key features of the machine:
- The first four cores are Cortex-A35 cores.
- CPU 4 is designated as the SSP core (Cortex-M4).
- CPU 5 is designated as the TSP core (Cortex-M4).
Test Step:
- Download ast2700-a0-default-obmc.tar.gz and ast2700-a0-ssp-tsp.tar.gz
from AspeedTech-BMC OpenBmc release page.
- Run the following QEMU command:
```
IMGDIR=~/path/to/image
UBOOT_SIZE=$(stat --format=%s -L ${IMGDIR}/u-boot-nodtb.bin)
./qemu-system-aarch64 -machine ast2700fc-a0 \
-device loader,force-raw=on,addr=0x400000000,file=${IMGDIR}/u-boot-nodtb.bin \
-device loader,force-raw=on,addr=$((0x400000000 + ${UBOOT_SIZE})),file=${IMGDIR}/u-boot.dtb \
-device loader,force-raw=on,addr=0x430000000,file=${IMGDIR}/bl31.bin \
-device loader,force-raw=on,addr=0x430080000,file=${IMGDIR}/tee-raw.bin \
-device loader,cpu-num=0,addr=0x430000000 \
-device loader,cpu-num=1,addr=0x430000000 \
-device loader,cpu-num=2,addr=0x430000000 \
-device loader,cpu-num=3,addr=0x430000000 \
-device loader,file=${IMGDIR}/ast2700-ssp.elf,cpu-num=4 \
-device loader,file=${IMGDIR}/ast2700-tsp.elf,cpu-num=5 \
-drive file=${IMGDIR}/image-bmc,if=mtd,format=raw \
-serial pty -serial pty -serial pty \
-snapshot \
-S -nographic
```
- After starting QEMU, serial devices will be redirected:
char device redirected to /dev/pts/51 (label serial0)
char device redirected to /dev/pts/52 (label serial1)
char device redirected to /dev/pts/53 (label serial2)
- serial0 is the console for the four Cortex-A35 primary processors,
serial1 and serial2 are the consoles for the two Cortex-M4 coprocessors.
- Connect to the consoles using a terminal emulator.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: Ifebfd7a19be0f8bcbebb20b2116f1ea353f422ab
---
hw/arm/aspeed_ast27x0-fc.c | 190 +++++++++++++++++++++++++++++++++++++
hw/arm/meson.build | 4 +-
2 files changed, 193 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/aspeed_ast27x0-fc.c
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
new file mode 100644
index 0000000000..d03a1b5f1e
--- /dev/null
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -0,0 +1,190 @@
+/*
+ * ASPEED SoC 2700 family
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qapi/error.h"
+#include "system/block-backend.h"
+#include "system/system.h"
+#include "hw/arm/aspeed.h"
+#include "hw/boards.h"
+#include "hw/qdev-clock.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/loader.h"
+#include "hw/arm/boot.h"
+#include "hw/block/flash.h"
+
+
+#define TYPE_AST2700A0FC MACHINE_TYPE_NAME("ast2700fc-a0")
+OBJECT_DECLARE_SIMPLE_TYPE(Ast2700a0FCState, AST2700A0FC);
+
+static struct arm_boot_info ast2700fc_board_info = {
+ .board_id = -1, /* device-tree-only board */
+};
+
+struct Ast2700a0FCState {
+ MachineState parent_obj;
+
+ MemoryRegion ca35_memory;
+ MemoryRegion ca35_dram;
+ MemoryRegion ssp_memory;
+ MemoryRegion tsp_memory;
+
+ Clock *ssp_sysclk;
+ Clock *tsp_sysclk;
+
+ Aspeed27x0SoCState ca35;
+ Aspeed27x0SSPSoCState ssp;
+ Aspeed27x0TSPSoCState tsp;
+
+ bool mmio_exec;
+};
+
+#define AST2700FC_BMC_RAM_SIZE (2 * GiB)
+#define AST2700FC_CM4_DRAM_SIZE (32 * MiB)
+
+#define AST2700FC_HW_STRAP1 0x000000C0
+#define AST2700FC_HW_STRAP2 0x00000003
+#define AST2700FC_FMC_MODEL "w25q01jvq"
+#define AST2700FC_SPI_MODEL "w25q512jv"
+
+static void ast2700a0fc_ca35_init(MachineState *machine)
+{
+ Ast2700a0FCState *s = AST2700A0FC(machine);
+ AspeedSoCState *soc;
+ AspeedSoCClass *sc;
+
+ object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a0");
+ soc = ASPEED_SOC(&s->ca35);
+ sc = ASPEED_SOC_GET_CLASS(soc);
+
+ memory_region_init(&s->ca35_memory, OBJECT(&s->ca35), "ca35-memory",
+ UINT64_MAX);
+
+ if (!memory_region_init_ram(&s->ca35_dram, OBJECT(&s->ca35), "ca35-dram",
+ AST2700FC_BMC_RAM_SIZE, &error_abort)) {
+ return;
+ }
+ if (!object_property_set_link(OBJECT(&s->ca35), "memory",
+ OBJECT(&s->ca35_memory),
+ &error_abort)) {
+ return;
+ };
+ if (!object_property_set_link(OBJECT(&s->ca35), "dram",
+ OBJECT(&s->ca35_dram), &error_abort)) {
+ return;
+ }
+ if (!object_property_set_int(OBJECT(&s->ca35), "ram-size",
+ AST2700FC_BMC_RAM_SIZE, &error_abort)) {
+ return;
+ }
+ if (!object_property_set_int(OBJECT(&s->ca35), "hw-strap1",
+ AST2700FC_HW_STRAP1, &error_abort)) {
+ return;
+ }
+ if (!object_property_set_int(OBJECT(&s->ca35), "hw-strap2",
+ AST2700FC_HW_STRAP2, &error_abort)) {
+ return;
+ }
+ aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART12, serial_hd(0));
+ if (!qdev_realize(DEVICE(&s->ca35), NULL, &error_abort)) {
+ return;
+ }
+ /*
+ * AST2700 EVB has a LM75 temperature sensor on I2C bus 0 at address 0x4d.
+ */
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "tmp105", 0x4d);
+
+ aspeed_board_init_flashes(&soc->fmc, AST2700FC_FMC_MODEL, 2, 0);
+ aspeed_board_init_flashes(&soc->spi[0], AST2700FC_SPI_MODEL, 1, 2);
+
+ ast2700fc_board_info.ram_size = machine->ram_size;
+ ast2700fc_board_info.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
+
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info);
+}
+
+static void ast2700a0fc_ssp_init(MachineState *machine)
+{
+ AspeedSoCState *soc;
+ Ast2700a0FCState *s = AST2700A0FC(machine);
+ s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
+ clock_set_hz(s->ssp_sysclk, 200000000ULL);
+
+ object_initialize_child(OBJECT(s), "ssp", &s->ssp, "ast2700ssp-a0");
+ memory_region_init(&s->ssp_memory, OBJECT(&s->ssp), "ssp-memory",
+ UINT64_MAX);
+
+ qdev_connect_clock_in(DEVICE(&s->ssp), "sysclk", s->ssp_sysclk);
+ if (!object_property_set_link(OBJECT(&s->ssp), "memory",
+ OBJECT(&s->ssp_memory), &error_abort)) {
+ return;
+ }
+
+ soc = ASPEED_SOC(&s->ssp);
+ aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART4, serial_hd(1));
+ if (!qdev_realize(DEVICE(&s->ssp), NULL, &error_abort)) {
+ return;
+ }
+}
+
+static void ast2700a0fc_tsp_init(MachineState *machine)
+{
+ AspeedSoCState *soc;
+ Ast2700a0FCState *s = AST2700A0FC(machine);
+ s->tsp_sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");
+ clock_set_hz(s->tsp_sysclk, 200000000ULL);
+
+ object_initialize_child(OBJECT(s), "tsp", &s->tsp, "ast2700tsp-a0");
+ memory_region_init(&s->tsp_memory, OBJECT(&s->tsp), "tsp-memory",
+ UINT64_MAX);
+
+ qdev_connect_clock_in(DEVICE(&s->tsp), "sysclk", s->tsp_sysclk);
+ if (!object_property_set_link(OBJECT(&s->tsp), "memory",
+ OBJECT(&s->tsp_memory), &error_abort)) {
+ return;
+ }
+
+ soc = ASPEED_SOC(&s->tsp);
+ aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART4, serial_hd(2));
+ if (!qdev_realize(DEVICE(&s->tsp), NULL, &error_abort)) {
+ return;
+ }
+}
+
+static void ast2700a0fc_init(MachineState *machine)
+{
+ ast2700a0fc_ca35_init(machine);
+ ast2700a0fc_ssp_init(machine);
+ ast2700a0fc_tsp_init(machine);
+}
+
+static void ast2700a0fc_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->desc = "ast2700-a0 full core support";
+ mc->init = ast2700a0fc_init;
+ mc->no_floppy = 1;
+ mc->no_cdrom = 1;
+ mc->min_cpus = mc->max_cpus = mc->default_cpus = 6;
+}
+
+static const TypeInfo ast2700fc_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("ast2700fc-a0"),
+ .parent = TYPE_MACHINE,
+ .class_init = ast2700a0fc_class_init,
+ .instance_size = sizeof(Ast2700a0FCState),
+ },
+};
+
+DEFINE_TYPES(ast2700fc_types)
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index ac6657d3ec..b0923b45df 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -49,7 +49,9 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast10x0.c',
'aspeed_eeprom.c',
'fby35.c'))
-arm_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files('aspeed_ast27x0.c'))
+arm_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
+ 'aspeed_ast27x0.c',
+ 'aspeed_ast27x0-fc.c'))
arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2.c'))
arm_ss.add(when: 'CONFIG_MPS2', if_true: files('mps2-tz.c'))
arm_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-soc.c'))
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 10/13] hw/arm: Introduce ASPEED AST2700 a1 full core machine
2025-03-13 5:40 [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine Steven Lee via
` (8 preceding siblings ...)
2025-03-13 5:40 ` [PATCH 09/13] hw/arm: Introduce ASPEED AST2700 a0 full core machine Steven Lee via
@ 2025-03-13 5:40 ` Steven Lee via
2025-03-13 5:40 ` [PATCH 11/13] tests/function/aspeed: Add functional test for AST2700FC Steven Lee via
` (3 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Steven Lee via @ 2025-03-13 5:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
- Added new machine type `ast2700fc-a1` with full core support.
- Defined `Ast2700a1FCState` structure for the new machine type.
- Implemented initialization functions for CA35, SSP, and TSP components.
- Updated `ast2700fc_types` to include the new machine type.
- Set machine class properties for `ast2700fc-a1`.
- Add alias `ast2700fc` for a1 machine.
Test Step:
- Download ast2700-default-obmc.tar.gz from AspeedTech-BMC OpenBmc
release page.
- Run the following QEMU command:
```
IMGDIR=~/path/to/image
UBOOT_SIZE=$(stat --format=%s -L ${IMGDIR}/u-boot-nodtb.bin)
./qemu-system-aarch64 -machine ast2700fc \
-device loader,force-raw=on,addr=0x400000000,file=${IMGDIR}/u-boot-nodtb.bin \
-device loader,force-raw=on,addr=$((0x400000000 + ${UBOOT_SIZE})),file=${IMGDIR}/u-boot.dtb \
-device loader,force-raw=on,addr=0x430000000,file=${IMGDIR}/bl31.bin \
-device loader,force-raw=on,addr=0x430080000,file=${IMGDIR}/tee-raw.bin \
-device loader,cpu-num=0,addr=0x430000000 \
-device loader,cpu-num=1,addr=0x430000000 \
-device loader,cpu-num=2,addr=0x430000000 \
-device loader,cpu-num=3,addr=0x430000000 \
-device loader,file=${IMGDIR}/ast2700-ssp.elf,cpu-num=4 \
-device loader,file=${IMGDIR}/ast2700-tsp.elf,cpu-num=5 \
-drive file=${IMGDIR}/image-bmc,if=mtd,format=raw \
-serial pty -serial pty -serial pty \
-snapshot \
-S -nographic
```
- After starting QEMU, serial devices will be redirected:
char device redirected to /dev/pts/51 (label serial0)
char device redirected to /dev/pts/52 (label serial1)
char device redirected to /dev/pts/53 (label serial2)
- serial0 is the console for the four Cortex-A35 primary processors,
serial1 and serial2 are the consoles for the two Cortex-M4 coprocessors.
- Connect to the consoles using a terminal emulator.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: I1e7645a4689859fdd41be2a734909975ba04a1f9
---
hw/arm/aspeed_ast27x0-fc.c | 150 +++++++++++++++++++++++++++++++++++++
1 file changed, 150 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index d03a1b5f1e..1c4895e9d1 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -25,6 +25,8 @@
#define TYPE_AST2700A0FC MACHINE_TYPE_NAME("ast2700fc-a0")
OBJECT_DECLARE_SIMPLE_TYPE(Ast2700a0FCState, AST2700A0FC);
+#define TYPE_AST2700A1FC MACHINE_TYPE_NAME("ast2700fc-a1")
+OBJECT_DECLARE_SIMPLE_TYPE(Ast2700a1FCState, AST2700A1FC);
static struct arm_boot_info ast2700fc_board_info = {
.board_id = -1, /* device-tree-only board */
@@ -48,6 +50,24 @@ struct Ast2700a0FCState {
bool mmio_exec;
};
+struct Ast2700a1FCState {
+ MachineState parent_obj;
+
+ MemoryRegion ca35_memory;
+ MemoryRegion ca35_dram;
+ MemoryRegion ssp_memory;
+ MemoryRegion tsp_memory;
+
+ Clock *ssp_sysclk;
+ Clock *tsp_sysclk;
+
+ Aspeed27x0SoCState ca35;
+ Aspeed27x0SSPSoCState ssp;
+ Aspeed27x0TSPSoCState tsp;
+
+ bool mmio_exec;
+};
+
#define AST2700FC_BMC_RAM_SIZE (2 * GiB)
#define AST2700FC_CM4_DRAM_SIZE (32 * MiB)
@@ -112,6 +132,63 @@ static void ast2700a0fc_ca35_init(MachineState *machine)
arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info);
}
+static void ast2700a1fc_ca35_init(MachineState *machine)
+{
+ Ast2700a1FCState *s = AST2700A1FC(machine);
+ AspeedSoCState *soc;
+ AspeedSoCClass *sc;
+
+ object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a1");
+ soc = ASPEED_SOC(&s->ca35);
+ sc = ASPEED_SOC_GET_CLASS(soc);
+
+ memory_region_init(&s->ca35_memory, OBJECT(&s->ca35), "ca35-memory",
+ UINT64_MAX);
+
+ if (!memory_region_init_ram(&s->ca35_dram, OBJECT(&s->ca35), "ca35-dram",
+ AST2700FC_BMC_RAM_SIZE, &error_abort)) {
+ return;
+ }
+ if (!object_property_set_link(OBJECT(&s->ca35), "memory",
+ OBJECT(&s->ca35_memory),
+ &error_abort)) {
+ return;
+ };
+ if (!object_property_set_link(OBJECT(&s->ca35), "dram",
+ OBJECT(&s->ca35_dram), &error_abort)) {
+ return;
+ }
+ if (!object_property_set_int(OBJECT(&s->ca35), "ram-size",
+ AST2700FC_BMC_RAM_SIZE, &error_abort)) {
+ return;
+ }
+ if (!object_property_set_int(OBJECT(&s->ca35), "hw-strap1",
+ AST2700FC_HW_STRAP1, &error_abort)) {
+ return;
+ }
+ if (!object_property_set_int(OBJECT(&s->ca35), "hw-strap2",
+ AST2700FC_HW_STRAP2, &error_abort)) {
+ return;
+ }
+ aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART12, serial_hd(0));
+ if (!qdev_realize(DEVICE(&s->ca35), NULL, &error_abort)) {
+ return;
+ }
+
+ /*
+ * AST2700 EVB has a LM75 temperature sensor on I2C bus 0 at address 0x4d.
+ */
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "tmp105", 0x4d);
+
+ aspeed_board_init_flashes(&soc->fmc, AST2700FC_FMC_MODEL, 2, 0);
+ aspeed_board_init_flashes(&soc->spi[0], AST2700FC_SPI_MODEL, 1, 2);
+
+ ast2700fc_board_info.ram_size = machine->ram_size;
+ ast2700fc_board_info.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
+
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info);
+}
+
static void ast2700a0fc_ssp_init(MachineState *machine)
{
AspeedSoCState *soc;
@@ -136,6 +213,30 @@ static void ast2700a0fc_ssp_init(MachineState *machine)
}
}
+static void ast2700a1fc_ssp_init(MachineState *machine)
+{
+ AspeedSoCState *soc;
+ Ast2700a1FCState *s = AST2700A1FC(machine);
+ s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
+ clock_set_hz(s->ssp_sysclk, 200000000ULL);
+
+ object_initialize_child(OBJECT(s), "ssp", &s->ssp, "ast2700ssp-a1");
+ memory_region_init(&s->ssp_memory, OBJECT(&s->ssp), "ssp-memory",
+ UINT64_MAX);
+
+ qdev_connect_clock_in(DEVICE(&s->ssp), "sysclk", s->ssp_sysclk);
+ if (!object_property_set_link(OBJECT(&s->ssp), "memory",
+ OBJECT(&s->ssp_memory), &error_abort)) {
+ return;
+ }
+
+ soc = ASPEED_SOC(&s->ssp);
+ aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART4, serial_hd(1));
+ if (!qdev_realize(DEVICE(&s->ssp), NULL, &error_abort)) {
+ return;
+ }
+}
+
static void ast2700a0fc_tsp_init(MachineState *machine)
{
AspeedSoCState *soc;
@@ -160,6 +261,30 @@ static void ast2700a0fc_tsp_init(MachineState *machine)
}
}
+static void ast2700a1fc_tsp_init(MachineState *machine)
+{
+ AspeedSoCState *soc;
+ Ast2700a1FCState *s = AST2700A1FC(machine);
+ s->tsp_sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");
+ clock_set_hz(s->tsp_sysclk, 200000000ULL);
+
+ object_initialize_child(OBJECT(s), "tsp", &s->tsp, "ast2700tsp-a1");
+ memory_region_init(&s->tsp_memory, OBJECT(&s->tsp), "tsp-memory",
+ UINT64_MAX);
+
+ qdev_connect_clock_in(DEVICE(&s->tsp), "sysclk", s->tsp_sysclk);
+ if (!object_property_set_link(OBJECT(&s->tsp), "memory",
+ OBJECT(&s->tsp_memory), &error_abort)) {
+ return;
+ }
+
+ soc = ASPEED_SOC(&s->tsp);
+ aspeed_soc_uart_set_chr(soc, ASPEED_DEV_UART7, serial_hd(2));
+ if (!qdev_realize(DEVICE(&s->tsp), NULL, &error_abort)) {
+ return;
+ }
+}
+
static void ast2700a0fc_init(MachineState *machine)
{
ast2700a0fc_ca35_init(machine);
@@ -167,6 +292,13 @@ static void ast2700a0fc_init(MachineState *machine)
ast2700a0fc_tsp_init(machine);
}
+static void ast2700a1fc_init(MachineState *machine)
+{
+ ast2700a1fc_ca35_init(machine);
+ ast2700a1fc_ssp_init(machine);
+ ast2700a1fc_tsp_init(machine);
+}
+
static void ast2700a0fc_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -178,6 +310,18 @@ static void ast2700a0fc_class_init(ObjectClass *oc, void *data)
mc->min_cpus = mc->max_cpus = mc->default_cpus = 6;
}
+static void ast2700a1fc_class_init(ObjectClass *oc, void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
+ mc->alias = "ast2700fc";
+ mc->desc = "ast2700-a1 full core support";
+ mc->init = ast2700a1fc_init;
+ mc->no_floppy = 1;
+ mc->no_cdrom = 1;
+ mc->min_cpus = mc->max_cpus = mc->default_cpus = 6;
+}
+
static const TypeInfo ast2700fc_types[] = {
{
.name = MACHINE_TYPE_NAME("ast2700fc-a0"),
@@ -185,6 +329,12 @@ static const TypeInfo ast2700fc_types[] = {
.class_init = ast2700a0fc_class_init,
.instance_size = sizeof(Ast2700a0FCState),
},
+ {
+ .name = MACHINE_TYPE_NAME("ast2700fc-a1"),
+ .parent = TYPE_MACHINE,
+ .class_init = ast2700a1fc_class_init,
+ .instance_size = sizeof(Ast2700a1FCState),
+ },
};
DEFINE_TYPES(ast2700fc_types)
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 11/13] tests/function/aspeed: Add functional test for AST2700FC
2025-03-13 5:40 [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine Steven Lee via
` (9 preceding siblings ...)
2025-03-13 5:40 ` [PATCH 10/13] hw/arm: Introduce ASPEED AST2700 a1 " Steven Lee via
@ 2025-03-13 5:40 ` Steven Lee via
2025-03-13 5:40 ` [PATCH 12/13] tests/function/aspeed: Add functional test for AST2700FC A1 Steven Lee via
` (2 subsequent siblings)
13 siblings, 0 replies; 26+ messages in thread
From: Steven Lee via @ 2025-03-13 5:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
Introduce a new functional test for AST2700 multi-SoCs.
The test includes booting ast2700 with bmc image on
ca35 cores and booting ssp/tsp firmware on cm4 cores.
Assets for SDK and SSP/TSP images are downloaded from
AspeedTech-BMC's OpenBmc release page.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: I95807c8a49ee92d3a9978b1a533e10fcdfd64597
---
tests/functional/test_aarch64_ast2700fc.py | 139 +++++++++++++++++++++
1 file changed, 139 insertions(+)
create mode 100755 tests/functional/test_aarch64_ast2700fc.py
diff --git a/tests/functional/test_aarch64_ast2700fc.py b/tests/functional/test_aarch64_ast2700fc.py
new file mode 100755
index 0000000000..243b74d77e
--- /dev/null
+++ b/tests/functional/test_aarch64_ast2700fc.py
@@ -0,0 +1,139 @@
+#!/usr/bin/env python3
+#
+# Functional test that boots the AST2700 multi-SoCs with firmware
+#
+# Copyright (C) 2025 ASPEED Technology Inc
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+import os
+
+from qemu_test import QemuSystemTest, Asset
+from qemu_test import wait_for_console_pattern
+from qemu_test import exec_command_and_wait_for_pattern
+
+
+class AST2700fcMachineSDK(QemuSystemTest):
+ ASSET_SDK_V905_AST2700_A0 = Asset(
+ 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.05/ast2700-a0-default-obmc.tar.gz',
+ 'cfbbd1cce72f2a3b73b9080c41eecdadebb7077fba4f7806d72ac99f3e84b74a')
+ ASSET_SDK_SSP_TSP_AST2700_A0 = Asset(
+ 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.05/ast2700-a0-ssp-tsp.tar.gz',
+ 'a3ca348bd1cb39086f9fdc40eab293afead351925a46f9ab0da4dcc3a1157382')
+
+ def do_test_aarch64_ast2700fc_ca35_start(self, image):
+ self.require_netdev('user')
+ self.vm.set_console()
+ self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw',
+ '-net', 'nic', '-net', 'user', '-snapshot')
+
+ self.vm.launch()
+
+ wait_for_console_pattern(self, 'U-Boot 2023.10')
+ wait_for_console_pattern(self, '## Loading kernel from FIT Image')
+ wait_for_console_pattern(self, 'Starting kernel ...')
+
+ def do_test_aarch64_ast2700fc_ssp_start(self):
+
+ self.vm.shutdown()
+ self.vm.set_console(console_index=1)
+ self.vm.launch()
+
+ def do_test_aarch64_ast2700fc_tsp_start(self):
+ self.vm.shutdown()
+ self.vm.set_console(console_index=2)
+ self.vm.launch()
+
+ def start_ast2700fc_test(self, name):
+ ca35_core = 4
+ uboot_size = os.path.getsize(self.scratch_file(name,
+ 'u-boot-nodtb.bin'))
+ uboot_dtb_load_addr = hex(0x400000000 + uboot_size)
+
+ load_images_list = [
+ {
+ 'addr': '0x400000000',
+ 'file': self.scratch_file(name,
+ 'u-boot-nodtb.bin')
+ },
+ {
+ 'addr': str(uboot_dtb_load_addr),
+ 'file': self.scratch_file(name, 'u-boot.dtb')
+ },
+ {
+ 'addr': '0x430000000',
+ 'file': self.scratch_file(name, 'bl31.bin')
+ },
+ {
+ 'addr': '0x430080000',
+ 'file': self.scratch_file(name, 'optee',
+ 'tee-raw.bin')
+ }
+ ]
+
+ for load_image in load_images_list:
+ addr = load_image['addr']
+ file = load_image['file']
+ self.vm.add_args('-device',
+ f'loader,force-raw=on,addr={addr},file={file}')
+
+ for i in range(ca35_core):
+ self.vm.add_args('-device',
+ f'loader,addr=0x430000000,cpu-num={i}')
+
+ load_elf_list = {
+ 'ssp': self.scratch_file('ast2700-a0-ssp-tsp', 'ast2700-ssp.elf'),
+ 'tsp': self.scratch_file('ast2700-a0-ssp-tsp', 'ast2700-tsp.elf')
+ }
+
+ for cpu_num, key in enumerate(load_elf_list, start=4):
+ file = load_elf_list[key]
+ self.vm.add_args('-device',
+ f'loader,file={file},cpu-num={cpu_num}')
+
+ self.vm.add_args('-device',
+ 'tmp105,bus=aspeed.i2c.bus.1,address=0x4d,id=tmp-test')
+ self.do_test_aarch64_ast2700fc_ca35_start(
+ self.scratch_file(name, 'image-bmc'))
+
+ wait_for_console_pattern(self, f'{name} login:')
+
+ exec_command_and_wait_for_pattern(self, 'root', 'Password:')
+ exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~#')
+
+ exec_command_and_wait_for_pattern(
+ self,
+ 'echo lm75 0x4d > /sys/class/i2c-dev/i2c-1/device/new_device ',
+ 'i2c i2c-1: new_device: Instantiated device lm75 at 0x4d')
+ exec_command_and_wait_for_pattern(
+ self,
+ 'cat /sys/class/hwmon/hwmon*/temp1_input', '0')
+ self.vm.cmd('qom-set', path='/machine/peripheral/tmp-test',
+ property='temperature', value=18000)
+ exec_command_and_wait_for_pattern(
+ self,
+ 'cat /sys/class/hwmon/hwmon*/temp1_input', '18000')
+
+ self.do_test_aarch64_ast2700fc_ssp_start()
+
+ exec_command_and_wait_for_pattern(self, '\012', 'ssp:~$')
+ exec_command_and_wait_for_pattern(self, 'version',
+ 'Zephyr version 3.7.1')
+ exec_command_and_wait_for_pattern(self, 'md 72c02000 1',
+ '[72c02000] 06000103')
+ self.do_test_aarch64_ast2700fc_tsp_start()
+ exec_command_and_wait_for_pattern(self, '\012', 'tsp:~$')
+ exec_command_and_wait_for_pattern(self, 'version',
+ 'Zephyr version 3.7.1')
+ exec_command_and_wait_for_pattern(self, 'md 72c02000 1',
+ '[72c02000] 06000103')
+
+ def test_aarch64_ast2700fc_a0_sdk_v09_05(self):
+ self.set_machine('ast2700fc-a0')
+ self.archive_extract(self.ASSET_SDK_V905_AST2700_A0)
+ self.archive_extract(self.ASSET_SDK_SSP_TSP_AST2700_A0)
+ self.start_ast2700fc_test('ast2700-a0-default')
+
+
+if __name__ == '__main__':
+ QemuSystemTest.main()
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 12/13] tests/function/aspeed: Add functional test for AST2700FC A1
2025-03-13 5:40 [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine Steven Lee via
` (10 preceding siblings ...)
2025-03-13 5:40 ` [PATCH 11/13] tests/function/aspeed: Add functional test for AST2700FC Steven Lee via
@ 2025-03-13 5:40 ` Steven Lee via
2025-03-13 5:40 ` [PATCH 13/13] docs: Add support for ast2700fc machine Steven Lee via
2025-03-25 17:33 ` [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine Cédric Le Goater
13 siblings, 0 replies; 26+ messages in thread
From: Steven Lee via @ 2025-03-13 5:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
Add functional test for AST2700a1-fc machine.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: I87584164b2632c58d2e051fd92d9e280347bcf19
---
tests/functional/test_aarch64_ast2700fc.py | 38 +++++++++++++++++-----
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/tests/functional/test_aarch64_ast2700fc.py b/tests/functional/test_aarch64_ast2700fc.py
index 243b74d77e..b54346a57f 100755
--- a/tests/functional/test_aarch64_ast2700fc.py
+++ b/tests/functional/test_aarch64_ast2700fc.py
@@ -14,6 +14,9 @@
class AST2700fcMachineSDK(QemuSystemTest):
+ ASSET_SDK_V905_AST2700 = Asset(
+ 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.05/ast2700-default-obmc.tar.gz',
+ 'c1f4496aec06743c812a6e9a1a18d032f34d62f3ddb6956e924fef62aa2046a5')
ASSET_SDK_V905_AST2700_A0 = Asset(
'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.05/ast2700-a0-default-obmc.tar.gz',
'cfbbd1cce72f2a3b73b9080c41eecdadebb7077fba4f7806d72ac99f3e84b74a')
@@ -81,10 +84,16 @@ def start_ast2700fc_test(self, name):
self.vm.add_args('-device',
f'loader,addr=0x430000000,cpu-num={i}')
- load_elf_list = {
- 'ssp': self.scratch_file('ast2700-a0-ssp-tsp', 'ast2700-ssp.elf'),
- 'tsp': self.scratch_file('ast2700-a0-ssp-tsp', 'ast2700-tsp.elf')
- }
+ if name == 'ast2700-a0-default':
+ load_elf_list = {
+ 'ssp': self.scratch_file('ast2700-a0-ssp-tsp', 'ast2700-ssp.elf'),
+ 'tsp': self.scratch_file('ast2700-a0-ssp-tsp', 'ast2700-tsp.elf')
+ }
+ else:
+ load_elf_list = {
+ 'ssp': self.scratch_file(name, 'ast2700-ssp.elf'),
+ 'tsp': self.scratch_file(name, 'ast2700-tsp.elf')
+ }
for cpu_num, key in enumerate(load_elf_list, start=4):
file = load_elf_list[key]
@@ -119,14 +128,27 @@ def start_ast2700fc_test(self, name):
exec_command_and_wait_for_pattern(self, '\012', 'ssp:~$')
exec_command_and_wait_for_pattern(self, 'version',
'Zephyr version 3.7.1')
- exec_command_and_wait_for_pattern(self, 'md 72c02000 1',
- '[72c02000] 06000103')
+ if name == 'ast2700-a0-default':
+ exec_command_and_wait_for_pattern(self, 'md 72c02000 1',
+ '[72c02000] 06000103')
+ else:
+ exec_command_and_wait_for_pattern(self, 'md 72c02000 1',
+ '[72c02000] 06010103')
self.do_test_aarch64_ast2700fc_tsp_start()
exec_command_and_wait_for_pattern(self, '\012', 'tsp:~$')
exec_command_and_wait_for_pattern(self, 'version',
'Zephyr version 3.7.1')
- exec_command_and_wait_for_pattern(self, 'md 72c02000 1',
- '[72c02000] 06000103')
+ if name == 'ast2700-a0-default':
+ exec_command_and_wait_for_pattern(self, 'md 72c02000 1',
+ '[72c02000] 06000103')
+ else:
+ exec_command_and_wait_for_pattern(self, 'md 72c02000 1',
+ '[72c02000] 06010103')
+
+ def test_aarch64_ast2700fc_sdk_v09_05(self):
+ self.set_machine('ast2700fc-a1')
+ self.archive_extract(self.ASSET_SDK_V905_AST2700)
+ self.start_ast2700fc_test('ast2700-default')
def test_aarch64_ast2700fc_a0_sdk_v09_05(self):
self.set_machine('ast2700fc-a0')
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* [PATCH 13/13] docs: Add support for ast2700fc machine
2025-03-13 5:40 [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine Steven Lee via
` (11 preceding siblings ...)
2025-03-13 5:40 ` [PATCH 12/13] tests/function/aspeed: Add functional test for AST2700FC A1 Steven Lee via
@ 2025-03-13 5:40 ` Steven Lee via
2025-03-25 17:33 ` [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine Cédric Le Goater
13 siblings, 0 replies; 26+ messages in thread
From: Steven Lee via @ 2025-03-13 5:40 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
- Updated Aspeed family boards list to include `ast2700fc`.
- Added boot instructions for the `ast2700fc` machine.
- Detailed the configuration and loading of firmware for the
Cortex-A35 and Cortex-M4 processors.
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: I48d90589d29ae6bb70a172e1798f18c0c38e6e22
---
docs/system/arm/aspeed.rst | 61 ++++++++++++++++++++++++++++++++++++--
1 file changed, 59 insertions(+), 2 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 97fd6a0e7f..160472411f 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -1,5 +1,5 @@
-Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
-==================================================================================================================================================================================================================================================================================================================================================================================================================
+Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, ``ast2700fc``, ``bletchley-bmc``, ``fuji-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspoon-bmc``, ``yosemitev2-bmc``)
+=================================================================================================================================================================================================================================================================================================================================================================================================================================
The QEMU Aspeed machines model BMCs of various OpenPOWER systems and
Aspeed evaluation boards. They are based on different releases of the
@@ -42,6 +42,7 @@ AST2600 SoC based machines :
AST2700 SoC based machines :
- ``ast2700-evb`` Aspeed AST2700 Evaluation board (Cortex-A35)
+- ``ast2700fc`` Aspeed AST2700 Evaluation board (Cortex-A35 + Cortex-M4)
Supported devices
-----------------
@@ -270,6 +271,62 @@ Boot the AST2700 machine from the flash image, use an MTD drive :
-drive file=${IMGDIR}/image-bmc,format=raw,if=mtd \
-nographic
+Booting the ast2700fc machine
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+AST2700 features four Cortex-A35 primary processors and two Cortex-M4 coprocessors.
+**ast2700-evb** machine focuses on emulating the four Cortex-A35 primary processors,
+**ast2700fc** machine extends **ast2700-evb** by adding support for the two Cortex-M4 coprocessors.
+
+To boot the AST2700 full-core machine, follow these steps:
+
+ 1. Configure an MTD drive for the four Cortex-A35 primary processors.
+ 2. Load:
+
+ - SSP (Secondary Service Processor) firmware on CPU 5 (``cpu-num=4``).
+ - TSP (Tertiary Service Processor) firmware on CPU 6 (``cpu-num=5``).
+
+.. code-block:: bash
+
+ IMGDIR=ast2700-default
+ UBOOT_SIZE=$(stat --format=%s -L ${IMGDIR}/u-boot-nodtb.bin)
+
+ $ qemu-system-aarch64 -M ast2700fc \
+ -device loader,force-raw=on,addr=0x400000000,file=${IMGDIR}/u-boot-nodtb.bin \
+ -device loader,force-raw=on,addr=$((0x400000000 + ${UBOOT_SIZE})),file=${IMGDIR}/u-boot.dtb \
+ -device loader,force-raw=on,addr=0x430000000,file=${IMGDIR}/bl31.bin \
+ -device loader,force-raw=on,addr=0x430080000,file=${IMGDIR}/tee-raw.bin \
+ -device loader,cpu-num=0,addr=0x430000000 \
+ -device loader,cpu-num=1,addr=0x430000000 \
+ -device loader,cpu-num=2,addr=0x430000000 \
+ -device loader,cpu-num=3,addr=0x430000000 \
+ -drive file=${IMGDIR}/image-bmc,if=mtd,format=raw \
+ -device loader,file=${IMGDIR}/ast2700-ssp.elf,cpu-num=4 \
+ -device loader,file=${IMGDIR}/ast2700-tsp.elf,cpu-num=5 \
+ -serial pty -serial pty -serial pty \
+ -snapshot \
+ -S -nographic
+
+After starting QEMU, the serial devices will be redirected:
+
+.. code-block:: bash
+
+ char device redirected to /dev/pts/55 (label serial0)
+ char device redirected to /dev/pts/56 (label serial1)
+ char device redirected to /dev/pts/57 (label serial2)
+
+
+
+`serial0` is the console for the four Cortex-A35 primary processors, `serial1` and `serial2` are the consoles for the two Cortex-M4 coprocessors.
+To connect to the console, use `tio` or other terminal emulator:
+
+.. code-block:: bash
+
+ $ tio /dev/pts/55
+ $ tio /dev/pts/56
+ $ tio /dev/pts/57
+
+
Aspeed minibmc family boards (``ast1030-evb``)
==================================================================
--
2.34.1
^ permalink raw reply related [flat|nested] 26+ messages in thread* Re: [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine
2025-03-13 5:40 [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine Steven Lee via
` (12 preceding siblings ...)
2025-03-13 5:40 ` [PATCH 13/13] docs: Add support for ast2700fc machine Steven Lee via
@ 2025-03-25 17:33 ` Cédric Le Goater
2025-04-08 6:35 ` Steven Lee
13 siblings, 1 reply; 26+ messages in thread
From: Cédric Le Goater @ 2025-03-25 17:33 UTC (permalink / raw)
To: Steven Lee, Peter Maydell, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: troy_lee, yunlin.tang
Hello Steven,
On 3/13/25 06:40, Steven Lee wrote:
> This patch series introduces full core support for the AST27x0 SoC, along with necessary updates to the ASPEED AST27x0 SOC.
> The AST27x0 SoC is a new family of ASPEED SoCs featuring 4 Cortex-A35 cores and 2 Cortex-M4 cores.
>
> v1:
> - Map unimplemented devices in SoC memory
> - Intruduce AST2700 CM4 SoC
> - Introduce AST27x0FC Machine
>
> v2:
> - Remove unused functions
> - Correct hex notation for device addresses in AST27x0 SoC
> - Add AST2700 SSP INTC and AST2700 TSP INTC
> - Split AST27x0 CM4 SoC to AST27x0 SSP SoC and AST27x0 TSP SoC
> - Add AST27x0 A0 SSP SoC and AST27x0 A1 SSP SoC
> - Add AST27x0 A0 TSP SoC and AST27x0 A1 TSP SoC
> - Add functional tests for AST2700FC A0 and AST2700FC A1
> - Add Documentation for AST2700FC
Please try to label all patches as v2. See 'git format-patch -v ...'
> Steven Lee (13):
> aspeed: ast27x0: Map unimplemented devices in SoC memory
> aspeed: ast27x0: Correct hex notation for device addresses
> hw/intc/aspeed: Add support for AST2700 SSP INTC
> hw/intc/aspeed: Add support for AST2700 TSP INTC
> hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC
> hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC
> hw/arm/aspeed_ast27x0-tsp: Introduce AST27x0 A0 TSP SoC
> hw/arm/aspeed_ast27x0-tsp: Introduce AST27x0 A1 TSP SoC
> hw/arm: Introduce ASPEED AST2700 a0 full core machine
> hw/arm: Introduce ASPEED AST2700 a1 full core machine
> tests/function/aspeed: Add functional test for AST2700FC
> tests/function/aspeed: Add functional test for AST2700FC A1
> docs: Add support for ast2700fc machine
Do we need to add support for the A0 and A1 ? Would A1 be enough ?
Thanks,
C.
> docs/system/arm/aspeed.rst | 61 ++-
> include/hw/arm/aspeed_soc.h | 32 ++
> include/hw/intc/aspeed_intc.h | 5 +
> hw/arm/aspeed_ast27x0-fc.c | 340 +++++++++++++++++
> hw/arm/aspeed_ast27x0-ssp.c | 400 +++++++++++++++++++
> hw/arm/aspeed_ast27x0-tsp.c | 400 +++++++++++++++++++
> hw/arm/aspeed_ast27x0.c | 79 +++-
> hw/intc/aspeed_intc.c | 424 +++++++++++++++++++++
> hw/arm/meson.build | 6 +-
> tests/functional/test_aarch64_ast2700fc.py | 161 ++++++++
> 10 files changed, 1884 insertions(+), 24 deletions(-)
> create mode 100644 hw/arm/aspeed_ast27x0-fc.c
> create mode 100644 hw/arm/aspeed_ast27x0-ssp.c
> create mode 100644 hw/arm/aspeed_ast27x0-tsp.c
> create mode 100755 tests/functional/test_aarch64_ast2700fc.py
>
^ permalink raw reply [flat|nested] 26+ messages in thread* RE: [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine
2025-03-25 17:33 ` [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine Cédric Le Goater
@ 2025-04-08 6:35 ` Steven Lee
2025-04-08 6:46 ` Cédric Le Goater
2025-04-23 9:51 ` Cédric Le Goater
0 siblings, 2 replies; 26+ messages in thread
From: Steven Lee @ 2025-04-08 6:35 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Troy Lee, Jamin Lin,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
> -----Original Message-----
> From: Cédric Le Goater <clg@kaod.org>
> Sent: Wednesday, March 26, 2025 1:34 AM
> To: Steven Lee <steven_lee@aspeedtech.com>; Peter Maydell
> <peter.maydell@linaro.org>; Troy Lee <leetroy@gmail.com>; Jamin Lin
> <jamin_lin@aspeedtech.com>; Andrew Jeffery
> <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
> <qemu-devel@nongnu.org>
> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
> <yunlin.tang@aspeedtech.com>
> Subject: Re: [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine
>
> Hello Steven,
>
> On 3/13/25 06:40, Steven Lee wrote:
> > This patch series introduces full core support for the AST27x0 SoC, along with
> necessary updates to the ASPEED AST27x0 SOC.
> > The AST27x0 SoC is a new family of ASPEED SoCs featuring 4 Cortex-A35
> cores and 2 Cortex-M4 cores.
> >
> > v1:
> > - Map unimplemented devices in SoC memory
> > - Intruduce AST2700 CM4 SoC
> > - Introduce AST27x0FC Machine
> >
> > v2:
> > - Remove unused functions
> > - Correct hex notation for device addresses in AST27x0 SoC
> > - Add AST2700 SSP INTC and AST2700 TSP INTC
> > - Split AST27x0 CM4 SoC to AST27x0 SSP SoC and AST27x0 TSP SoC
> > - Add AST27x0 A0 SSP SoC and AST27x0 A1 SSP SoC
> > - Add AST27x0 A0 TSP SoC and AST27x0 A1 TSP SoC
> > - Add functional tests for AST2700FC A0 and AST2700FC A1
> > - Add Documentation for AST2700FC
>
> Please try to label all patches as v2. See 'git format-patch -v ...'
>
Hi Cédric,
Thanks for the reminder. I will label the patches as v3 in the next submission.
Regards,
Steven
> > Steven Lee (13):
> > aspeed: ast27x0: Map unimplemented devices in SoC memory
> > aspeed: ast27x0: Correct hex notation for device addresses
> > hw/intc/aspeed: Add support for AST2700 SSP INTC
> > hw/intc/aspeed: Add support for AST2700 TSP INTC
> > hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC
> > hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC
> > hw/arm/aspeed_ast27x0-tsp: Introduce AST27x0 A0 TSP SoC
> > hw/arm/aspeed_ast27x0-tsp: Introduce AST27x0 A1 TSP SoC
> > hw/arm: Introduce ASPEED AST2700 a0 full core machine
> > hw/arm: Introduce ASPEED AST2700 a1 full core machine
> > tests/function/aspeed: Add functional test for AST2700FC
> > tests/function/aspeed: Add functional test for AST2700FC A1
> > docs: Add support for ast2700fc machine
>
> Do we need to add support for the A0 and A1 ? Would A1 be enough ?
>
I will remove A0 in v3 the patch series.
>
>
>
>
> > docs/system/arm/aspeed.rst | 61 ++-
> > include/hw/arm/aspeed_soc.h | 32 ++
> > include/hw/intc/aspeed_intc.h | 5 +
> > hw/arm/aspeed_ast27x0-fc.c | 340
> +++++++++++++++++
> > hw/arm/aspeed_ast27x0-ssp.c | 400
> +++++++++++++++++++
> > hw/arm/aspeed_ast27x0-tsp.c | 400
> +++++++++++++++++++
> > hw/arm/aspeed_ast27x0.c | 79 +++-
> > hw/intc/aspeed_intc.c | 424
> +++++++++++++++++++++
> > hw/arm/meson.build | 6 +-
> > tests/functional/test_aarch64_ast2700fc.py | 161 ++++++++
> > 10 files changed, 1884 insertions(+), 24 deletions(-)
> > create mode 100644 hw/arm/aspeed_ast27x0-fc.c
> > create mode 100644 hw/arm/aspeed_ast27x0-ssp.c
> > create mode 100644 hw/arm/aspeed_ast27x0-tsp.c
> > create mode 100755 tests/functional/test_aarch64_ast2700fc.py
> >
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine
2025-04-08 6:35 ` Steven Lee
@ 2025-04-08 6:46 ` Cédric Le Goater
2025-04-23 9:51 ` Cédric Le Goater
1 sibling, 0 replies; 26+ messages in thread
From: Cédric Le Goater @ 2025-04-08 6:46 UTC (permalink / raw)
To: Steven Lee, Peter Maydell, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
On 4/8/25 08:35, Steven Lee wrote:
>> -----Original Message-----
>> From: Cédric Le Goater <clg@kaod.org>
>> Sent: Wednesday, March 26, 2025 1:34 AM
>> To: Steven Lee <steven_lee@aspeedtech.com>; Peter Maydell
>> <peter.maydell@linaro.org>; Troy Lee <leetroy@gmail.com>; Jamin Lin
>> <jamin_lin@aspeedtech.com>; Andrew Jeffery
>> <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
>> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
>> <qemu-devel@nongnu.org>
>> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
>> <yunlin.tang@aspeedtech.com>
>> Subject: Re: [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine
>>
>> Hello Steven,
>>
>> On 3/13/25 06:40, Steven Lee wrote:
>>> This patch series introduces full core support for the AST27x0 SoC, along with
>> necessary updates to the ASPEED AST27x0 SOC.
>>> The AST27x0 SoC is a new family of ASPEED SoCs featuring 4 Cortex-A35
>> cores and 2 Cortex-M4 cores.
>>>
>>> v1:
>>> - Map unimplemented devices in SoC memory
>>> - Intruduce AST2700 CM4 SoC
>>> - Introduce AST27x0FC Machine
>>>
>>> v2:
>>> - Remove unused functions
>>> - Correct hex notation for device addresses in AST27x0 SoC
>>> - Add AST2700 SSP INTC and AST2700 TSP INTC
>>> - Split AST27x0 CM4 SoC to AST27x0 SSP SoC and AST27x0 TSP SoC
>>> - Add AST27x0 A0 SSP SoC and AST27x0 A1 SSP SoC
>>> - Add AST27x0 A0 TSP SoC and AST27x0 A1 TSP SoC
>>> - Add functional tests for AST2700FC A0 and AST2700FC A1
>>> - Add Documentation for AST2700FC
>>
>> Please try to label all patches as v2. See 'git format-patch -v ...'
>>
>
> Hi Cédric,
>
> Thanks for the reminder. I will label the patches as v3 in the next submission.
>
> Regards,
> Steven
>
>>> Steven Lee (13):
>>> aspeed: ast27x0: Map unimplemented devices in SoC memory
>>> aspeed: ast27x0: Correct hex notation for device addresses
>>> hw/intc/aspeed: Add support for AST2700 SSP INTC
>>> hw/intc/aspeed: Add support for AST2700 TSP INTC
>>> hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC
>>> hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC
>>> hw/arm/aspeed_ast27x0-tsp: Introduce AST27x0 A0 TSP SoC
>>> hw/arm/aspeed_ast27x0-tsp: Introduce AST27x0 A1 TSP SoC
>>> hw/arm: Introduce ASPEED AST2700 a0 full core machine
>>> hw/arm: Introduce ASPEED AST2700 a1 full core machine
>>> tests/function/aspeed: Add functional test for AST2700FC
>>> tests/function/aspeed: Add functional test for AST2700FC A1
>>> docs: Add support for ast2700fc machine
>>
>> Do we need to add support for the A0 and A1 ? Would A1 be enough ?
>>
>
> I will remove A0 in v3 the patch series.
Thanks, it all looked good to me. I should be able to queue the series
quickly for QEMU 10.1 before Jamin's HACE changes.
C.
>
>>
>>
>>
>>
>>> docs/system/arm/aspeed.rst | 61 ++-
>>> include/hw/arm/aspeed_soc.h | 32 ++
>>> include/hw/intc/aspeed_intc.h | 5 +
>>> hw/arm/aspeed_ast27x0-fc.c | 340
>> +++++++++++++++++
>>> hw/arm/aspeed_ast27x0-ssp.c | 400
>> +++++++++++++++++++
>>> hw/arm/aspeed_ast27x0-tsp.c | 400
>> +++++++++++++++++++
>>> hw/arm/aspeed_ast27x0.c | 79 +++-
>>> hw/intc/aspeed_intc.c | 424
>> +++++++++++++++++++++
>>> hw/arm/meson.build | 6 +-
>>> tests/functional/test_aarch64_ast2700fc.py | 161 ++++++++
>>> 10 files changed, 1884 insertions(+), 24 deletions(-)
>>> create mode 100644 hw/arm/aspeed_ast27x0-fc.c
>>> create mode 100644 hw/arm/aspeed_ast27x0-ssp.c
>>> create mode 100644 hw/arm/aspeed_ast27x0-tsp.c
>>> create mode 100755 tests/functional/test_aarch64_ast2700fc.py
>>>
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine
2025-04-08 6:35 ` Steven Lee
2025-04-08 6:46 ` Cédric Le Goater
@ 2025-04-23 9:51 ` Cédric Le Goater
1 sibling, 0 replies; 26+ messages in thread
From: Cédric Le Goater @ 2025-04-23 9:51 UTC (permalink / raw)
To: Steven Lee, Peter Maydell, Troy Lee, Jamin Lin, Andrew Jeffery,
Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: Troy Lee, Yunlin Tang
Hello Steven,
On 4/8/25 08:35, Steven Lee wrote:
>> -----Original Message-----
>> From: Cédric Le Goater <clg@kaod.org>
>> Sent: Wednesday, March 26, 2025 1:34 AM
>> To: Steven Lee <steven_lee@aspeedtech.com>; Peter Maydell
>> <peter.maydell@linaro.org>; Troy Lee <leetroy@gmail.com>; Jamin Lin
>> <jamin_lin@aspeedtech.com>; Andrew Jeffery
>> <andrew@codeconstruct.com.au>; Joel Stanley <joel@jms.id.au>; open
>> list:ASPEED BMCs <qemu-arm@nongnu.org>; open list:All patches CC here
>> <qemu-devel@nongnu.org>
>> Cc: Troy Lee <troy_lee@aspeedtech.com>; Yunlin Tang
>> <yunlin.tang@aspeedtech.com>
>> Subject: Re: [PATCH v2 00/13] Introduce AST27x0 multi-SoC machine
>>
>> Hello Steven,
>>
>> On 3/13/25 06:40, Steven Lee wrote:
>>> This patch series introduces full core support for the AST27x0 SoC, along with
>> necessary updates to the ASPEED AST27x0 SOC.
>>> The AST27x0 SoC is a new family of ASPEED SoCs featuring 4 Cortex-A35
>> cores and 2 Cortex-M4 cores.
>>>
>>> v1:
>>> - Map unimplemented devices in SoC memory
>>> - Intruduce AST2700 CM4 SoC
>>> - Introduce AST27x0FC Machine
>>>
>>> v2:
>>> - Remove unused functions
>>> - Correct hex notation for device addresses in AST27x0 SoC
>>> - Add AST2700 SSP INTC and AST2700 TSP INTC
>>> - Split AST27x0 CM4 SoC to AST27x0 SSP SoC and AST27x0 TSP SoC
>>> - Add AST27x0 A0 SSP SoC and AST27x0 A1 SSP SoC
>>> - Add AST27x0 A0 TSP SoC and AST27x0 A1 TSP SoC
>>> - Add functional tests for AST2700FC A0 and AST2700FC A1
>>> - Add Documentation for AST2700FC
>>
>> Please try to label all patches as v2. See 'git format-patch -v ...'
>>
>
> Hi Cédric,
>
> Thanks for the reminder. I will label the patches as v3 in the next submission.
>
> Regards,
> Steven
>
>>> Steven Lee (13):
>>> aspeed: ast27x0: Map unimplemented devices in SoC memory
>>> aspeed: ast27x0: Correct hex notation for device addresses
>>> hw/intc/aspeed: Add support for AST2700 SSP INTC
>>> hw/intc/aspeed: Add support for AST2700 TSP INTC
>>> hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A0 SSP SoC
>>> hw/arm/aspeed_ast27x0-ssp: Introduce AST27x0 A1 SSP SoC
>>> hw/arm/aspeed_ast27x0-tsp: Introduce AST27x0 A0 TSP SoC
>>> hw/arm/aspeed_ast27x0-tsp: Introduce AST27x0 A1 TSP SoC
>>> hw/arm: Introduce ASPEED AST2700 a0 full core machine
>>> hw/arm: Introduce ASPEED AST2700 a1 full core machine
>>> tests/function/aspeed: Add functional test for AST2700FC
>>> tests/function/aspeed: Add functional test for AST2700FC A1
>>> docs: Add support for ast2700fc machine
>>
>> Do we need to add support for the A0 and A1 ? Would A1 be enough ?
>>
>
> I will remove A0 in v3 the patch series.
Do you plan to resend soon ? I think we could merge this series
quickly.
It would be nice to handle the conflicts on the documentation
with the series from Jamin adding vbootrom support.
Thanks,
C.
^ permalink raw reply [flat|nested] 26+ messages in thread