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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9b55cdsm14089517f8f.52.2025.03.25.08.20.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Mar 2025 08:20:39 -0700 (PDT) Message-ID: <8426486f-d795-475a-b98e-35c31ae3f9a9@linaro.org> Date: Tue, 25 Mar 2025 16:20:39 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 17/18] target/mips: Make MIPS_CPU common to new MIPS32_CPU / MIPS64_CPU types From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= To: Richard Henderson , qemu-devel@nongnu.org Cc: Manos Pitsidianakis , Markus Armbruster , Pierrick Bouvier References: <20231010092901.99189-1-philmd@linaro.org> <20231010092901.99189-18-philmd@linaro.org> <8d30ccda-5b81-42fd-b36c-79bbaceffa2a@linaro.org> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 15/3/24 13:22, Philippe Mathieu-Daudé wrote: > On 13/10/23 06:34, Richard Henderson wrote: >> On 10/10/23 02:28, Philippe Mathieu-Daudé wrote: >>> "target/foo/cpu-qom.h" can not use any target specific definitions. >>> >>> Currently "target/mips/cpu-qom.h" defines TYPE_MIPS_CPU depending >>> on the mips(32)/mips64 build type. This doesn't scale in a >>> heterogeneous context where we need to access both types concurrently. >>> >>> In order to do that, introduce the new MIPS32_CPU / MIPS64_CPU types, >>> both inheriting a common TYPE_MIPS_CPU base type. >>> >>> Keep the current CPU types registered in mips_register_cpudef_type() >>> as 32 or 64-bit, but instead of depending on the binary built being >>> targeting 32/64-bit, check whether the CPU is 64-bit by looking at >>> the CPU_MIPS64 bit. >>> >>> Signed-off-by: Philippe Mathieu-Daudé >>> --- >>>   target/mips/cpu-qom.h | 13 ++++++------- >>>   target/mips/cpu.h     |  3 +++ >>>   target/mips/cpu.c     | 11 ++++++++++- >>>   3 files changed, 19 insertions(+), 8 deletions(-) >>> >>> diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h >>> index 9c98ca1956..1a71509b5e 100644 >>> --- a/target/mips/cpu-qom.h >>> +++ b/target/mips/cpu-qom.h >>> @@ -1,5 +1,5 @@ >>>   /* >>> - * QEMU MIPS CPU >>> + * QEMU MIPS CPU QOM header (target agnostic) >>>    * >>>    * Copyright (c) 2012 SUSE LINUX Products GmbH >>>    * >>> @@ -23,13 +23,12 @@ >>>   #include "hw/core/cpu.h" >>>   #include "qom/object.h" >>> -#ifdef TARGET_MIPS64 >>> -#define TYPE_MIPS_CPU "mips64-cpu" >>> -#else >>> -#define TYPE_MIPS_CPU "mips-cpu" >>> -#endif >>> +#define TYPE_MIPS_CPU   "mips-cpu" >>> +#define TYPE_MIPS32_CPU "mips32-cpu" >>> +#define TYPE_MIPS64_CPU "mips64-cpu" >>> -OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) >>> +OBJECT_DECLARE_CPU_TYPE(MIPS32CPU, MIPSCPUClass, MIPS32_CPU) >>> +OBJECT_DECLARE_CPU_TYPE(MIPS64CPU, MIPSCPUClass, MIPS64_CPU) >>>   #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU >>>   #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX >>> diff --git a/target/mips/cpu.h b/target/mips/cpu.h >>> index 6b026e6bcf..3b6d0a7a8a 100644 >>> --- a/target/mips/cpu.h >>> +++ b/target/mips/cpu.h >>> @@ -10,6 +10,9 @@ >>>   #include "hw/clock.h" >>>   #include "mips-defs.h" >>> +/* Abstract QOM MIPS CPU, not exposed to other targets */ >>> +OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) >> >> Why is this one moved back to cpu.h? >> You exposed TYPE_X86_CPU in i386/cpu-qom.h... > > First thinking was to expose the base TYPE, so we can use QOM methods > to enumerate implementations, but not expose QOM state/class getter > for the base type (except in target/foo/). HW would use concrete > 32 or 64b type state/class getter. I might be wrong, so I'll keep > the base type exposed for now. We might restrict later. With retrospective I was indeed wrong, as it seems useful for a heterogeneous board to check "is there any vCPU based on Arch FOO" without having to worry for FOO being 32 or 64. I'll expose the base arch as QOM definition.