From: Richard Henderson <richard.henderson@linaro.org>
To: Stephen Long <steplong@quicinc.com>, qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, apazos@quicinc.com
Subject: Re: [PATCH RFC] target/arm: Implement SVE2 bitwise shift immediate
Date: Thu, 30 Apr 2020 11:19:39 -0700 [thread overview]
Message-ID: <84356e80-96fb-e0e8-9fd1-a380c375680a@linaro.org> (raw)
In-Reply-To: <20200430162828.13993-1-steplong@quicinc.com>
On 4/30/20 9:28 AM, Stephen Long wrote:
> Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU
>
> Signed-off-by: Stephen Long <steplong@quicinc.com>
> ---
>
> I'm not too sure about the casting I'm doing willy nilly in the helper
> functions, but I think they should be ok. Also, there might be some avenues
> for optimization when translating similar to asr_zpzi and lsl_zpzi.
No, the optimization would interfere with the saturation.
The casting is ok except for sqshlu. Negative values should saturate to 0, but
by passing them to the uqshl helper, the inputs get treated as large unsigned
values and saturate to UINT_MAX. You need to use do_suqrshl_bhs for that.
r~
prev parent reply other threads:[~2020-04-30 18:43 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-30 16:28 [PATCH RFC] target/arm: Implement SVE2 bitwise shift immediate Stephen Long
2020-04-30 18:19 ` Richard Henderson [this message]
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