From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Gregory Price" <gourry.memverge@gmail.com>,
"Gregory Price" <gregory.price@memverge.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Jonathan Cameron" <Jonathan.Cameron@huawei.com>,
"Thomas Huth" <thuth@redhat.com>,
"Laurent Vivier" <lvivier@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>
Subject: [PULL 10/40] tests/qtest/cxl-test: whitespace, line ending cleanup
Date: Fri, 19 May 2023 10:50:24 -0400 [thread overview]
Message-ID: <847ea4e746a1cac861ffe6b8256052131e8e3b93.1684507742.git.mst@redhat.com> (raw)
In-Reply-To: <cover.1684507742.git.mst@redhat.com>
From: Gregory Price <gourry.memverge@gmail.com>
Defines are starting to exceed line length limits, align them for
cleanliness before making modifications.
Signed-off-by: Gregory Price <gregory.price@memverge.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20230421160827.2227-2-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/cxl-test.c | 78 +++++++++++++++++++++++-------------------
1 file changed, 43 insertions(+), 35 deletions(-)
diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
index 61f25a72b6..eda2bbbbe6 100644
--- a/tests/qtest/cxl-test.c
+++ b/tests/qtest/cxl-test.c
@@ -8,50 +8,58 @@
#include "qemu/osdep.h"
#include "libqtest-single.h"
-#define QEMU_PXB_CMD "-machine q35,cxl=on " \
- "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
- "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.size=4G "
+#define QEMU_PXB_CMD \
+ "-machine q35,cxl=on " \
+ "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
+ "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.size=4G "
-#define QEMU_2PXB_CMD "-machine q35,cxl=on " \
- "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
- "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \
- "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G "
+#define QEMU_2PXB_CMD \
+ "-machine q35,cxl=on " \
+ "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
+ "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 " \
+ "-M cxl-fmw.0.targets.0=cxl.0,cxl-fmw.0.targets.1=cxl.1,cxl-fmw.0.size=4G "
-#define QEMU_RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 "
+#define QEMU_RP \
+ "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 "
/* Dual ports on first pxb */
-#define QEMU_2RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
- "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 "
+#define QEMU_2RP \
+ "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
+ "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 "
/* Dual ports on each of the pxb instances */
-#define QEMU_4RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
- "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " \
- "-device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 " \
- "-device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 "
+#define QEMU_4RP \
+ "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
+ "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " \
+ "-device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 " \
+ "-device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 "
-#define QEMU_T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
- "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
- "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 "
+#define QEMU_T3D \
+ "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
+ "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
+ "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 "
-#define QEMU_2T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
- "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
- "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \
- "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \
- "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M " \
- "-device cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 "
+#define QEMU_2T3D \
+ "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
+ "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
+ "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \
+ "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \
+ "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M " \
+ "-device cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 "
-#define QEMU_4T3D "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
- "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
- "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \
- "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \
- "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M " \
- "-device cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 " \
- "-object memory-backend-file,id=cxl-mem2,mem-path=%s,size=256M " \
- "-object memory-backend-file,id=lsa2,mem-path=%s,size=256M " \
- "-device cxl-type3,bus=rp2,memdev=cxl-mem2,lsa=lsa2,id=cxl-pmem2 " \
- "-object memory-backend-file,id=cxl-mem3,mem-path=%s,size=256M " \
- "-object memory-backend-file,id=lsa3,mem-path=%s,size=256M " \
- "-device cxl-type3,bus=rp3,memdev=cxl-mem3,lsa=lsa3,id=cxl-pmem3 "
+#define QEMU_4T3D \
+ "-object memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
+ "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M " \
+ "-device cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \
+ "-object memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \
+ "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M " \
+ "-device cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 " \
+ "-object memory-backend-file,id=cxl-mem2,mem-path=%s,size=256M " \
+ "-object memory-backend-file,id=lsa2,mem-path=%s,size=256M " \
+ "-device cxl-type3,bus=rp2,memdev=cxl-mem2,lsa=lsa2,id=cxl-pmem2 " \
+ "-object memory-backend-file,id=cxl-mem3,mem-path=%s,size=256M " \
+ "-object memory-backend-file,id=lsa3,mem-path=%s,size=256M " \
+ "-device cxl-type3,bus=rp3,memdev=cxl-mem3,lsa=lsa3,id=cxl-pmem3 "
static void cxl_basic_hb(void)
{
--
MST
next prev parent reply other threads:[~2023-05-19 14:52 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-19 14:49 [PULL 00/40] virtio,pc,pci: fixes, features, cleanups Michael S. Tsirkin
2023-05-19 14:49 ` [PULL 01/40] vhost: fix possible wrap in SVQ descriptor ring Michael S. Tsirkin
2023-05-19 14:49 ` [PULL 02/40] hw/cxl: cdat: Fix open file not closed in ct3_load_cdat() Michael S. Tsirkin
2023-05-19 14:49 ` [PULL 03/40] hw/cxl: cdat: Fix failure to free buffer in erorr paths Michael S. Tsirkin
2023-05-19 14:49 ` [PULL 04/40] docs/cxl: fix some typos Michael S. Tsirkin
2023-05-19 14:49 ` [PULL 05/40] docs/cxl: Remove incorrect CXL type 3 size parameter Michael S. Tsirkin
2023-05-19 14:50 ` [PULL 06/40] docs/cxl: Replace unsupported AARCH64 with x86_64 Michael S. Tsirkin
2023-05-19 14:50 ` [PULL 07/40] hw/cxl: drop pointless memory_region_transaction_guards Michael S. Tsirkin
2023-05-19 14:50 ` [PULL 08/40] hw/cxl: Fix endian handling for decoder commit Michael S. Tsirkin
2023-05-19 14:50 ` [PULL 09/40] hw/cxl: Fix incorrect reset of commit and associated clearing of committed Michael S. Tsirkin
2023-05-19 14:50 ` Michael S. Tsirkin [this message]
2023-05-19 14:50 ` [PULL 11/40] hw/mem: Use memory_region_size() in cxl_type3 Michael S. Tsirkin
2023-05-19 14:50 ` [PULL 12/40] hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent) Michael S. Tsirkin
2023-05-19 14:50 ` [PULL 13/40] ACPI: bios-tables-test.c step 2 (allowed-diff entries) Michael S. Tsirkin
2023-05-19 14:50 ` [PULL 14/40] ACPI: i386: bump to MADT to revision 3 Michael S. Tsirkin
2023-05-19 14:50 ` [PULL 15/40] ACPI: bios-tables-test.c step 5 (update expected table binaries) Michael S. Tsirkin
2023-05-19 14:51 ` [PULL 16/40] pci: pci_add_option_rom(): improve style Michael S. Tsirkin
2023-05-19 14:51 ` [PULL 17/40] pci: pci_add_option_rom(): refactor: use g_autofree for path variable Michael S. Tsirkin
2023-05-19 14:51 ` [PULL 18/40] vhost-user: send SET_STATUS 0 after GET_VRING_BASE Michael S. Tsirkin
2023-05-19 14:51 ` [PULL 19/40] hw/pci: Disable PCI_ERR_UNCOR_MASK register for machine type < 8.0 Michael S. Tsirkin
2023-05-19 14:51 ` [PULL 20/40] virtio-mem: Default to "unplugged-inaccessible=on" with 8.1 on x86-64 Michael S. Tsirkin
2023-05-19 14:51 ` [PULL 21/40] vhost-user: Remove acpi-specific memslot limit Michael S. Tsirkin
2023-05-19 14:51 ` [PULL 22/40] virtio-net: not enable vq reset feature unconditionally Michael S. Tsirkin
2023-05-19 14:51 ` [PULL 23/40] virtio-crypto: fix NULL pointer dereference in virtio_crypto_free_request Michael S. Tsirkin
2023-05-19 14:51 ` [PULL 24/40] vhost: expose function vhost_dev_has_iommu() Michael S. Tsirkin
2023-05-19 14:51 ` [PULL 25/40] vhost_vdpa: fix the input in trace_vhost_vdpa_listener_region_del() Michael S. Tsirkin
2023-05-19 14:51 ` [PULL 26/40] vhost-vdpa: Add check for full 64-bit in region delete Michael S. Tsirkin
2023-05-19 14:51 ` [PULL 27/40] vhost-vdpa: Add support for vIOMMU Michael S. Tsirkin
2023-05-19 14:52 ` [PULL 28/40] hw/pci-host/i440fx: Inline sysbus_add_io() Michael S. Tsirkin
2023-05-19 14:52 ` [PULL 29/40] hw/pci-host/q35: " Michael S. Tsirkin
2023-05-19 14:52 ` [PULL 30/40] hw/i386/pc_q35: Reuse machine parameter Michael S. Tsirkin
2023-05-19 14:52 ` [PULL 31/40] hw/i386/pc_{q35,piix}: Reuse MachineClass::desc as SMB product name Michael S. Tsirkin
2023-05-19 14:52 ` [PULL 32/40] hw/i386/pc_{q35,piix}: Minimize usage of get_system_memory() Michael S. Tsirkin
2023-05-19 14:52 ` [PULL 33/40] hw/i386/pc: Initialize ram_memory variable directly Michael S. Tsirkin
2023-05-19 14:52 ` [PULL 34/40] hw/pci-host/pam: Make init_pam() usage more readable Michael S. Tsirkin
2023-05-19 14:52 ` [PULL 35/40] virtio-pci: add handling of PCI ATS and Device-TLB enable/disable Michael S. Tsirkin
2023-05-19 14:52 ` [PULL 36/40] hw/pci-bridge: make building pcie-to-pci bridge configurable Michael S. Tsirkin
2023-05-19 14:52 ` [PULL 37/40] hw/cxl: rename mailbox return code type from ret_code to CXLRetCode Michael S. Tsirkin
2023-05-19 14:52 ` [PULL 38/40] hw/cxl: Introduce cxl_device_get_timestamp() utility function Michael S. Tsirkin
2023-05-19 14:53 ` [PULL 39/40] hw/i386/pc: Create RTC controllers in south bridges Michael S. Tsirkin
2023-05-19 14:53 ` [PULL 40/40] hw/i386/pc: No need for rtc_state to be an out-parameter Michael S. Tsirkin
2023-05-20 3:34 ` [PULL 00/40] virtio,pc,pci: fixes, features, cleanups Richard Henderson
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