From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Anton Kochkov <anton.kochkov@proton.me>, qemu-devel@nongnu.org
Cc: eitan_eliahu@hotmail.com,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Subject: Re: [PATCH] target/tricore: Fix OPC1_16_SRO_LD_H translation
Date: Thu, 12 Jan 2023 17:11:11 +0100 [thread overview]
Message-ID: <84956702-ce6d-8a7d-6bf7-ee6f9a49881e@linaro.org> (raw)
In-Reply-To: <20230112142258.514079-1-anton.kochkov@proton.me>
On 12/1/23 15:24, Anton Kochkov wrote:
Fixes: 5a7634a28c ("target-tricore: Add instructions of SLR, SSRO and
SRO opcode format")
> Signed-off-by: Eitan Eliahu <eitan_eliahu@hotmail.com>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/652
> ---
> target/tricore/translate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/tricore/translate.c b/target/tricore/translate.c
> index df9e46c649..b2a5e11778 100644
> --- a/target/tricore/translate.c
> +++ b/target/tricore/translate.c
> @@ -3878,7 +3878,7 @@ static void decode_sro_opc(DisasContext *ctx, int op1)
> gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
> break;
> case OPC1_16_SRO_LD_H:
> - gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
> + gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
Good catch!
> break;
> case OPC1_16_SRO_LD_W:
> gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
> --
> 2.39.0
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
next prev parent reply other threads:[~2023-01-12 16:12 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-12 14:24 [PATCH] target/tricore: Fix OPC1_16_SRO_LD_H translation Anton Kochkov
2023-01-12 16:11 ` Philippe Mathieu-Daudé [this message]
2023-01-12 21:03 ` Bastian Koppelmann
2023-02-02 15:55 ` Anton Kochkov
2023-02-08 9:16 ` Bastian Koppelmann
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