From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1GWGhq-0004U6-T8 for qemu-devel@nongnu.org; Sat, 07 Oct 2006 14:15:26 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1GWGho-0004Mt-Qb for qemu-devel@nongnu.org; Sat, 07 Oct 2006 14:15:26 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1GWGho-0004MK-L9 for qemu-devel@nongnu.org; Sat, 07 Oct 2006 14:15:24 -0400 Received: from [66.249.82.239] (helo=wx-out-0506.google.com) by monty-python.gnu.org with esmtp (Exim 4.52) id 1GWGoy-0004cA-A9 for qemu-devel@nongnu.org; Sat, 07 Oct 2006 14:22:48 -0400 Received: by wx-out-0506.google.com with SMTP id r21so1556104wxc for ; Sat, 07 Oct 2006 11:15:23 -0700 (PDT) Message-ID: <84e41160610071115t75b4ec55vbe656630d5ab9373@mail.gmail.com> Date: Sun, 8 Oct 2006 02:15:23 +0800 From: "Donald Liew" MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline Subject: [Qemu-devel] why do qem/arm not clear CPU_INTERRUPT_HARD bit of env->interrupt_request automatically? Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org i'm reading qemu-system-arm code and trying to add some more evaluation boards support for it. in the 0.8.2 source code i found something i can't understand, when handling interrupts all other targets clears this bit after calling do_interrupt, however the arm target doesn't do this, why? won't this cause problems like redundant interrupts? any special consideration about this? donald