Re: [PATCH 6/9] target/arm: Store FPSR and FPCR in separate CPU state fields

[Richard Henderson <richard.henderson@linaro.org>]

On 6/28/24 07:23, Peter Maydell wrote:
> Now that we have refactored the set/get functions so that the FPSCR
> format is no longer the authoritative one, we can keep FPSR and FPCR
> in separate CPU state fields.
> 
> As well as the get and set functions, we also have a scattering of
> places in the code which directly access vfp.xregs[ARM_VFP_FPSCR] to
> extract single fields which are stored there.  These all change to
> directly access either vfp.fpsr or vfp.fpcr, depending on the
> location of the field.  (Most commonly, this is the NZCV flags.)
> 
> We make the field in the CPU state struct 64 bits, because
> architecturally FPSR and FPCR are 64 bits.  However we leave the
> types of the arguments and return values of the get/set functions as
> 32 bits, since we don't need to make that change with the current
> architecture and various callsites would be unable to handle
> set bits in the high half (for instance the gdbstub protocol
> assumes they're only 32 bit registers).
> 
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
>   target/arm/cpu.h                  |  7 +++++++
>   target/arm/tcg/translate.h        |  3 +--
>   target/arm/tcg/mve_helper.c       | 12 ++++++------
>   target/arm/tcg/translate-m-nocp.c |  6 +++---
>   target/arm/tcg/translate-vfp.c    |  2 +-
>   target/arm/vfp_helper.c           | 25 ++++++++++---------------
>   6 files changed, 28 insertions(+), 27 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~