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[174.21.76.141]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70803ecf878sm1770250b3a.135.2024.06.28.09.06.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Jun 2024 09:06:34 -0700 (PDT) Message-ID: <851098d0-4183-468c-b5a5-458baa3892d6@linaro.org> Date: Fri, 28 Jun 2024 09:06:32 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6/9] target/arm: Store FPSR and FPCR in separate CPU state fields To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20240628142347.1283015-1-peter.maydell@linaro.org> <20240628142347.1283015-7-peter.maydell@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240628142347.1283015-7-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/28/24 07:23, Peter Maydell wrote: > Now that we have refactored the set/get functions so that the FPSCR > format is no longer the authoritative one, we can keep FPSR and FPCR > in separate CPU state fields. > > As well as the get and set functions, we also have a scattering of > places in the code which directly access vfp.xregs[ARM_VFP_FPSCR] to > extract single fields which are stored there. These all change to > directly access either vfp.fpsr or vfp.fpcr, depending on the > location of the field. (Most commonly, this is the NZCV flags.) > > We make the field in the CPU state struct 64 bits, because > architecturally FPSR and FPCR are 64 bits. However we leave the > types of the arguments and return values of the get/set functions as > 32 bits, since we don't need to make that change with the current > architecture and various callsites would be unable to handle > set bits in the high half (for instance the gdbstub protocol > assumes they're only 32 bit registers). > > Signed-off-by: Peter Maydell > --- > target/arm/cpu.h | 7 +++++++ > target/arm/tcg/translate.h | 3 +-- > target/arm/tcg/mve_helper.c | 12 ++++++------ > target/arm/tcg/translate-m-nocp.c | 6 +++--- > target/arm/tcg/translate-vfp.c | 2 +- > target/arm/vfp_helper.c | 25 ++++++++++--------------- > 6 files changed, 28 insertions(+), 27 deletions(-) Reviewed-by: Richard Henderson r~