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[176.172.51.223]) by smtp.gmail.com with ESMTPSA id d19-20020a1709067f1300b0098748422178sm8402417ejr.56.2023.09.05.21.51.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 05 Sep 2023 21:51:00 -0700 (PDT) Message-ID: <8539de89-6a8b-ebac-a82c-2d09ae58202c@linaro.org> Date: Wed, 6 Sep 2023 06:50:59 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.15.0 Subject: Re: [RFC Patch 1/5] hw/display: Allwinner A10 HDMI controller emulation Content-Language: en-US To: Strahinja Jankovic , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Beniamino Galvani , Peter Maydell , Strahinja Jankovic References: <20230905201425.118918-1-strahinja.p.jankovic@gmail.com> <20230905201425.118918-2-strahinja.p.jankovic@gmail.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230905201425.118918-2-strahinja.p.jankovic@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=philmd@linaro.org; helo=mail-ej1-x62a.google.com X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.473, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Strahinja, On 5/9/23 22:14, Strahinja Jankovic wrote: > This patch adds basic Allwinner A10 HDMI controller support. > Emulated HDMI component will always show that a display is connected and > provide default EDID info. > > Signed-off-by: Strahinja Jankovic > --- > hw/arm/allwinner-a10.c | 7 + > hw/display/allwinner-a10-hdmi.c | 214 ++++++++++++++++++++++++ > hw/display/meson.build | 2 + > hw/display/trace-events | 4 + > include/hw/arm/allwinner-a10.h | 2 + > include/hw/display/allwinner-a10-hdmi.h | 69 ++++++++ > 6 files changed, 298 insertions(+) > create mode 100644 hw/display/allwinner-a10-hdmi.c > create mode 100644 include/hw/display/allwinner-a10-hdmi.h > diff --git a/hw/display/allwinner-a10-hdmi.c b/hw/display/allwinner-a10-hdmi.c > new file mode 100644 > index 0000000000..0f046e3cc7 > --- /dev/null > +++ b/hw/display/allwinner-a10-hdmi.c > +#define REG_INDEX(offset) (offset / sizeof(uint32_t)) > + > +static uint64_t allwinner_a10_hdmi_read(void *opaque, hwaddr offset, > + unsigned size) > +{ > + AwA10HdmiState *s = AW_A10_HDMI(opaque); > + const uint32_t idx = REG_INDEX(offset); > + uint32_t val = s->regs[idx]; > + > + switch (offset) { > + case REG_HPD: > + val = FIELD_HPD_HOTPLUG_DET_HIGH; > + break; > +} > + > +static void allwinner_a10_hdmi_write(void *opaque, hwaddr offset, > + uint64_t val, unsigned size) > +{ > + AwA10HdmiState *s = AW_A10_HDMI(opaque); > + const uint32_t idx = REG_INDEX(offset); > + > + switch (offset) { > + case REG_DDC_CTRL: > + if (val & FIELD_DDC_CTRL_SW_RST) { > + val &= ~FIELD_DDC_CTRL_SW_RST; > + } > + s->regs[idx] = (uint32_t) val; > +} > + > +static const MemoryRegionOps allwinner_a10_hdmi_ops = { > + .read = allwinner_a10_hdmi_read, > + .write = allwinner_a10_hdmi_write, > + .endianness = DEVICE_NATIVE_ENDIAN, > + .valid = { > + .min_access_size = 1, > + .max_access_size = 4, > + }, > + .impl.min_access_size = 1, Per REG_INDEX() you have .impl.min/max = 4. Otherwise your patch LGTM :) > +};