From: Richard Henderson <richard.henderson@linaro.org>
To: Craig Janeczek <jancraig@amazon.com>, qemu-devel@nongnu.org
Cc: aurelien@aurel32.net, amarkovic@wavecomp.com
Subject: Re: [Qemu-devel] [PATCH v4 5/9] target/mips: Add MXU instruction S8LDD
Date: Wed, 12 Sep 2018 13:19:42 -0700 [thread overview]
Message-ID: <8542d2e6-c2e2-fa86-28e6-af4be0929801@linaro.org> (raw)
In-Reply-To: <20180830193019.20104-6-jancraig@amazon.com>
On 08/30/2018 12:30 PM, Craig Janeczek via Qemu-devel wrote:
> + gen_load_mxu_cr(t0);
> + tcg_gen_andi_tl(t0, t0, MXUEN);
> + tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXUEN, l0);
Probably MXUEN should be included in env->hflags, and therefore
tested via ctx->hflags. (Which also means ending a TB after a
write to MCR, which can change this value).
The documentation says that if MXUEN is unset the result is
"unpredictable". What does real hardware do? Does it really
treat the instruction as a nop? Does it raise an exception?
Otherwise another possibility for "unpredictable" is to simply
execute the instruction. Which would certainly be the easiest
implementation...
r~
next prev parent reply other threads:[~2018-09-12 20:19 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-30 19:30 [Qemu-devel] [PATCH v4 0/9] Add limited MXU instruction support Craig Janeczek
2018-08-30 19:30 ` [Qemu-devel] [PATCH v4 1/9] target/mips: Introduce MXU registers Craig Janeczek
2018-09-12 19:59 ` Richard Henderson
2018-08-30 19:30 ` [Qemu-devel] [PATCH v4 2/9] target/mips: Add all MXU opcodes Craig Janeczek
2018-08-31 18:59 ` Aleksandar Markovic
2018-09-04 14:47 ` Janeczek, Craig
2018-08-30 19:30 ` [Qemu-devel] [PATCH v4 3/9] target/mips: Split mips instruction handling Craig Janeczek
2018-08-31 18:40 ` Aleksandar Markovic
2018-09-04 14:44 ` Janeczek, Craig
2018-09-05 17:21 ` Aleksandar Markovic
2018-09-05 17:25 ` Aleksandar Markovic
2018-08-30 19:30 ` [Qemu-devel] [PATCH v4 4/9] target/mips: Add MXU instructions S32I2M and S32M2I Craig Janeczek
2018-09-12 20:08 ` Richard Henderson
2018-08-30 19:30 ` [Qemu-devel] [PATCH v4 5/9] target/mips: Add MXU instruction S8LDD Craig Janeczek
2018-08-31 13:39 ` Aleksandar Markovic
2018-09-12 20:20 ` Richard Henderson
2018-09-12 20:19 ` Richard Henderson [this message]
2018-08-30 19:30 ` [Qemu-devel] [PATCH v4 6/9] target/mips: Add MXU instruction D16MUL Craig Janeczek
2018-08-30 19:30 ` [Qemu-devel] [PATCH v4 7/9] target/mips: Add MXU instruction D16MAC Craig Janeczek
2018-08-30 19:30 ` [Qemu-devel] [PATCH v4 8/9] target/mips: Add MXU instructions Q8MUL and Q8MULSU Craig Janeczek
2018-08-30 19:30 ` [Qemu-devel] [PATCH v4 9/9] target/mips: Add MXU instructions S32LDD and S32LDDR Craig Janeczek
2018-09-05 13:36 ` [Qemu-devel] [PATCH v4 0/9] Add limited MXU instruction support Aleksandar Markovic
2018-09-11 12:27 ` Janeczek, Craig
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