* [PATCH 0/5] Support GPIO for AST2700
@ 2024-09-23 9:42 Jamin Lin via
2024-09-23 9:42 ` [PATCH 1/5] hw/gpio/aspeed: Fix coding style Jamin Lin via
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Jamin Lin via @ 2024-09-23 9:42 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs,
open list:All patches CC here
Cc: jamin_lin, troy_lee, yunlin.tang
v1: support GPIO for AST2700
Jamin Lin (5):
hw/gpio/aspeed: Fix coding style
hw/gpio/aspeed: Support to set the different memory size
hw/gpio/aspeed: Support different memory region ops
hw/gpio/aspeed: Add AST2700 support
aspeed/soc: Support GPIO for AST2700
hw/arm/aspeed_ast27x0.c | 18 +-
hw/gpio/aspeed_gpio.c | 390 +++++++++++++++++++++++++++++++++-
include/hw/gpio/aspeed_gpio.h | 4 +-
3 files changed, 405 insertions(+), 7 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH 1/5] hw/gpio/aspeed: Fix coding style 2024-09-23 9:42 [PATCH 0/5] Support GPIO for AST2700 Jamin Lin via @ 2024-09-23 9:42 ` Jamin Lin via 2024-09-23 9:42 ` [PATCH 2/5] hw/gpio/aspeed: Support to set the different memory size Jamin Lin via ` (3 subsequent siblings) 4 siblings, 0 replies; 13+ messages in thread From: Jamin Lin via @ 2024-09-23 9:42 UTC (permalink / raw) To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs, open list:All patches CC here Cc: jamin_lin, troy_lee, yunlin.tang Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- hw/gpio/aspeed_gpio.c | 3 ++- include/hw/gpio/aspeed_gpio.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index 71756664dd..901b576144 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -340,7 +340,8 @@ static void aspeed_gpio_set_pin_level(AspeedGPIOState *s, uint32_t set_idx, value &= ~pin_mask; } - aspeed_gpio_update(s, &s->sets[set_idx], value, ~s->sets[set_idx].direction); + aspeed_gpio_update(s, &s->sets[set_idx], value, + ~s->sets[set_idx].direction); } /* diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h index 90a12ae318..39febda9ea 100644 --- a/include/hw/gpio/aspeed_gpio.h +++ b/include/hw/gpio/aspeed_gpio.h @@ -88,7 +88,7 @@ struct AspeedGPIOState { qemu_irq irq; qemu_irq gpios[ASPEED_GPIO_MAX_NR_SETS][ASPEED_GPIOS_PER_SET]; -/* Parallel GPIO Registers */ + /* Parallel GPIO Registers */ uint32_t debounce_regs[ASPEED_GPIO_NR_DEBOUNCE_REGS]; struct GPIOSets { uint32_t data_value; /* Reflects pin values */ -- 2.34.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/5] hw/gpio/aspeed: Support to set the different memory size 2024-09-23 9:42 [PATCH 0/5] Support GPIO for AST2700 Jamin Lin via 2024-09-23 9:42 ` [PATCH 1/5] hw/gpio/aspeed: Fix coding style Jamin Lin via @ 2024-09-23 9:42 ` Jamin Lin via 2024-09-23 9:42 ` [PATCH 3/5] hw/gpio/aspeed: Support different memory region ops Jamin Lin via ` (2 subsequent siblings) 4 siblings, 0 replies; 13+ messages in thread From: Jamin Lin via @ 2024-09-23 9:42 UTC (permalink / raw) To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs, open list:All patches CC here Cc: jamin_lin, troy_lee, yunlin.tang According to the datasheet of ASPEED SOCs, a GPIO controller owns 4KB of register space for AST2700, AST2500, AST2400 and AST1030; owns 2KB of register space for AST2600 1.8v and owns 2KB of register space for AST2600 3.3v. It set the memory region size 2KB by default and it does not compatible register space for AST2700. Introduce a new class attribute to set the GPIO controller memory size for different ASPEED SOCs. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- hw/gpio/aspeed_gpio.c | 7 ++++++- include/hw/gpio/aspeed_gpio.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index 901b576144..94a5f3ee03 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -1048,7 +1048,7 @@ static void aspeed_gpio_realize(DeviceState *dev, Error **errp) } memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s, - TYPE_ASPEED_GPIO, 0x800); + TYPE_ASPEED_GPIO, agc->mem_size); sysbus_init_mmio(sbd, &s->iomem); } @@ -1131,6 +1131,7 @@ static void aspeed_gpio_ast2400_class_init(ObjectClass *klass, void *data) agc->nr_gpio_sets = 7; agc->reg_table = aspeed_3_3v_gpios; agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; + agc->mem_size = 0x1000; } static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) @@ -1142,6 +1143,7 @@ static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) agc->nr_gpio_sets = 8; agc->reg_table = aspeed_3_3v_gpios; agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; + agc->mem_size = 0x1000; } static void aspeed_gpio_ast2600_3_3v_class_init(ObjectClass *klass, void *data) @@ -1153,6 +1155,7 @@ static void aspeed_gpio_ast2600_3_3v_class_init(ObjectClass *klass, void *data) agc->nr_gpio_sets = 7; agc->reg_table = aspeed_3_3v_gpios; agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; + agc->mem_size = 0x800; } static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data) @@ -1164,6 +1167,7 @@ static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data) agc->nr_gpio_sets = 2; agc->reg_table = aspeed_1_8v_gpios; agc->reg_table_count = GPIO_1_8V_REG_ARRAY_SIZE; + agc->mem_size = 0x800; } static void aspeed_gpio_1030_class_init(ObjectClass *klass, void *data) @@ -1175,6 +1179,7 @@ static void aspeed_gpio_1030_class_init(ObjectClass *klass, void *data) agc->nr_gpio_sets = 6; agc->reg_table = aspeed_3_3v_gpios; agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; + agc->mem_size = 0x1000; } static const TypeInfo aspeed_gpio_info = { diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h index 39febda9ea..8cd2ff5496 100644 --- a/include/hw/gpio/aspeed_gpio.h +++ b/include/hw/gpio/aspeed_gpio.h @@ -76,6 +76,7 @@ struct AspeedGPIOClass { uint32_t nr_gpio_sets; const AspeedGPIOReg *reg_table; unsigned reg_table_count; + uint64_t mem_size; }; struct AspeedGPIOState { -- 2.34.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/5] hw/gpio/aspeed: Support different memory region ops 2024-09-23 9:42 [PATCH 0/5] Support GPIO for AST2700 Jamin Lin via 2024-09-23 9:42 ` [PATCH 1/5] hw/gpio/aspeed: Fix coding style Jamin Lin via 2024-09-23 9:42 ` [PATCH 2/5] hw/gpio/aspeed: Support to set the different memory size Jamin Lin via @ 2024-09-23 9:42 ` Jamin Lin via 2024-09-23 9:42 ` [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support Jamin Lin via 2024-09-23 9:42 ` [PATCH 5/5] aspeed/soc: Support GPIO for AST2700 Jamin Lin via 4 siblings, 0 replies; 13+ messages in thread From: Jamin Lin via @ 2024-09-23 9:42 UTC (permalink / raw) To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs, open list:All patches CC here Cc: jamin_lin, troy_lee, yunlin.tang It set "aspeed_gpio_ops" struct which containing read and write callbacks to be used when I/O is performed on the GPIO region. Besides, in the previous design of ASPEED SOCs, one register is used for setting one function for 32 GPIO pins. ex: GPIO000 is used for setting data value for GPIO A, B, C and D in AST2600. ex: GPIO004 is used for setting direction for GPIO A, B, C and D in AST2600. However, the register set have a significant change in AST2700. Each GPIO pin has their own control register. In other words, users are able to set one GPIO pin’s direction, interrupt enable, input mask and so on in one register. The aspeed_gpio_read/aspeed_gpio_write callback functions are not compatible AST2700. Introduce a new "const MemoryRegionOps *" attribute in AspeedGPIOClass and use it in aspeed_gpio_realize function. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- hw/gpio/aspeed_gpio.c | 7 ++++++- include/hw/gpio/aspeed_gpio.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index 94a5f3ee03..f23ffae34d 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -1047,7 +1047,7 @@ static void aspeed_gpio_realize(DeviceState *dev, Error **errp) } } - memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s, + memory_region_init_io(&s->iomem, OBJECT(s), agc->reg_ops, s, TYPE_ASPEED_GPIO, agc->mem_size); sysbus_init_mmio(sbd, &s->iomem); @@ -1132,6 +1132,7 @@ static void aspeed_gpio_ast2400_class_init(ObjectClass *klass, void *data) agc->reg_table = aspeed_3_3v_gpios; agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; agc->mem_size = 0x1000; + agc->reg_ops = &aspeed_gpio_ops; } static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) @@ -1144,6 +1145,7 @@ static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) agc->reg_table = aspeed_3_3v_gpios; agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; agc->mem_size = 0x1000; + agc->reg_ops = &aspeed_gpio_ops; } static void aspeed_gpio_ast2600_3_3v_class_init(ObjectClass *klass, void *data) @@ -1156,6 +1158,7 @@ static void aspeed_gpio_ast2600_3_3v_class_init(ObjectClass *klass, void *data) agc->reg_table = aspeed_3_3v_gpios; agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; agc->mem_size = 0x800; + agc->reg_ops = &aspeed_gpio_ops; } static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data) @@ -1168,6 +1171,7 @@ static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data) agc->reg_table = aspeed_1_8v_gpios; agc->reg_table_count = GPIO_1_8V_REG_ARRAY_SIZE; agc->mem_size = 0x800; + agc->reg_ops = &aspeed_gpio_ops; } static void aspeed_gpio_1030_class_init(ObjectClass *klass, void *data) @@ -1180,6 +1184,7 @@ static void aspeed_gpio_1030_class_init(ObjectClass *klass, void *data) agc->reg_table = aspeed_3_3v_gpios; agc->reg_table_count = GPIO_3_3V_REG_ARRAY_SIZE; agc->mem_size = 0x1000; + agc->reg_ops = &aspeed_gpio_ops; } static const TypeInfo aspeed_gpio_info = { diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h index 8cd2ff5496..e1e6c54333 100644 --- a/include/hw/gpio/aspeed_gpio.h +++ b/include/hw/gpio/aspeed_gpio.h @@ -77,6 +77,7 @@ struct AspeedGPIOClass { const AspeedGPIOReg *reg_table; unsigned reg_table_count; uint64_t mem_size; + const MemoryRegionOps *reg_ops; }; struct AspeedGPIOState { -- 2.34.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support 2024-09-23 9:42 [PATCH 0/5] Support GPIO for AST2700 Jamin Lin via ` (2 preceding siblings ...) 2024-09-23 9:42 ` [PATCH 3/5] hw/gpio/aspeed: Support different memory region ops Jamin Lin via @ 2024-09-23 9:42 ` Jamin Lin via 2024-09-24 1:11 ` Andrew Jeffery 2024-09-23 9:42 ` [PATCH 5/5] aspeed/soc: Support GPIO for AST2700 Jamin Lin via 4 siblings, 1 reply; 13+ messages in thread From: Jamin Lin via @ 2024-09-23 9:42 UTC (permalink / raw) To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs, open list:All patches CC here Cc: jamin_lin, troy_lee, yunlin.tang AST2700 integrates two set of Parallel GPIO Controller with maximum 212 control pins, which are 27 groups. (H, exclude pin: H7 H6 H5 H4) In the previous design of ASPEED SOCs, one register is used for setting one function for one set which are 32 pins and 4 groups. ex: GPIO000 is used for setting data value for GPIO A, B, C and D in AST2600. ex: GPIO004 is used for setting direction for GPIO A, B, C and D in AST2600. However, the register set have a significant change since AST2700. Each GPIO pin has their own individual control register. In other words, users are able to set one GPIO pin’s direction, interrupt enable, input mask and so on in the same one register. Currently, aspeed_gpio_read/aspeed_gpio_write callback functions are not compatible AST2700. Introduce new aspeed_gpio_2700_read/aspeed_gpio_2700_write callback functions and aspeed_gpio_2700_ops memory region operation for AST2700. Introduce a new ast2700 class to support AST2700. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- hw/gpio/aspeed_gpio.c | 373 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 373 insertions(+) diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index f23ffae34d..e3d5556dc1 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -227,6 +227,38 @@ REG32(GPIO_INDEX_REG, 0x2AC) FIELD(GPIO_INDEX_REG, COMMAND_SRC_1, 21, 1) FIELD(GPIO_INDEX_REG, INPUT_MASK, 20, 1) +/* AST2700 GPIO Register Address Offsets */ +REG32(GPIO_2700_DEBOUNCE_TIME_1, 0x000) +REG32(GPIO_2700_DEBOUNCE_TIME_2, 0x004) +REG32(GPIO_2700_DEBOUNCE_TIME_3, 0x008) +REG32(GPIO_2700_INT_STATUS_1, 0x100) +REG32(GPIO_2700_INT_STATUS_2, 0x104) +REG32(GPIO_2700_INT_STATUS_3, 0x108) +REG32(GPIO_2700_INT_STATUS_4, 0x10C) +REG32(GPIO_2700_INT_STATUS_5, 0x110) +REG32(GPIO_2700_INT_STATUS_6, 0x114) +REG32(GPIO_2700_INT_STATUS_7, 0x118) +/* GPIOA0 - GPIOAA7 Control Register*/ +REG32(GPIO_A0_CONTROL, 0x180) + SHARED_FIELD(GPIO_CONTROL_OUT_DATA, 0, 1) + SHARED_FIELD(GPIO_CONTROL_DIRECTION, 1, 1) + SHARED_FIELD(GPIO_CONTROL_INT_ENABLE, 2, 1) + SHARED_FIELD(GPIO_CONTROL_INT_SENS_0, 3, 1) + SHARED_FIELD(GPIO_CONTROL_INT_SENS_1, 4, 1) + SHARED_FIELD(GPIO_CONTROL_INT_SENS_2, 5, 1) + SHARED_FIELD(GPIO_CONTROL_RESET_TOLERANCE, 6, 1) + SHARED_FIELD(GPIO_CONTROL_DEBOUNCE_1, 7, 1) + SHARED_FIELD(GPIO_CONTROL_DEBOUNCE_2, 8, 1) + SHARED_FIELD(GPIO_CONTROL_INPUT_MASK, 9, 1) + SHARED_FIELD(GPIO_CONTROL_BLINK_COUNTER_1, 10, 1) + SHARED_FIELD(GPIO_CONTROL_BLINK_COUNTER_2, 11, 1) + SHARED_FIELD(GPIO_CONTROL_INT_STATUS, 12, 1) + SHARED_FIELD(GPIO_CONTROL_IN_DATA, 13, 1) + SHARED_FIELD(GPIO_CONTROL_RESERVED, 14, 18) +REG32(GPIO_AA7_CONTROL, 0x4DC) +#define GPIO_2700_MEM_SIZE 0x4E0 +#define GPIO_2700_REG_ARRAY_SIZE (GPIO_2700_MEM_SIZE >> 2) + static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio) { uint32_t falling_edge = 0, rising_edge = 0; @@ -964,6 +996,309 @@ static void aspeed_gpio_set_pin(Object *obj, Visitor *v, const char *name, aspeed_gpio_set_pin_level(s, set_idx, pin, level); } +static uint64_t aspeed_gpio_read_control_reg(AspeedGPIOState *s, uint32_t pin) +{ + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); + GPIOSets *set; + uint64_t value = 0; + uint32_t set_idx; + uint32_t pin_idx; + + set_idx = pin / ASPEED_GPIOS_PER_SET; + pin_idx = pin % ASPEED_GPIOS_PER_SET; + + if (set_idx >= agc->nr_gpio_sets) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: set index: %d, out of bounds\n", + __func__, set_idx); + return 0; + } + + set = &s->sets[set_idx]; + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_OUT_DATA, + extract32(set->data_read, pin_idx, 1)); + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_DIRECTION, + extract32(set->direction, pin_idx, 1)); + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_ENABLE, + extract32(set->int_enable, pin_idx, 1)); + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_SENS_0, + extract32(set->int_sens_0, pin_idx, 1)); + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_SENS_1, + extract32(set->int_sens_1, pin_idx, 1)); + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_SENS_2, + extract32(set->int_sens_2, pin_idx, 1)); + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_RESET_TOLERANCE, + extract32(set->reset_tol, pin_idx, 1)); + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_DEBOUNCE_1, + extract32(set->debounce_1, pin_idx, 1)); + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_DEBOUNCE_2, + extract32(set->debounce_2, pin_idx, 1)); + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INPUT_MASK, + extract32(set->input_mask, pin_idx, 1)); + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_STATUS, + extract32(set->int_status, pin_idx, 1)); + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_IN_DATA, + extract32(set->data_value, pin_idx, 1)); + return value; +} + +static void aspeed_gpio_write_control_reg(AspeedGPIOState *s, + uint32_t pin, uint32_t type, uint64_t data) +{ + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); + const GPIOSetProperties *props; + GPIOSets *set; + uint32_t cleared; + uint32_t set_idx; + uint32_t pin_idx; + uint32_t group_value = 0; + + set_idx = pin / ASPEED_GPIOS_PER_SET; + pin_idx = pin % ASPEED_GPIOS_PER_SET; + + if (set_idx >= agc->nr_gpio_sets) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: set index: %d, out of bounds\n", + __func__, set_idx); + return; + } + + set = &s->sets[set_idx]; + props = &agc->props[set_idx]; + + /* direction */ + group_value = set->direction; + group_value = deposit32(group_value, pin_idx, 1, + SHARED_FIELD_EX32(data, GPIO_CONTROL_DIRECTION)); + /* + * where data is the value attempted to be written to the pin: + * pin type | input mask | output mask | expected value + * ------------------------------------------------------------ + * bidirectional | 1 | 1 | data + * input only | 1 | 0 | 0 + * output only | 0 | 1 | 1 + * no pin | 0 | 0 | 0 + * + * which is captured by: + * data = ( data | ~input) & output; + */ + group_value = (group_value | ~props->input) & props->output; + set->direction = update_value_control_source(set, set->direction, + group_value); + + /* out data */ + group_value = set->data_read; + group_value = deposit32(group_value, pin_idx, 1, + SHARED_FIELD_EX32(data, GPIO_CONTROL_OUT_DATA)); + group_value &= props->output; + group_value = update_value_control_source(set, set->data_read, + group_value); + set->data_read = group_value; + + /* interrupt enable */ + group_value = set->int_enable; + group_value = deposit32(group_value, pin_idx, 1, + SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_ENABLE)); + set->int_enable = update_value_control_source(set, set->int_enable, + group_value); + + /* interrupt sensitivity type 0 */ + group_value = set->int_sens_0; + group_value = deposit32(group_value, pin_idx, 1, + SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_SENS_0)); + set->int_sens_0 = update_value_control_source(set, set->int_sens_0, + group_value); + + /* interrupt sensitivity type 1 */ + group_value = set->int_sens_1; + group_value = deposit32(group_value, pin_idx, 1, + SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_SENS_1)); + set->int_sens_1 = update_value_control_source(set, set->int_sens_1, + group_value); + + /* interrupt sensitivity type 2 */ + group_value = set->int_sens_2; + group_value = deposit32(group_value, pin_idx, 1, + SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_SENS_2)); + set->int_sens_2 = update_value_control_source(set, set->int_sens_2, + group_value); + + /* reset tolerance enable */ + group_value = set->reset_tol; + group_value = deposit32(group_value, pin_idx, 1, + SHARED_FIELD_EX32(data, GPIO_CONTROL_RESET_TOLERANCE)); + set->reset_tol = update_value_control_source(set, set->reset_tol, + group_value); + + /* debounce 1 */ + group_value = set->debounce_1; + group_value = deposit32(group_value, pin_idx, 1, + SHARED_FIELD_EX32(data, GPIO_CONTROL_DEBOUNCE_1)); + set->debounce_1 = update_value_control_source(set, set->debounce_1, + group_value); + + /* debounce 2 */ + group_value = set->debounce_2; + group_value = deposit32(group_value, pin_idx, 1, + SHARED_FIELD_EX32(data, GPIO_CONTROL_DEBOUNCE_2)); + set->debounce_2 = update_value_control_source(set, set->debounce_2, + group_value); + + /* input mask */ + group_value = set->input_mask; + group_value = deposit32(group_value, pin_idx, 1, + SHARED_FIELD_EX32(data, GPIO_CONTROL_INPUT_MASK)); + /* + * feeds into interrupt generation + * 0: read from data value reg will be updated + * 1: read from data value reg will not be updated + */ + set->input_mask = group_value & props->input; + + /* blink counter 1 */ + /* blink counter 2 */ + /* unimplement */ + + /* interrupt status */ + group_value = set->int_status; + group_value = deposit32(group_value, pin_idx, 1, + SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_STATUS)); + cleared = ctpop32(group_value & set->int_status); + if (s->pending && cleared) { + assert(s->pending >= cleared); + s->pending -= cleared; + } + set->int_status &= ~group_value; + + aspeed_gpio_update(s, set, set->data_value, UINT32_MAX); + return; +} + +static uint64_t aspeed_gpio_2700_read(void *opaque, hwaddr offset, + uint32_t size) +{ + AspeedGPIOState *s = ASPEED_GPIO(opaque); + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); + GPIOSets *set; + uint64_t value; + uint64_t reg; + uint32_t pin; + uint32_t idx; + + reg = offset >> 2; + + if (reg >= agc->reg_table_count) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: offset 0x%" PRIx64 " out of bounds\n", + __func__, offset); + return 0; + } + + switch (reg) { + case R_GPIO_2700_DEBOUNCE_TIME_1 ... R_GPIO_2700_DEBOUNCE_TIME_3: + idx = reg - R_GPIO_2700_DEBOUNCE_TIME_1; + + if (idx >= ASPEED_GPIO_NR_DEBOUNCE_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: debounce index: %d, out of bounds\n", + __func__, idx); + return 0; + } + + value = (uint64_t) s->debounce_regs[idx]; + break; + case R_GPIO_2700_INT_STATUS_1 ... R_GPIO_2700_INT_STATUS_7: + idx = reg - R_GPIO_2700_INT_STATUS_1; + + if (idx >= agc->nr_gpio_sets) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: interrupt status index: %d, out of bounds\n", + __func__, idx); + return 0; + } + + set = &s->sets[idx]; + value = (uint64_t) set->int_status; + break; + case R_GPIO_A0_CONTROL ... R_GPIO_AA7_CONTROL: + pin = reg - R_GPIO_A0_CONTROL; + + if (pin >= agc->nr_gpio_pins) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid pin number: %d\n", + __func__, pin); + return 0; + } + + value = aspeed_gpio_read_control_reg(s, pin); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" + PRIx64"\n", __func__, offset); + return 0; + } + + trace_aspeed_gpio_read(offset, value); + return value; +} + +static void aspeed_gpio_2700_write(void *opaque, hwaddr offset, + uint64_t data, uint32_t size) +{ + AspeedGPIOState *s = ASPEED_GPIO(opaque); + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); + uint64_t reg; + uint32_t pin; + uint32_t type; + uint32_t idx; + + trace_aspeed_gpio_write(offset, data); + + reg = offset >> 2; + + if (reg >= agc->reg_table_count) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: offset 0x%" PRIx64 " out of bounds\n", + __func__, offset); + return; + } + + switch (reg) { + case R_GPIO_2700_DEBOUNCE_TIME_1 ... R_GPIO_2700_DEBOUNCE_TIME_3: + idx = reg - R_GPIO_2700_DEBOUNCE_TIME_1; + + if (idx >= ASPEED_GPIO_NR_DEBOUNCE_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: debounce index: %d out of bounds\n", + __func__, idx); + return; + } + + s->debounce_regs[idx] = (uint32_t) data; + break; + case R_GPIO_A0_CONTROL ... R_GPIO_AA7_CONTROL: + pin = reg - R_GPIO_A0_CONTROL; + + if (pin >= agc->nr_gpio_pins) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid pin number: %d\n", + __func__, pin); + return; + } + + if (SHARED_FIELD_EX32(data, GPIO_CONTROL_RESERVED)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid reserved data: 0x%" + PRIx64"\n", __func__, data); + return; + } + + aspeed_gpio_write_control_reg(s, pin, type, data); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" + PRIx64"\n", __func__, offset); + break; + } + + return; +} + /****************** Setup functions ******************/ static const GPIOSetProperties ast2400_set_props[ASPEED_GPIO_MAX_NR_SETS] = { [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, @@ -1010,6 +1345,16 @@ static GPIOSetProperties ast1030_set_props[ASPEED_GPIO_MAX_NR_SETS] = { [5] = {0x000000ff, 0x00000000, {"U"} }, }; +static GPIOSetProperties ast2700_set_props[ASPEED_GPIO_MAX_NR_SETS] = { + [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, + [1] = {0x0fffffff, 0x0fffffff, {"E", "F", "G", "H"} }, + [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, + [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, + [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, + [5] = {0xffffffff, 0xffffffff, {"U", "V", "W", "X"} }, + [6] = {0x00ffffff, 0x00ffffff, {"Y", "Z", "AA"} }, +}; + static const MemoryRegionOps aspeed_gpio_ops = { .read = aspeed_gpio_read, .write = aspeed_gpio_write, @@ -1018,6 +1363,14 @@ static const MemoryRegionOps aspeed_gpio_ops = { .valid.max_access_size = 4, }; +static const MemoryRegionOps aspeed_gpio_2700_ops = { + .read = aspeed_gpio_2700_read, + .write = aspeed_gpio_2700_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid.min_access_size = 4, + .valid.max_access_size = 4, +}; + static void aspeed_gpio_reset(DeviceState *dev) { AspeedGPIOState *s = ASPEED_GPIO(dev); @@ -1187,6 +1540,18 @@ static void aspeed_gpio_1030_class_init(ObjectClass *klass, void *data) agc->reg_ops = &aspeed_gpio_ops; } +static void aspeed_gpio_2700_class_init(ObjectClass *klass, void *data) +{ + AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); + + agc->props = ast2700_set_props; + agc->nr_gpio_pins = 216; + agc->nr_gpio_sets = 7; + agc->reg_table_count = GPIO_2700_REG_ARRAY_SIZE; + agc->mem_size = 0x1000; + agc->reg_ops = &aspeed_gpio_2700_ops; +} + static const TypeInfo aspeed_gpio_info = { .name = TYPE_ASPEED_GPIO, .parent = TYPE_SYS_BUS_DEVICE, @@ -1231,6 +1596,13 @@ static const TypeInfo aspeed_gpio_ast1030_info = { .instance_init = aspeed_gpio_init, }; +static const TypeInfo aspeed_gpio_ast2700_info = { + .name = TYPE_ASPEED_GPIO "-ast2700", + .parent = TYPE_ASPEED_GPIO, + .class_init = aspeed_gpio_2700_class_init, + .instance_init = aspeed_gpio_init, +}; + static void aspeed_gpio_register_types(void) { type_register_static(&aspeed_gpio_info); @@ -1239,6 +1611,7 @@ static void aspeed_gpio_register_types(void) type_register_static(&aspeed_gpio_ast2600_3_3v_info); type_register_static(&aspeed_gpio_ast2600_1_8v_info); type_register_static(&aspeed_gpio_ast1030_info); + type_register_static(&aspeed_gpio_ast2700_info); } type_init(aspeed_gpio_register_types); -- 2.34.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support 2024-09-23 9:42 ` [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support Jamin Lin via @ 2024-09-24 1:11 ` Andrew Jeffery 2024-09-24 3:03 ` Jamin Lin 0 siblings, 1 reply; 13+ messages in thread From: Andrew Jeffery @ 2024-09-24 1:11 UTC (permalink / raw) To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee, Joel Stanley, open list:ASPEED BMCs, open list:All patches CC here Cc: troy_lee, yunlin.tang Hi Jamin, On Mon, 2024-09-23 at 17:42 +0800, Jamin Lin wrote: > AST2700 integrates two set of Parallel GPIO Controller > with maximum 212 control pins, which are 27 groups. > (H, exclude pin: H7 H6 H5 H4) > > In the previous design of ASPEED SOCs, > one register is used for setting one function for one set which are 32 pins > and 4 groups. > ex: GPIO000 is used for setting data value for GPIO A, B, C and D in AST2600. > ex: GPIO004 is used for setting direction for GPIO A, B, C and D in AST2600. > > However, the register set have a significant change since AST2700. > Each GPIO pin has their own individual control register. In other words, users are able to > set one GPIO pin’s direction, interrupt enable, input mask and so on > in the same one register. > > Currently, aspeed_gpio_read/aspeed_gpio_write callback functions > are not compatible AST2700. > Introduce new aspeed_gpio_2700_read/aspeed_gpio_2700_write callback functions > and aspeed_gpio_2700_ops memory region operation for AST2700. > Introduce a new ast2700 class to support AST2700. > > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> > --- > hw/gpio/aspeed_gpio.c | 373 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 373 insertions(+) > > diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c > index f23ffae34d..e3d5556dc1 100644 > --- a/hw/gpio/aspeed_gpio.c > +++ b/hw/gpio/aspeed_gpio.c > @@ -227,6 +227,38 @@ REG32(GPIO_INDEX_REG, 0x2AC) > FIELD(GPIO_INDEX_REG, COMMAND_SRC_1, 21, 1) > FIELD(GPIO_INDEX_REG, INPUT_MASK, 20, 1) > > +/* AST2700 GPIO Register Address Offsets */ > +REG32(GPIO_2700_DEBOUNCE_TIME_1, 0x000) > +REG32(GPIO_2700_DEBOUNCE_TIME_2, 0x004) > +REG32(GPIO_2700_DEBOUNCE_TIME_3, 0x008) > +REG32(GPIO_2700_INT_STATUS_1, 0x100) > +REG32(GPIO_2700_INT_STATUS_2, 0x104) > +REG32(GPIO_2700_INT_STATUS_3, 0x108) > +REG32(GPIO_2700_INT_STATUS_4, 0x10C) > +REG32(GPIO_2700_INT_STATUS_5, 0x110) > +REG32(GPIO_2700_INT_STATUS_6, 0x114) > +REG32(GPIO_2700_INT_STATUS_7, 0x118) > +/* GPIOA0 - GPIOAA7 Control Register*/ > +REG32(GPIO_A0_CONTROL, 0x180) > + SHARED_FIELD(GPIO_CONTROL_OUT_DATA, 0, 1) > + SHARED_FIELD(GPIO_CONTROL_DIRECTION, 1, 1) > + SHARED_FIELD(GPIO_CONTROL_INT_ENABLE, 2, 1) > + SHARED_FIELD(GPIO_CONTROL_INT_SENS_0, 3, 1) > + SHARED_FIELD(GPIO_CONTROL_INT_SENS_1, 4, 1) > + SHARED_FIELD(GPIO_CONTROL_INT_SENS_2, 5, 1) > + SHARED_FIELD(GPIO_CONTROL_RESET_TOLERANCE, 6, 1) > + SHARED_FIELD(GPIO_CONTROL_DEBOUNCE_1, 7, 1) > + SHARED_FIELD(GPIO_CONTROL_DEBOUNCE_2, 8, 1) > + SHARED_FIELD(GPIO_CONTROL_INPUT_MASK, 9, 1) > + SHARED_FIELD(GPIO_CONTROL_BLINK_COUNTER_1, 10, 1) > + SHARED_FIELD(GPIO_CONTROL_BLINK_COUNTER_2, 11, 1) > + SHARED_FIELD(GPIO_CONTROL_INT_STATUS, 12, 1) > + SHARED_FIELD(GPIO_CONTROL_IN_DATA, 13, 1) > + SHARED_FIELD(GPIO_CONTROL_RESERVED, 14, 18) > +REG32(GPIO_AA7_CONTROL, 0x4DC) > +#define GPIO_2700_MEM_SIZE 0x4E0 > +#define GPIO_2700_REG_ARRAY_SIZE (GPIO_2700_MEM_SIZE >> 2) > + > static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio) > { > uint32_t falling_edge = 0, rising_edge = 0; > @@ -964,6 +996,309 @@ static void aspeed_gpio_set_pin(Object *obj, Visitor *v, const char *name, > aspeed_gpio_set_pin_level(s, set_idx, pin, level); > } > > +static uint64_t aspeed_gpio_read_control_reg(AspeedGPIOState *s, uint32_t pin) This function is specific to the AST2700 and I think the name should reflect that. > +{ > + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); > + GPIOSets *set; > + uint64_t value = 0; > + uint32_t set_idx; > + uint32_t pin_idx; > + > + set_idx = pin / ASPEED_GPIOS_PER_SET; > + pin_idx = pin % ASPEED_GPIOS_PER_SET; > + > + if (set_idx >= agc->nr_gpio_sets) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: set index: %d, out of bounds\n", > + __func__, set_idx); > + return 0; > + } > + > + set = &s->sets[set_idx]; > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_OUT_DATA, > + extract32(set->data_read, pin_idx, 1)); > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_DIRECTION, > + extract32(set->direction, pin_idx, 1)); > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_ENABLE, > + extract32(set->int_enable, pin_idx, 1)); > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_SENS_0, > + extract32(set->int_sens_0, pin_idx, 1)); > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_SENS_1, > + extract32(set->int_sens_1, pin_idx, 1)); > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_SENS_2, > + extract32(set->int_sens_2, pin_idx, 1)); > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_RESET_TOLERANCE, > + extract32(set->reset_tol, pin_idx, 1)); > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_DEBOUNCE_1, > + extract32(set->debounce_1, pin_idx, 1)); > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_DEBOUNCE_2, > + extract32(set->debounce_2, pin_idx, 1)); > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INPUT_MASK, > + extract32(set->input_mask, pin_idx, 1)); > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_STATUS, > + extract32(set->int_status, pin_idx, 1)); > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_IN_DATA, > + extract32(set->data_value, pin_idx, 1)); > + return value; > +} > + > +static void aspeed_gpio_write_control_reg(AspeedGPIOState *s, Also should reflect it's specific to the AST2700? > + uint32_t pin, uint32_t type, uint64_t data) > +{ > + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); > + const GPIOSetProperties *props; > + GPIOSets *set; > + uint32_t cleared; > + uint32_t set_idx; > + uint32_t pin_idx; > + uint32_t group_value = 0; > + > + set_idx = pin / ASPEED_GPIOS_PER_SET; > + pin_idx = pin % ASPEED_GPIOS_PER_SET; > + > + if (set_idx >= agc->nr_gpio_sets) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: set index: %d, out of bounds\n", > + __func__, set_idx); > + return; > + } > + > + set = &s->sets[set_idx]; > + props = &agc->props[set_idx]; > + > + /* direction */ > + group_value = set->direction; > + group_value = deposit32(group_value, pin_idx, 1, > + SHARED_FIELD_EX32(data, GPIO_CONTROL_DIRECTION)); > + /* > + * where data is the value attempted to be written to the pin: > + * pin type | input mask | output mask | expected value > + * ------------------------------------------------------------ > + * bidirectional | 1 | 1 | data > + * input only | 1 | 0 | 0 > + * output only | 0 | 1 | 1 > + * no pin | 0 | 0 | 0 > + * > + * which is captured by: > + * data = ( data | ~input) & output; > + */ > + group_value = (group_value | ~props->input) & props->output; > + set->direction = update_value_control_source(set, set->direction, > + group_value); > + > + /* out data */ > + group_value = set->data_read; > + group_value = deposit32(group_value, pin_idx, 1, > + SHARED_FIELD_EX32(data, GPIO_CONTROL_OUT_DATA)); > + group_value &= props->output; > + group_value = update_value_control_source(set, set->data_read, > + group_value); > + set->data_read = group_value; > + > + /* interrupt enable */ > + group_value = set->int_enable; > + group_value = deposit32(group_value, pin_idx, 1, > + SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_ENABLE)); > + set->int_enable = update_value_control_source(set, set->int_enable, > + group_value); > + > + /* interrupt sensitivity type 0 */ > + group_value = set->int_sens_0; > + group_value = deposit32(group_value, pin_idx, 1, > + SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_SENS_0)); > + set->int_sens_0 = update_value_control_source(set, set->int_sens_0, > + group_value); > + > + /* interrupt sensitivity type 1 */ > + group_value = set->int_sens_1; > + group_value = deposit32(group_value, pin_idx, 1, > + SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_SENS_1)); > + set->int_sens_1 = update_value_control_source(set, set->int_sens_1, > + group_value); > + > + /* interrupt sensitivity type 2 */ > + group_value = set->int_sens_2; > + group_value = deposit32(group_value, pin_idx, 1, > + SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_SENS_2)); > + set->int_sens_2 = update_value_control_source(set, set->int_sens_2, > + group_value); > + > + /* reset tolerance enable */ > + group_value = set->reset_tol; > + group_value = deposit32(group_value, pin_idx, 1, > + SHARED_FIELD_EX32(data, GPIO_CONTROL_RESET_TOLERANCE)); > + set->reset_tol = update_value_control_source(set, set->reset_tol, > + group_value); > + > + /* debounce 1 */ > + group_value = set->debounce_1; > + group_value = deposit32(group_value, pin_idx, 1, > + SHARED_FIELD_EX32(data, GPIO_CONTROL_DEBOUNCE_1)); > + set->debounce_1 = update_value_control_source(set, set->debounce_1, > + group_value); > + > + /* debounce 2 */ > + group_value = set->debounce_2; > + group_value = deposit32(group_value, pin_idx, 1, > + SHARED_FIELD_EX32(data, GPIO_CONTROL_DEBOUNCE_2)); > + set->debounce_2 = update_value_control_source(set, set->debounce_2, > + group_value); > + > + /* input mask */ > + group_value = set->input_mask; > + group_value = deposit32(group_value, pin_idx, 1, > + SHARED_FIELD_EX32(data, GPIO_CONTROL_INPUT_MASK)); > + /* > + * feeds into interrupt generation > + * 0: read from data value reg will be updated > + * 1: read from data value reg will not be updated > + */ > + set->input_mask = group_value & props->input; > + > + /* blink counter 1 */ > + /* blink counter 2 */ > + /* unimplement */ > + > + /* interrupt status */ > + group_value = set->int_status; > + group_value = deposit32(group_value, pin_idx, 1, > + SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_STATUS)); This makes me a bit wary. The interrupt status field is W1C, where a set bit on read indicates an interrupt is pending. If the bit extracted from data is set it should clear the corresponding bit in group_value. However, if the extracted bit is clear then the value of the corresponding bit in group_value should be unchanged. SHARED_FIELD_EX32() extracts the interrupt status bit from the write (data). group_value is set to the set's interrupt status, which means that for any pin with an interrupt pending, the corresponding bit is set. The deposit32() call updates the bit at pin_idx in the group, using the value extracted from the write (data). However, the result is that if the interrupt was pending and the write was acknowledging it, then the update has no effect. Alternatively, if the interrupt was pending but the write was acknowledging it, then the update will mark the interrupt as pending. Or, if the interrupt was pending but the write was _not_ acknowledging it, then the interrupt will _no longer_ be marked pending. If this is intentional it feels a bit hard to follow. > + cleared = ctpop32(group_value & set->int_status); Can this rather be expressed as ``` cleared = SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_STATUS); ``` > + if (s->pending && cleared) { > + assert(s->pending >= cleared); > + s->pending -= cleared; We're only ever going to be subtracting 1, as each GPIO has its own register. This feels overly abstract. > + } > + set->int_status &= ~group_value; This feels like it misbehaves in the face of multiple pending interrupts. For example, say we have an interrupt pending for GPIOA0, where the following statements are true: set->int_status == 0b01 s->pending == 1 Before it is acknowledged, an interrupt becomes pending for GPIOA1: set->int_status == 0b11 s->pending == 2 A write is issued to acknowledge the interrupt for GPIOA0. This causes the following sequence: group_value == 0b11 cleared == 2 s->pending = 0 set->int_status == 0b00 It seems the pending interrupt for GPIOA1 is lost? > + > + aspeed_gpio_update(s, set, set->data_value, UINT32_MAX); > + return; > +} > + > +static uint64_t aspeed_gpio_2700_read(void *opaque, hwaddr offset, > + uint32_t size) > +{ > + AspeedGPIOState *s = ASPEED_GPIO(opaque); > + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); > + GPIOSets *set; > + uint64_t value; > + uint64_t reg; > + uint32_t pin; > + uint32_t idx; > + > + reg = offset >> 2; > + > + if (reg >= agc->reg_table_count) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: offset 0x%" PRIx64 " out of bounds\n", > + __func__, offset); > + return 0; > + } > + > + switch (reg) { > + case R_GPIO_2700_DEBOUNCE_TIME_1 ... R_GPIO_2700_DEBOUNCE_TIME_3: > + idx = reg - R_GPIO_2700_DEBOUNCE_TIME_1; > + > + if (idx >= ASPEED_GPIO_NR_DEBOUNCE_REGS) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: debounce index: %d, out of bounds\n", > + __func__, idx); > + return 0; > + } > + > + value = (uint64_t) s->debounce_regs[idx]; > + break; > + case R_GPIO_2700_INT_STATUS_1 ... R_GPIO_2700_INT_STATUS_7: > + idx = reg - R_GPIO_2700_INT_STATUS_1; > + > + if (idx >= agc->nr_gpio_sets) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: interrupt status index: %d, out of bounds\n", > + __func__, idx); > + return 0; > + } > + > + set = &s->sets[idx]; > + value = (uint64_t) set->int_status; > + break; > + case R_GPIO_A0_CONTROL ... R_GPIO_AA7_CONTROL: > + pin = reg - R_GPIO_A0_CONTROL; > + > + if (pin >= agc->nr_gpio_pins) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid pin number: %d\n", > + __func__, pin); > + return 0; > + } > + > + value = aspeed_gpio_read_control_reg(s, pin); > + break; > + default: > + qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" > + PRIx64"\n", __func__, offset); > + return 0; > + } > + > + trace_aspeed_gpio_read(offset, value); > + return value; > +} > + > +static void aspeed_gpio_2700_write(void *opaque, hwaddr offset, > + uint64_t data, uint32_t size) > +{ > + AspeedGPIOState *s = ASPEED_GPIO(opaque); > + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); > + uint64_t reg; > + uint32_t pin; > + uint32_t type; > + uint32_t idx; > + > + trace_aspeed_gpio_write(offset, data); > + > + reg = offset >> 2; > + > + if (reg >= agc->reg_table_count) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: offset 0x%" PRIx64 " out of bounds\n", > + __func__, offset); > + return; > + } > + > + switch (reg) { > + case R_GPIO_2700_DEBOUNCE_TIME_1 ... R_GPIO_2700_DEBOUNCE_TIME_3: > + idx = reg - R_GPIO_2700_DEBOUNCE_TIME_1; > + > + if (idx >= ASPEED_GPIO_NR_DEBOUNCE_REGS) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: debounce index: %d out of bounds\n", > + __func__, idx); > + return; > + } > + > + s->debounce_regs[idx] = (uint32_t) data; > + break; > + case R_GPIO_A0_CONTROL ... R_GPIO_AA7_CONTROL: > + pin = reg - R_GPIO_A0_CONTROL; > + > + if (pin >= agc->nr_gpio_pins) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid pin number: %d\n", > + __func__, pin); > + return; > + } > + > + if (SHARED_FIELD_EX32(data, GPIO_CONTROL_RESERVED)) { > + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid reserved data: 0x%" > + PRIx64"\n", __func__, data); > + return; > + } > + > + aspeed_gpio_write_control_reg(s, pin, type, data); > + break; > + default: > + qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" > + PRIx64"\n", __func__, offset); > + break; > + } > + > + return; > +} > + > /****************** Setup functions ******************/ Bit of a nitpick, but I'm not personally a fan of banner comments like this. Andrew ^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support 2024-09-24 1:11 ` Andrew Jeffery @ 2024-09-24 3:03 ` Jamin Lin 2024-09-24 6:48 ` Jamin Lin 2024-09-24 23:55 ` Andrew Jeffery 0 siblings, 2 replies; 13+ messages in thread From: Jamin Lin @ 2024-09-24 3:03 UTC (permalink / raw) To: Andrew Jeffery, Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee, Joel Stanley, open list:ASPEED BMCs, open list:All patches CC here Cc: Troy Lee, Yunlin Tang Hi Andrew, > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support > > Hi Jamin, > > On Mon, 2024-09-23 at 17:42 +0800, Jamin Lin wrote: > > AST2700 integrates two set of Parallel GPIO Controller with maximum > > 212 control pins, which are 27 groups. > > (H, exclude pin: H7 H6 H5 H4) > > > > In the previous design of ASPEED SOCs, one register is used for > > setting one function for one set which are 32 pins and 4 groups. > > ex: GPIO000 is used for setting data value for GPIO A, B, C and D in AST2600. > > ex: GPIO004 is used for setting direction for GPIO A, B, C and D in AST2600. > > > > However, the register set have a significant change since AST2700. > > Each GPIO pin has their own individual control register. In other > > words, users are able to set one GPIO pin’s direction, interrupt > > enable, input mask and so on in the same one register. > > > > Currently, aspeed_gpio_read/aspeed_gpio_write callback functions are > > not compatible AST2700. > > Introduce new aspeed_gpio_2700_read/aspeed_gpio_2700_write callback > > functions and aspeed_gpio_2700_ops memory region operation for AST2700. > > Introduce a new ast2700 class to support AST2700. > > > > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> > > --- > > hw/gpio/aspeed_gpio.c | 373 > > ++++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 373 insertions(+) > > > > diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index > > f23ffae34d..e3d5556dc1 100644 > > --- a/hw/gpio/aspeed_gpio.c > > +++ b/hw/gpio/aspeed_gpio.c > > @@ -227,6 +227,38 @@ REG32(GPIO_INDEX_REG, 0x2AC) > > FIELD(GPIO_INDEX_REG, COMMAND_SRC_1, 21, 1) > > FIELD(GPIO_INDEX_REG, INPUT_MASK, 20, 1) > > > > +/* AST2700 GPIO Register Address Offsets */ > > +REG32(GPIO_2700_DEBOUNCE_TIME_1, 0x000) > > +REG32(GPIO_2700_DEBOUNCE_TIME_2, 0x004) > > +REG32(GPIO_2700_DEBOUNCE_TIME_3, 0x008) > REG32(GPIO_2700_INT_STATUS_1, > > +0x100) REG32(GPIO_2700_INT_STATUS_2, 0x104) > > +REG32(GPIO_2700_INT_STATUS_3, 0x108) > REG32(GPIO_2700_INT_STATUS_4, > > +0x10C) REG32(GPIO_2700_INT_STATUS_5, 0x110) > > +REG32(GPIO_2700_INT_STATUS_6, 0x114) > REG32(GPIO_2700_INT_STATUS_7, > > +0x118) > > +/* GPIOA0 - GPIOAA7 Control Register*/ REG32(GPIO_A0_CONTROL, > 0x180) > > + SHARED_FIELD(GPIO_CONTROL_OUT_DATA, 0, 1) > > + SHARED_FIELD(GPIO_CONTROL_DIRECTION, 1, 1) > > + SHARED_FIELD(GPIO_CONTROL_INT_ENABLE, 2, 1) > > + SHARED_FIELD(GPIO_CONTROL_INT_SENS_0, 3, 1) > > + SHARED_FIELD(GPIO_CONTROL_INT_SENS_1, 4, 1) > > + SHARED_FIELD(GPIO_CONTROL_INT_SENS_2, 5, 1) > > + SHARED_FIELD(GPIO_CONTROL_RESET_TOLERANCE, 6, 1) > > + SHARED_FIELD(GPIO_CONTROL_DEBOUNCE_1, 7, 1) > > + SHARED_FIELD(GPIO_CONTROL_DEBOUNCE_2, 8, 1) > > + SHARED_FIELD(GPIO_CONTROL_INPUT_MASK, 9, 1) > > + SHARED_FIELD(GPIO_CONTROL_BLINK_COUNTER_1, 10, 1) > > + SHARED_FIELD(GPIO_CONTROL_BLINK_COUNTER_2, 11, 1) > > + SHARED_FIELD(GPIO_CONTROL_INT_STATUS, 12, 1) > > + SHARED_FIELD(GPIO_CONTROL_IN_DATA, 13, 1) > > + SHARED_FIELD(GPIO_CONTROL_RESERVED, 14, 18) > > +REG32(GPIO_AA7_CONTROL, 0x4DC) #define GPIO_2700_MEM_SIZE 0x4E0 > > +#define GPIO_2700_REG_ARRAY_SIZE (GPIO_2700_MEM_SIZE >> 2) > > + > > static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, > > int gpio) { > > uint32_t falling_edge = 0, rising_edge = 0; @@ -964,6 +996,309 @@ > > static void aspeed_gpio_set_pin(Object *obj, Visitor *v, const char *name, > > aspeed_gpio_set_pin_level(s, set_idx, pin, level); } > > > > +static uint64_t aspeed_gpio_read_control_reg(AspeedGPIOState *s, > > +uint32_t pin) > > This function is specific to the AST2700 and I think the name should reflect > that. > Will rename it. > > +{ > > + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); > > + GPIOSets *set; > > + uint64_t value = 0; > > + uint32_t set_idx; > > + uint32_t pin_idx; > > + > > + set_idx = pin / ASPEED_GPIOS_PER_SET; > > + pin_idx = pin % ASPEED_GPIOS_PER_SET; > > + > > + if (set_idx >= agc->nr_gpio_sets) { > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: set index: %d, out of > bounds\n", > > + __func__, set_idx); > > + return 0; > > + } > > + > > + set = &s->sets[set_idx]; > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_OUT_DATA, > > + extract32(set->data_read, pin_idx, 1)); > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_DIRECTION, > > + extract32(set->direction, pin_idx, 1)); > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_ENABLE, > > + extract32(set->int_enable, pin_idx, 1)); > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_SENS_0, > > + extract32(set->int_sens_0, pin_idx, 1)); > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_SENS_1, > > + extract32(set->int_sens_1, pin_idx, 1)); > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_SENS_2, > > + extract32(set->int_sens_2, pin_idx, 1)); > > + value = SHARED_FIELD_DP32(value, > GPIO_CONTROL_RESET_TOLERANCE, > > + extract32(set->reset_tol, pin_idx, 1)); > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_DEBOUNCE_1, > > + extract32(set->debounce_1, pin_idx, > 1)); > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_DEBOUNCE_2, > > + extract32(set->debounce_2, pin_idx, > 1)); > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INPUT_MASK, > > + extract32(set->input_mask, pin_idx, > 1)); > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_STATUS, > > + extract32(set->int_status, pin_idx, 1)); > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_IN_DATA, > > + extract32(set->data_value, pin_idx, > 1)); > > + return value; > > +} > > + > > +static void aspeed_gpio_write_control_reg(AspeedGPIOState *s, > > Also should reflect it's specific to the AST2700? > Will rename it. > > + uint32_t pin, uint32_t type, uint64_t data) { > > + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); > > + const GPIOSetProperties *props; > > + GPIOSets *set; > > + uint32_t cleared; > > + uint32_t set_idx; > > + uint32_t pin_idx; > > + uint32_t group_value = 0; > > + > > + set_idx = pin / ASPEED_GPIOS_PER_SET; > > + pin_idx = pin % ASPEED_GPIOS_PER_SET; > > + > > + if (set_idx >= agc->nr_gpio_sets) { > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: set index: %d, out of > bounds\n", > > + __func__, set_idx); > > + return; > > + } > > + > > + set = &s->sets[set_idx]; > > + props = &agc->props[set_idx]; > > + > > + /* direction */ > > + group_value = set->direction; > > + group_value = deposit32(group_value, pin_idx, 1, > > + SHARED_FIELD_EX32(data, > GPIO_CONTROL_DIRECTION)); > > + /* > > + * where data is the value attempted to be written to the pin: > > + * pin type | input mask | output mask | expected value > > + * ------------------------------------------------------------ > > + * bidirectional | 1 | 1 | data > > + * input only | 1 | 0 | 0 > > + * output only | 0 | 1 | 1 > > + * no pin | 0 | 0 | 0 > > + * > > + * which is captured by: > > + * data = ( data | ~input) & output; > > + */ > > + group_value = (group_value | ~props->input) & props->output; > > + set->direction = update_value_control_source(set, set->direction, > > + group_value); > > + > > + /* out data */ > > + group_value = set->data_read; > > + group_value = deposit32(group_value, pin_idx, 1, > > + SHARED_FIELD_EX32(data, > GPIO_CONTROL_OUT_DATA)); > > + group_value &= props->output; > > + group_value = update_value_control_source(set, set->data_read, > > + group_value); > > + set->data_read = group_value; > > + > > + /* interrupt enable */ > > + group_value = set->int_enable; > > + group_value = deposit32(group_value, pin_idx, 1, > > + SHARED_FIELD_EX32(data, > GPIO_CONTROL_INT_ENABLE)); > > + set->int_enable = update_value_control_source(set, set->int_enable, > > + group_value); > > + > > + /* interrupt sensitivity type 0 */ > > + group_value = set->int_sens_0; > > + group_value = deposit32(group_value, pin_idx, 1, > > + SHARED_FIELD_EX32(data, > GPIO_CONTROL_INT_SENS_0)); > > + set->int_sens_0 = update_value_control_source(set, set->int_sens_0, > > + group_value); > > + > > + /* interrupt sensitivity type 1 */ > > + group_value = set->int_sens_1; > > + group_value = deposit32(group_value, pin_idx, 1, > > + SHARED_FIELD_EX32(data, > GPIO_CONTROL_INT_SENS_1)); > > + set->int_sens_1 = update_value_control_source(set, set->int_sens_1, > > + group_value); > > + > > + /* interrupt sensitivity type 2 */ > > + group_value = set->int_sens_2; > > + group_value = deposit32(group_value, pin_idx, 1, > > + SHARED_FIELD_EX32(data, > GPIO_CONTROL_INT_SENS_2)); > > + set->int_sens_2 = update_value_control_source(set, set->int_sens_2, > > + group_value); > > + > > + /* reset tolerance enable */ > > + group_value = set->reset_tol; > > + group_value = deposit32(group_value, pin_idx, 1, > > + SHARED_FIELD_EX32(data, > GPIO_CONTROL_RESET_TOLERANCE)); > > + set->reset_tol = update_value_control_source(set, set->reset_tol, > > + group_value); > > + > > + /* debounce 1 */ > > + group_value = set->debounce_1; > > + group_value = deposit32(group_value, pin_idx, 1, > > + SHARED_FIELD_EX32(data, > GPIO_CONTROL_DEBOUNCE_1)); > > + set->debounce_1 = update_value_control_source(set, > set->debounce_1, > > + group_value); > > + > > + /* debounce 2 */ > > + group_value = set->debounce_2; > > + group_value = deposit32(group_value, pin_idx, 1, > > + SHARED_FIELD_EX32(data, > GPIO_CONTROL_DEBOUNCE_2)); > > + set->debounce_2 = update_value_control_source(set, > set->debounce_2, > > + group_value); > > + > > + /* input mask */ > > + group_value = set->input_mask; > > + group_value = deposit32(group_value, pin_idx, 1, > > + SHARED_FIELD_EX32(data, > GPIO_CONTROL_INPUT_MASK)); > > + /* > > + * feeds into interrupt generation > > + * 0: read from data value reg will be updated > > + * 1: read from data value reg will not be updated > > + */ > > + set->input_mask = group_value & props->input; > > + > > + /* blink counter 1 */ > > + /* blink counter 2 */ > > + /* unimplement */ > > + > > + /* interrupt status */ > > + group_value = set->int_status; > > + group_value = deposit32(group_value, pin_idx, 1, > > + SHARED_FIELD_EX32(data, > > + GPIO_CONTROL_INT_STATUS)); > > This makes me a bit wary. > > The interrupt status field is W1C, where a set bit on read indicates an interrupt > is pending. If the bit extracted from data is set it should clear the > corresponding bit in group_value. However, if the extracted bit is clear then > the value of the corresponding bit in group_value should be unchanged. > > SHARED_FIELD_EX32() extracts the interrupt status bit from the write (data). > group_value is set to the set's interrupt status, which means that for any pin > with an interrupt pending, the corresponding bit is set. The deposit32() call > updates the bit at pin_idx in the group, using the value extracted from the > write (data). > > However, the result is that if the interrupt was pending and the write was > acknowledging it, then the update has no effect. Alternatively, if the interrupt > was pending but the write was acknowledging it, then the update will mark the > interrupt as pending. Or, if the interrupt was pending but the write was _not_ > acknowledging it, then the interrupt will _no longer_ be marked pending. If > this is intentional it feels a bit hard to follow. > > > + cleared = ctpop32(group_value & set->int_status); > > Can this rather be expressed as > > ``` > cleared = SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_STATUS); ``` > > > + if (s->pending && cleared) { > > + assert(s->pending >= cleared); > > + s->pending -= cleared; > > We're only ever going to be subtracting 1, as each GPIO has its own register. > This feels overly abstract. > > > + } > > + set->int_status &= ~group_value; > > This feels like it misbehaves in the face of multiple pending interrupts. > > For example, say we have an interrupt pending for GPIOA0, where the > following statements are true: > > set->int_status == 0b01 > s->pending == 1 > > Before it is acknowledged, an interrupt becomes pending for GPIOA1: > > set->int_status == 0b11 > s->pending == 2 > > A write is issued to acknowledge the interrupt for GPIOA0. This causes the > following sequence: > > group_value == 0b11 > cleared == 2 > s->pending = 0 > set->int_status == 0b00 > > It seems the pending interrupt for GPIOA1 is lost? > Thanks for review and input. I should check "int_status" bit of write data in write callback function. If 1 clear status flag(group value), else should not change group value. I am checking and testing this issue and will update to you or directly resend the new patch series. > > + > > + aspeed_gpio_update(s, set, set->data_value, UINT32_MAX); > > + return; > > +} > > + > > +static uint64_t aspeed_gpio_2700_read(void *opaque, hwaddr offset, > > + uint32_t size) { > > + AspeedGPIOState *s = ASPEED_GPIO(opaque); > > + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); > > + GPIOSets *set; > > + uint64_t value; > > + uint64_t reg; > > + uint32_t pin; > > + uint32_t idx; > > + > > + reg = offset >> 2; > > + > > + if (reg >= agc->reg_table_count) { > > + qemu_log_mask(LOG_GUEST_ERROR, > > + "%s: offset 0x%" PRIx64 " out of bounds\n", > > + __func__, offset); > > + return 0; > > + } > > + > > + switch (reg) { > > + case R_GPIO_2700_DEBOUNCE_TIME_1 ... > R_GPIO_2700_DEBOUNCE_TIME_3: > > + idx = reg - R_GPIO_2700_DEBOUNCE_TIME_1; > > + > > + if (idx >= ASPEED_GPIO_NR_DEBOUNCE_REGS) { > > + qemu_log_mask(LOG_GUEST_ERROR, > > + "%s: debounce index: %d, out of bounds\n", > > + __func__, idx); > > + return 0; > > + } > > + > > + value = (uint64_t) s->debounce_regs[idx]; > > + break; > > + case R_GPIO_2700_INT_STATUS_1 ... R_GPIO_2700_INT_STATUS_7: > > + idx = reg - R_GPIO_2700_INT_STATUS_1; > > + > > + if (idx >= agc->nr_gpio_sets) { > > + qemu_log_mask(LOG_GUEST_ERROR, > > + "%s: interrupt status index: %d, out of > bounds\n", > > + __func__, idx); > > + return 0; > > + } > > + > > + set = &s->sets[idx]; > > + value = (uint64_t) set->int_status; > > + break; > > + case R_GPIO_A0_CONTROL ... R_GPIO_AA7_CONTROL: > > + pin = reg - R_GPIO_A0_CONTROL; > > + > > + if (pin >= agc->nr_gpio_pins) { > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid pin > number: %d\n", > > + __func__, pin); > > + return 0; > > + } > > + > > + value = aspeed_gpio_read_control_reg(s, pin); > > + break; > > + default: > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset > 0x%" > > + PRIx64"\n", __func__, offset); > > + return 0; > > + } > > + > > + trace_aspeed_gpio_read(offset, value); > > + return value; > > +} > > + > > +static void aspeed_gpio_2700_write(void *opaque, hwaddr offset, > > + uint64_t data, uint32_t size) { > > + AspeedGPIOState *s = ASPEED_GPIO(opaque); > > + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); > > + uint64_t reg; > > + uint32_t pin; > > + uint32_t type; > > + uint32_t idx; > > + > > + trace_aspeed_gpio_write(offset, data); > > + > > + reg = offset >> 2; > > + > > + if (reg >= agc->reg_table_count) { > > + qemu_log_mask(LOG_GUEST_ERROR, > > + "%s: offset 0x%" PRIx64 " out of bounds\n", > > + __func__, offset); > > + return; > > + } > > + > > + switch (reg) { > > + case R_GPIO_2700_DEBOUNCE_TIME_1 ... > R_GPIO_2700_DEBOUNCE_TIME_3: > > + idx = reg - R_GPIO_2700_DEBOUNCE_TIME_1; > > + > > + if (idx >= ASPEED_GPIO_NR_DEBOUNCE_REGS) { > > + qemu_log_mask(LOG_GUEST_ERROR, > > + "%s: debounce index: %d out of bounds\n", > > + __func__, idx); > > + return; > > + } > > + > > + s->debounce_regs[idx] = (uint32_t) data; > > + break; > > + case R_GPIO_A0_CONTROL ... R_GPIO_AA7_CONTROL: > > + pin = reg - R_GPIO_A0_CONTROL; > > + > > + if (pin >= agc->nr_gpio_pins) { > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid pin > number: %d\n", > > + __func__, pin); > > + return; > > + } > > + > > + if (SHARED_FIELD_EX32(data, GPIO_CONTROL_RESERVED)) { > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid reserved > data: 0x%" > > + PRIx64"\n", __func__, data); > > + return; > > + } > > + > > + aspeed_gpio_write_control_reg(s, pin, type, data); > > + break; > > + default: > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset > 0x%" > > + PRIx64"\n", __func__, offset); > > + break; > > + } > > + > > + return; > > +} > > + > > /****************** Setup functions ******************/ > > Bit of a nitpick, but I'm not personally a fan of banner comments like this. > Did you mean change as following? A. /************ Setup functions *****************/ 1. /* Setup functions */ 2. /* * Setup functions */ Thanks-Jamin > Andrew ^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support 2024-09-24 3:03 ` Jamin Lin @ 2024-09-24 6:48 ` Jamin Lin 2024-09-25 0:00 ` Andrew Jeffery 2024-09-24 23:55 ` Andrew Jeffery 1 sibling, 1 reply; 13+ messages in thread From: Jamin Lin @ 2024-09-24 6:48 UTC (permalink / raw) To: Jamin Lin, Andrew Jeffery, Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee, Joel Stanley, open list:ASPEED BMCs, open list:All patches CC here Cc: Troy Lee, Yunlin Tang Hi Andrew, > Subject: RE: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support > > Hi Andrew, > > > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support > > > > Hi Jamin, > > > > On Mon, 2024-09-23 at 17:42 +0800, Jamin Lin wrote: > > > AST2700 integrates two set of Parallel GPIO Controller with maximum > > > 212 control pins, which are 27 groups. > > > (H, exclude pin: H7 H6 H5 H4) > > > > > > In the previous design of ASPEED SOCs, one register is used for > > > setting one function for one set which are 32 pins and 4 groups. > > > ex: GPIO000 is used for setting data value for GPIO A, B, C and D in > AST2600. > > > ex: GPIO004 is used for setting direction for GPIO A, B, C and D in AST2600. > > > > > > However, the register set have a significant change since AST2700. > > > Each GPIO pin has their own individual control register. In other > > > words, users are able to set one GPIO pin’s direction, interrupt > > > enable, input mask and so on in the same one register. > > > > > > Currently, aspeed_gpio_read/aspeed_gpio_write callback functions are > > > not compatible AST2700. > > > Introduce new aspeed_gpio_2700_read/aspeed_gpio_2700_write callback > > > functions and aspeed_gpio_2700_ops memory region operation for > AST2700. > > > Introduce a new ast2700 class to support AST2700. > > > > > > Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> > > > --- > > > hw/gpio/aspeed_gpio.c | 373 > > > ++++++++++++++++++++++++++++++++++++++++++ > > > 1 file changed, 373 insertions(+) > > > > > > diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index > > > f23ffae34d..e3d5556dc1 100644 > > > --- a/hw/gpio/aspeed_gpio.c > > > +++ b/hw/gpio/aspeed_gpio.c > > > @@ -227,6 +227,38 @@ REG32(GPIO_INDEX_REG, 0x2AC) > > > FIELD(GPIO_INDEX_REG, COMMAND_SRC_1, 21, 1) > > > FIELD(GPIO_INDEX_REG, INPUT_MASK, 20, 1) > > > > > > +/* AST2700 GPIO Register Address Offsets */ > > > +REG32(GPIO_2700_DEBOUNCE_TIME_1, 0x000) > > > +REG32(GPIO_2700_DEBOUNCE_TIME_2, 0x004) > > > +REG32(GPIO_2700_DEBOUNCE_TIME_3, 0x008) > > REG32(GPIO_2700_INT_STATUS_1, > > > +0x100) REG32(GPIO_2700_INT_STATUS_2, 0x104) > > > +REG32(GPIO_2700_INT_STATUS_3, 0x108) > > REG32(GPIO_2700_INT_STATUS_4, > > > +0x10C) REG32(GPIO_2700_INT_STATUS_5, 0x110) > > > +REG32(GPIO_2700_INT_STATUS_6, 0x114) > > REG32(GPIO_2700_INT_STATUS_7, > > > +0x118) > > > +/* GPIOA0 - GPIOAA7 Control Register*/ REG32(GPIO_A0_CONTROL, > > 0x180) > > > + SHARED_FIELD(GPIO_CONTROL_OUT_DATA, 0, 1) > > > + SHARED_FIELD(GPIO_CONTROL_DIRECTION, 1, 1) > > > + SHARED_FIELD(GPIO_CONTROL_INT_ENABLE, 2, 1) > > > + SHARED_FIELD(GPIO_CONTROL_INT_SENS_0, 3, 1) > > > + SHARED_FIELD(GPIO_CONTROL_INT_SENS_1, 4, 1) > > > + SHARED_FIELD(GPIO_CONTROL_INT_SENS_2, 5, 1) > > > + SHARED_FIELD(GPIO_CONTROL_RESET_TOLERANCE, 6, 1) > > > + SHARED_FIELD(GPIO_CONTROL_DEBOUNCE_1, 7, 1) > > > + SHARED_FIELD(GPIO_CONTROL_DEBOUNCE_2, 8, 1) > > > + SHARED_FIELD(GPIO_CONTROL_INPUT_MASK, 9, 1) > > > + SHARED_FIELD(GPIO_CONTROL_BLINK_COUNTER_1, 10, 1) > > > + SHARED_FIELD(GPIO_CONTROL_BLINK_COUNTER_2, 11, 1) > > > + SHARED_FIELD(GPIO_CONTROL_INT_STATUS, 12, 1) > > > + SHARED_FIELD(GPIO_CONTROL_IN_DATA, 13, 1) > > > + SHARED_FIELD(GPIO_CONTROL_RESERVED, 14, 18) > > > +REG32(GPIO_AA7_CONTROL, 0x4DC) #define GPIO_2700_MEM_SIZE > 0x4E0 > > > +#define GPIO_2700_REG_ARRAY_SIZE (GPIO_2700_MEM_SIZE >> 2) > > > + > > > static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, > > > int gpio) { > > > uint32_t falling_edge = 0, rising_edge = 0; @@ -964,6 +996,309 > > > @@ static void aspeed_gpio_set_pin(Object *obj, Visitor *v, const char > *name, > > > aspeed_gpio_set_pin_level(s, set_idx, pin, level); } > > > > > > +static uint64_t aspeed_gpio_read_control_reg(AspeedGPIOState *s, > > > +uint32_t pin) > > > > This function is specific to the AST2700 and I think the name should > > reflect that. > > > Will rename it. > > > > +{ > > > + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); > > > + GPIOSets *set; > > > + uint64_t value = 0; > > > + uint32_t set_idx; > > > + uint32_t pin_idx; > > > + > > > + set_idx = pin / ASPEED_GPIOS_PER_SET; > > > + pin_idx = pin % ASPEED_GPIOS_PER_SET; > > > + > > > + if (set_idx >= agc->nr_gpio_sets) { > > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: set index: %d, out of > > bounds\n", > > > + __func__, set_idx); > > > + return 0; > > > + } > > > + > > > + set = &s->sets[set_idx]; > > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_OUT_DATA, > > > + extract32(set->data_read, pin_idx, > 1)); > > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_DIRECTION, > > > + extract32(set->direction, pin_idx, 1)); > > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_ENABLE, > > > + extract32(set->int_enable, pin_idx, > 1)); > > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_SENS_0, > > > + extract32(set->int_sens_0, pin_idx, > 1)); > > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_SENS_1, > > > + extract32(set->int_sens_1, pin_idx, > 1)); > > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_SENS_2, > > > + extract32(set->int_sens_2, pin_idx, > 1)); > > > + value = SHARED_FIELD_DP32(value, > > GPIO_CONTROL_RESET_TOLERANCE, > > > + extract32(set->reset_tol, pin_idx, 1)); > > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_DEBOUNCE_1, > > > + extract32(set->debounce_1, pin_idx, > > 1)); > > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_DEBOUNCE_2, > > > + extract32(set->debounce_2, pin_idx, > > 1)); > > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INPUT_MASK, > > > + extract32(set->input_mask, pin_idx, > > 1)); > > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_INT_STATUS, > > > + extract32(set->int_status, pin_idx, > 1)); > > > + value = SHARED_FIELD_DP32(value, GPIO_CONTROL_IN_DATA, > > > + extract32(set->data_value, pin_idx, > > 1)); > > > + return value; > > > +} > > > + > > > +static void aspeed_gpio_write_control_reg(AspeedGPIOState *s, > > > > Also should reflect it's specific to the AST2700? > > > Will rename it. > > > + uint32_t pin, uint32_t type, uint64_t data) { > > > + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); > > > + const GPIOSetProperties *props; > > > + GPIOSets *set; > > > + uint32_t cleared; > > > + uint32_t set_idx; > > > + uint32_t pin_idx; > > > + uint32_t group_value = 0; > > > + > > > + set_idx = pin / ASPEED_GPIOS_PER_SET; > > > + pin_idx = pin % ASPEED_GPIOS_PER_SET; > > > + > > > + if (set_idx >= agc->nr_gpio_sets) { > > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: set index: %d, out of > > bounds\n", > > > + __func__, set_idx); > > > + return; > > > + } > > > + > > > + set = &s->sets[set_idx]; > > > + props = &agc->props[set_idx]; > > > + > > > + /* direction */ > > > + group_value = set->direction; > > > + group_value = deposit32(group_value, pin_idx, 1, > > > + SHARED_FIELD_EX32(data, > > GPIO_CONTROL_DIRECTION)); > > > + /* > > > + * where data is the value attempted to be written to the pin: > > > + * pin type | input mask | output mask | expected value > > > + * ------------------------------------------------------------ > > > + * bidirectional | 1 | 1 | data > > > + * input only | 1 | 0 | 0 > > > + * output only | 0 | 1 | 1 > > > + * no pin | 0 | 0 | 0 > > > + * > > > + * which is captured by: > > > + * data = ( data | ~input) & output; > > > + */ > > > + group_value = (group_value | ~props->input) & props->output; > > > + set->direction = update_value_control_source(set, set->direction, > > > + group_value); > > > + > > > + /* out data */ > > > + group_value = set->data_read; > > > + group_value = deposit32(group_value, pin_idx, 1, > > > + SHARED_FIELD_EX32(data, > > GPIO_CONTROL_OUT_DATA)); > > > + group_value &= props->output; > > > + group_value = update_value_control_source(set, set->data_read, > > > + > group_value); > > > + set->data_read = group_value; > > > + > > > + /* interrupt enable */ > > > + group_value = set->int_enable; > > > + group_value = deposit32(group_value, pin_idx, 1, > > > + SHARED_FIELD_EX32(data, > > GPIO_CONTROL_INT_ENABLE)); > > > + set->int_enable = update_value_control_source(set, set->int_enable, > > > + > group_value); > > > + > > > + /* interrupt sensitivity type 0 */ > > > + group_value = set->int_sens_0; > > > + group_value = deposit32(group_value, pin_idx, 1, > > > + SHARED_FIELD_EX32(data, > > GPIO_CONTROL_INT_SENS_0)); > > > + set->int_sens_0 = update_value_control_source(set, set->int_sens_0, > > > + > group_value); > > > + > > > + /* interrupt sensitivity type 1 */ > > > + group_value = set->int_sens_1; > > > + group_value = deposit32(group_value, pin_idx, 1, > > > + SHARED_FIELD_EX32(data, > > GPIO_CONTROL_INT_SENS_1)); > > > + set->int_sens_1 = update_value_control_source(set, set->int_sens_1, > > > + > group_value); > > > + > > > + /* interrupt sensitivity type 2 */ > > > + group_value = set->int_sens_2; > > > + group_value = deposit32(group_value, pin_idx, 1, > > > + SHARED_FIELD_EX32(data, > > GPIO_CONTROL_INT_SENS_2)); > > > + set->int_sens_2 = update_value_control_source(set, set->int_sens_2, > > > + > group_value); > > > + > > > + /* reset tolerance enable */ > > > + group_value = set->reset_tol; > > > + group_value = deposit32(group_value, pin_idx, 1, > > > + SHARED_FIELD_EX32(data, > > GPIO_CONTROL_RESET_TOLERANCE)); > > > + set->reset_tol = update_value_control_source(set, set->reset_tol, > > > + group_value); > > > + > > > + /* debounce 1 */ > > > + group_value = set->debounce_1; > > > + group_value = deposit32(group_value, pin_idx, 1, > > > + SHARED_FIELD_EX32(data, > > GPIO_CONTROL_DEBOUNCE_1)); > > > + set->debounce_1 = update_value_control_source(set, > > set->debounce_1, > > > + > group_value); > > > + > > > + /* debounce 2 */ > > > + group_value = set->debounce_2; > > > + group_value = deposit32(group_value, pin_idx, 1, > > > + SHARED_FIELD_EX32(data, > > GPIO_CONTROL_DEBOUNCE_2)); > > > + set->debounce_2 = update_value_control_source(set, > > set->debounce_2, > > > + > group_value); > > > + > > > + /* input mask */ > > > + group_value = set->input_mask; > > > + group_value = deposit32(group_value, pin_idx, 1, > > > + SHARED_FIELD_EX32(data, > > GPIO_CONTROL_INPUT_MASK)); > > > + /* > > > + * feeds into interrupt generation > > > + * 0: read from data value reg will be updated > > > + * 1: read from data value reg will not be updated > > > + */ > > > + set->input_mask = group_value & props->input; > > > + > > > + /* blink counter 1 */ > > > + /* blink counter 2 */ > > > + /* unimplement */ > > > + > > > + /* interrupt status */ > > > + group_value = set->int_status; > > > + group_value = deposit32(group_value, pin_idx, 1, > > > + SHARED_FIELD_EX32(data, > > > + GPIO_CONTROL_INT_STATUS)); > > > > This makes me a bit wary. > > > > The interrupt status field is W1C, where a set bit on read indicates > > an interrupt is pending. If the bit extracted from data is set it > > should clear the corresponding bit in group_value. However, if the > > extracted bit is clear then the value of the corresponding bit in group_value > should be unchanged. > > > > SHARED_FIELD_EX32() extracts the interrupt status bit from the write (data). > > group_value is set to the set's interrupt status, which means that for > > any pin with an interrupt pending, the corresponding bit is set. The > > deposit32() call updates the bit at pin_idx in the group, using the > > value extracted from the write (data). > > > > However, the result is that if the interrupt was pending and the write > > was acknowledging it, then the update has no effect. Alternatively, if > > the interrupt was pending but the write was acknowledging it, then the > > update will mark the interrupt as pending. Or, if the interrupt was > > pending but the write was _not_ acknowledging it, then the interrupt > > will _no longer_ be marked pending. If this is intentional it feels a bit hard to > follow. > > > > > + cleared = ctpop32(group_value & set->int_status); > > > > Can this rather be expressed as > > > > ``` > > cleared = SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_STATUS); ``` > > > > > + if (s->pending && cleared) { > > > + assert(s->pending >= cleared); > > > + s->pending -= cleared; > > > > We're only ever going to be subtracting 1, as each GPIO has its own register. > > This feels overly abstract. > > > > > + } > > > + set->int_status &= ~group_value; > > > > This feels like it misbehaves in the face of multiple pending interrupts. > > > > For example, say we have an interrupt pending for GPIOA0, where the > > following statements are true: > > > > set->int_status == 0b01 > > s->pending == 1 > > > > Before it is acknowledged, an interrupt becomes pending for GPIOA1: > > > > set->int_status == 0b11 > > s->pending == 2 > > > > A write is issued to acknowledge the interrupt for GPIOA0. This causes > > the following sequence: > > > > group_value == 0b11 > > cleared == 2 > > s->pending = 0 > > set->int_status == 0b00 > > > > It seems the pending interrupt for GPIOA1 is lost? > > > Thanks for review and input. > I should check "int_status" bit of write data in write callback function. If 1 clear > status flag(group value), else should not change group value. > I am checking and testing this issue and will update to you or directly resend > the new patch series. I appreciate your review and finding this issue. My changes as following. If you agree, I will add them in v2 patch. Thanks-Jamin static void aspeed_gpio_2700_write_control_reg(AspeedGPIOState *s, uint32_t pin, uint32_t type, uint64_t data) { --- /* interrupt status */ if (SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_STATUS)) { cleared = extract32(set->int_status, pin_idx, 1); if (cleared) { if (s->pending) { assert(s->pending >= cleared); s->pending -= cleared; } set->int_status = deposit32(set->int_status, pin_idx, 1, 0); } } ---- } By the way, I found the same issue in "aspeed_gpio_write_index_mode" and my changes as following. If you agree this change, I will create a new patch in v2 patch series. static void aspeed_gpio_write_index_mode(void *opaque, hwaddr offset, uint64_t data, uint32_t size) { --- case gpio_reg_idx_interrupt: if (FIELD_EX32(data, GPIO_INDEX_REG, INT_STATUS)) { cleared = extract32(set->int_status, pin_idx, 1); if (cleared) { if (s->pending) { assert(s->pending >= cleared); s->pending -= cleared; } set->int_status = deposit32(set->int_status, pin_idx, 1, 0); } } break; --- } Thanks-Jamin > > > + > > > + aspeed_gpio_update(s, set, set->data_value, UINT32_MAX); > > > + return; > > > +} > > > + > > > +static uint64_t aspeed_gpio_2700_read(void *opaque, hwaddr offset, > > > + uint32_t size) { > > > + AspeedGPIOState *s = ASPEED_GPIO(opaque); > > > + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); > > > + GPIOSets *set; > > > + uint64_t value; > > > + uint64_t reg; > > > + uint32_t pin; > > > + uint32_t idx; > > > + > > > + reg = offset >> 2; > > > + > > > + if (reg >= agc->reg_table_count) { > > > + qemu_log_mask(LOG_GUEST_ERROR, > > > + "%s: offset 0x%" PRIx64 " out of bounds\n", > > > + __func__, offset); > > > + return 0; > > > + } > > > + > > > + switch (reg) { > > > + case R_GPIO_2700_DEBOUNCE_TIME_1 ... > > R_GPIO_2700_DEBOUNCE_TIME_3: > > > + idx = reg - R_GPIO_2700_DEBOUNCE_TIME_1; > > > + > > > + if (idx >= ASPEED_GPIO_NR_DEBOUNCE_REGS) { > > > + qemu_log_mask(LOG_GUEST_ERROR, > > > + "%s: debounce index: %d, out of > bounds\n", > > > + __func__, idx); > > > + return 0; > > > + } > > > + > > > + value = (uint64_t) s->debounce_regs[idx]; > > > + break; > > > + case R_GPIO_2700_INT_STATUS_1 ... R_GPIO_2700_INT_STATUS_7: > > > + idx = reg - R_GPIO_2700_INT_STATUS_1; > > > + > > > + if (idx >= agc->nr_gpio_sets) { > > > + qemu_log_mask(LOG_GUEST_ERROR, > > > + "%s: interrupt status index: %d, out of > > bounds\n", > > > + __func__, idx); > > > + return 0; > > > + } > > > + > > > + set = &s->sets[idx]; > > > + value = (uint64_t) set->int_status; > > > + break; > > > + case R_GPIO_A0_CONTROL ... R_GPIO_AA7_CONTROL: > > > + pin = reg - R_GPIO_A0_CONTROL; > > > + > > > + if (pin >= agc->nr_gpio_pins) { > > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid pin > > number: %d\n", > > > + __func__, pin); > > > + return 0; > > > + } > > > + > > > + value = aspeed_gpio_read_control_reg(s, pin); > > > + break; > > > + default: > > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset > > 0x%" > > > + PRIx64"\n", __func__, offset); > > > + return 0; > > > + } > > > + > > > + trace_aspeed_gpio_read(offset, value); > > > + return value; > > > +} > > > + > > > +static void aspeed_gpio_2700_write(void *opaque, hwaddr offset, > > > + uint64_t data, uint32_t size) { > > > + AspeedGPIOState *s = ASPEED_GPIO(opaque); > > > + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); > > > + uint64_t reg; > > > + uint32_t pin; > > > + uint32_t type; > > > + uint32_t idx; > > > + > > > + trace_aspeed_gpio_write(offset, data); > > > + > > > + reg = offset >> 2; > > > + > > > + if (reg >= agc->reg_table_count) { > > > + qemu_log_mask(LOG_GUEST_ERROR, > > > + "%s: offset 0x%" PRIx64 " out of bounds\n", > > > + __func__, offset); > > > + return; > > > + } > > > + > > > + switch (reg) { > > > + case R_GPIO_2700_DEBOUNCE_TIME_1 ... > > R_GPIO_2700_DEBOUNCE_TIME_3: > > > + idx = reg - R_GPIO_2700_DEBOUNCE_TIME_1; > > > + > > > + if (idx >= ASPEED_GPIO_NR_DEBOUNCE_REGS) { > > > + qemu_log_mask(LOG_GUEST_ERROR, > > > + "%s: debounce index: %d out of > bounds\n", > > > + __func__, idx); > > > + return; > > > + } > > > + > > > + s->debounce_regs[idx] = (uint32_t) data; > > > + break; > > > + case R_GPIO_A0_CONTROL ... R_GPIO_AA7_CONTROL: > > > + pin = reg - R_GPIO_A0_CONTROL; > > > + > > > + if (pin >= agc->nr_gpio_pins) { > > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid pin > > number: %d\n", > > > + __func__, pin); > > > + return; > > > + } > > > + > > > + if (SHARED_FIELD_EX32(data, GPIO_CONTROL_RESERVED)) { > > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid > reserved > > data: 0x%" > > > + PRIx64"\n", __func__, data); > > > + return; > > > + } > > > + > > > + aspeed_gpio_write_control_reg(s, pin, type, data); > > > + break; > > > + default: > > > + qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset > > 0x%" > > > + PRIx64"\n", __func__, offset); > > > + break; > > > + } > > > + > > > + return; > > > +} > > > + > > > /****************** Setup functions ******************/ > > > > Bit of a nitpick, but I'm not personally a fan of banner comments like this. > > > Did you mean change as following? > > A. > > /************ Setup functions *****************/ > > 1. /* Setup functions */ > 2. /* > * Setup functions > */ > > Thanks-Jamin > > > Andrew ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support 2024-09-24 6:48 ` Jamin Lin @ 2024-09-25 0:00 ` Andrew Jeffery 2024-09-25 2:54 ` Jamin Lin 0 siblings, 1 reply; 13+ messages in thread From: Andrew Jeffery @ 2024-09-25 0:00 UTC (permalink / raw) To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee, Joel Stanley, open list:ASPEED BMCs, open list:All patches CC here Cc: Troy Lee, Yunlin Tang On Tue, 2024-09-24 at 06:48 +0000, Jamin Lin wrote: > Hi Andrew, > > > Subject: RE: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support > > > > Hi Andrew, > > > > > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support > > > > > > Hi Jamin, > > > > > > > > > > + } > > > > + set->int_status &= ~group_value; > > > > > > This feels like it misbehaves in the face of multiple pending interrupts. > > > > > > For example, say we have an interrupt pending for GPIOA0, where the > > > following statements are true: > > > > > > set->int_status == 0b01 > > > s->pending == 1 > > > > > > Before it is acknowledged, an interrupt becomes pending for GPIOA1: > > > > > > set->int_status == 0b11 > > > s->pending == 2 > > > > > > A write is issued to acknowledge the interrupt for GPIOA0. This causes > > > the following sequence: > > > > > > group_value == 0b11 > > > cleared == 2 > > > s->pending = 0 > > > set->int_status == 0b00 > > > > > > It seems the pending interrupt for GPIOA1 is lost? > > > > > Thanks for review and input. > > I should check "int_status" bit of write data in write callback function. If 1 clear > > status flag(group value), else should not change group value. > > I am checking and testing this issue and will update to you or directly resend > > the new patch series. > > I appreciate your review and finding this issue. > My changes as following. > If you agree, I will add them in v2 patch. > Thanks-Jamin > > static void aspeed_gpio_2700_write_control_reg(AspeedGPIOState *s, > uint32_t pin, uint32_t type, uint64_t data) > { > --- > /* interrupt status */ > if (SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_STATUS)) { > cleared = extract32(set->int_status, pin_idx, 1); > if (cleared) { > if (s->pending) { > assert(s->pending >= cleared); > s->pending -= cleared; > } > set->int_status = deposit32(set->int_status, pin_idx, 1, 0); > } > } > ---- > } The logic is easier to follow. Not sure about calling the value extracted from set->int_status 'cleared' though, seems confusing on first pass. It would feel more appropriate if it were called 'pending'. I think 'cleared' is derived from `SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_STATUS)`. Anyway, that's just some quibbling over names. > > By the way, I found the same issue in "aspeed_gpio_write_index_mode" and my changes as following. > If you agree this change, I will create a new patch in v2 patch series. > > static void aspeed_gpio_write_index_mode(void *opaque, hwaddr offset, > uint64_t data, uint32_t size) > { > --- > case gpio_reg_idx_interrupt: > if (FIELD_EX32(data, GPIO_INDEX_REG, INT_STATUS)) { > cleared = extract32(set->int_status, pin_idx, 1); > if (cleared) { > if (s->pending) { > assert(s->pending >= cleared); > s->pending -= cleared; > } > set->int_status = deposit32(set->int_status, pin_idx, 1, 0); > } > } > break; > --- > } I'll take a look in v2. Cheers, Andrew ^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support 2024-09-25 0:00 ` Andrew Jeffery @ 2024-09-25 2:54 ` Jamin Lin 0 siblings, 0 replies; 13+ messages in thread From: Jamin Lin @ 2024-09-25 2:54 UTC (permalink / raw) To: Andrew Jeffery, Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee, Joel Stanley, open list:ASPEED BMCs, open list:All patches CC here Cc: Troy Lee, Yunlin Tang Hi Andrew, > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support > > On Tue, 2024-09-24 at 06:48 +0000, Jamin Lin wrote: > > Hi Andrew, > > > > > Subject: RE: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support > > > > > > Hi Andrew, > > > > > > > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support > > > > > > > > Hi Jamin, > > > > > > > > > > > > > + } > > > > > + set->int_status &= ~group_value; > > > > > > > > This feels like it misbehaves in the face of multiple pending interrupts. > > > > > > > > For example, say we have an interrupt pending for GPIOA0, where > > > > the following statements are true: > > > > > > > > set->int_status == 0b01 > > > > s->pending == 1 > > > > > > > > Before it is acknowledged, an interrupt becomes pending for GPIOA1: > > > > > > > > set->int_status == 0b11 > > > > s->pending == 2 > > > > > > > > A write is issued to acknowledge the interrupt for GPIOA0. This > > > > causes the following sequence: > > > > > > > > group_value == 0b11 > > > > cleared == 2 > > > > s->pending = 0 > > > > set->int_status == 0b00 > > > > > > > > It seems the pending interrupt for GPIOA1 is lost? > > > > > > > Thanks for review and input. > > > I should check "int_status" bit of write data in write callback > > > function. If 1 clear status flag(group value), else should not change group > value. > > > I am checking and testing this issue and will update to you or > > > directly resend the new patch series. > > > > I appreciate your review and finding this issue. > > My changes as following. > > If you agree, I will add them in v2 patch. > > Thanks-Jamin > > > > static void aspeed_gpio_2700_write_control_reg(AspeedGPIOState *s, > > uint32_t pin, uint32_t type, uint64_t > > data) { > > --- > > /* interrupt status */ > > if (SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_STATUS)) { > > cleared = extract32(set->int_status, pin_idx, 1); > > if (cleared) { > > if (s->pending) { > > assert(s->pending >= cleared); > > s->pending -= cleared; > > } > > set->int_status = deposit32(set->int_status, pin_idx, 1, 0); > > } > > } > > ---- > > } > > The logic is easier to follow. Not sure about calling the value extracted from > set->int_status 'cleared' though, seems confusing on first pass. It would feel > more appropriate if it were called 'pending'. > I think 'cleared' is derived from `SHARED_FIELD_EX32(data, > GPIO_CONTROL_INT_STATUS)`. Anyway, that's just some quibbling over > names. Got it. Will update it. Thanks for suggestion and review. > > > > > By the way, I found the same issue in "aspeed_gpio_write_index_mode" and > my changes as following. > > If you agree this change, I will create a new patch in v2 patch series. > > > > static void aspeed_gpio_write_index_mode(void *opaque, hwaddr offset, > > uint64_t data, > > uint32_t size) { > > --- > > case gpio_reg_idx_interrupt: > > if (FIELD_EX32(data, GPIO_INDEX_REG, INT_STATUS)) { > > cleared = extract32(set->int_status, pin_idx, 1); > > if (cleared) { > > if (s->pending) { > > assert(s->pending >= cleared); > > s->pending -= cleared; > > } > > set->int_status = deposit32(set->int_status, pin_idx, 1, > 0); > > } > > } > > break; > > --- > > } > > I'll take a look in v2. > > Cheers, > > Andrew ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support 2024-09-24 3:03 ` Jamin Lin 2024-09-24 6:48 ` Jamin Lin @ 2024-09-24 23:55 ` Andrew Jeffery 2024-09-25 2:55 ` Jamin Lin 1 sibling, 1 reply; 13+ messages in thread From: Andrew Jeffery @ 2024-09-24 23:55 UTC (permalink / raw) To: Jamin Lin, Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee, Joel Stanley, open list:ASPEED BMCs, open list:All patches CC here Cc: Troy Lee, Yunlin Tang On Tue, 2024-09-24 at 03:03 +0000, Jamin Lin wrote: > Hi Andrew, > > > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support > > > > Hi Jamin, > > > > On Mon, 2024-09-23 at 17:42 +0800, Jamin Lin wrote: > > > > > + > > > + /* interrupt status */ > > > + group_value = set->int_status; > > > + group_value = deposit32(group_value, pin_idx, 1, > > > + SHARED_FIELD_EX32(data, > > > + GPIO_CONTROL_INT_STATUS)); > > > > This makes me a bit wary. > > > > The interrupt status field is W1C, where a set bit on read indicates an interrupt > > is pending. If the bit extracted from data is set it should clear the > > corresponding bit in group_value. However, if the extracted bit is clear then > > the value of the corresponding bit in group_value should be unchanged. > > > > SHARED_FIELD_EX32() extracts the interrupt status bit from the write (data). > > group_value is set to the set's interrupt status, which means that for any pin > > with an interrupt pending, the corresponding bit is set. The deposit32() call > > updates the bit at pin_idx in the group, using the value extracted from the > > write (data). > > > > However, the result is that if the interrupt was pending and the write was > > acknowledging it, then the update has no effect. Alternatively, if the interrupt > > was pending but the write was acknowledging it, then the update will mark the > > interrupt as pending. Or, if the interrupt was pending but the write was _not_ > > acknowledging it, then the interrupt will _no longer_ be marked pending. If > > this is intentional it feels a bit hard to follow. > > > > > + cleared = ctpop32(group_value & set->int_status); > > > > Can this rather be expressed as > > > > ``` > > cleared = SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_STATUS); ``` > > > > > + if (s->pending && cleared) { > > > + assert(s->pending >= cleared); > > > + s->pending -= cleared; > > > > We're only ever going to be subtracting 1, as each GPIO has its own register. > > This feels overly abstract. > > > > > + } > > > + set->int_status &= ~group_value; > > > > This feels like it misbehaves in the face of multiple pending interrupts. > > > > For example, say we have an interrupt pending for GPIOA0, where the > > following statements are true: > > > > set->int_status == 0b01 > > s->pending == 1 > > > > Before it is acknowledged, an interrupt becomes pending for GPIOA1: > > > > set->int_status == 0b11 > > s->pending == 2 > > > > A write is issued to acknowledge the interrupt for GPIOA0. This causes the > > following sequence: > > > > group_value == 0b11 > > cleared == 2 > > s->pending = 0 > > set->int_status == 0b00 > > > > It seems the pending interrupt for GPIOA1 is lost? > > > Thanks for review and input. > I should check "int_status" bit of write data in write callback function. If 1 clear status flag(group value), else should not change group value. > I am checking and testing this issue and will update to you or directly resend the new patch series. Happy to take a look in a v2 of the series :) > > > + > > > /****************** Setup functions ******************/ > > > > Bit of a nitpick, but I'm not personally a fan of banner comments like this. > > > Did you mean change as following? > > A. > > /************ Setup functions *****************/ > > 1. /* Setup functions */ > 2. /* > * Setup functions > */ Either is fine, but I prefer 1. Cheers, Andrew ^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support 2024-09-24 23:55 ` Andrew Jeffery @ 2024-09-25 2:55 ` Jamin Lin 0 siblings, 0 replies; 13+ messages in thread From: Jamin Lin @ 2024-09-25 2:55 UTC (permalink / raw) To: Andrew Jeffery, Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee, Joel Stanley, open list:ASPEED BMCs, open list:All patches CC here Cc: Troy Lee, Yunlin Tang Hi Andrew, > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support > > On Tue, 2024-09-24 at 03:03 +0000, Jamin Lin wrote: > > Hi Andrew, > > > > > Subject: Re: [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support > > > > > > Hi Jamin, > > > > > > On Mon, 2024-09-23 at 17:42 +0800, Jamin Lin wrote: > > > > > > > + > > > > + /* interrupt status */ > > > > + group_value = set->int_status; > > > > + group_value = deposit32(group_value, pin_idx, 1, > > > > + SHARED_FIELD_EX32(data, > > > > + GPIO_CONTROL_INT_STATUS)); > > > > > > This makes me a bit wary. > > > > > > The interrupt status field is W1C, where a set bit on read indicates > > > an interrupt is pending. If the bit extracted from data is set it > > > should clear the corresponding bit in group_value. However, if the > > > extracted bit is clear then the value of the corresponding bit in group_value > should be unchanged. > > > > > > SHARED_FIELD_EX32() extracts the interrupt status bit from the write > (data). > > > group_value is set to the set's interrupt status, which means that > > > for any pin with an interrupt pending, the corresponding bit is set. > > > The deposit32() call updates the bit at pin_idx in the group, using > > > the value extracted from the write (data). > > > > > > However, the result is that if the interrupt was pending and the > > > write was acknowledging it, then the update has no effect. > > > Alternatively, if the interrupt was pending but the write was > > > acknowledging it, then the update will mark the interrupt as > > > pending. Or, if the interrupt was pending but the write was _not_ > > > acknowledging it, then the interrupt will _no longer_ be marked pending. If > this is intentional it feels a bit hard to follow. > > > > > > > + cleared = ctpop32(group_value & set->int_status); > > > > > > Can this rather be expressed as > > > > > > ``` > > > cleared = SHARED_FIELD_EX32(data, GPIO_CONTROL_INT_STATUS); ``` > > > > > > > + if (s->pending && cleared) { > > > > + assert(s->pending >= cleared); > > > > + s->pending -= cleared; > > > > > > We're only ever going to be subtracting 1, as each GPIO has its own > register. > > > This feels overly abstract. > > > > > > > + } > > > > + set->int_status &= ~group_value; > > > > > > This feels like it misbehaves in the face of multiple pending interrupts. > > > > > > For example, say we have an interrupt pending for GPIOA0, where the > > > following statements are true: > > > > > > set->int_status == 0b01 > > > s->pending == 1 > > > > > > Before it is acknowledged, an interrupt becomes pending for GPIOA1: > > > > > > set->int_status == 0b11 > > > s->pending == 2 > > > > > > A write is issued to acknowledge the interrupt for GPIOA0. This > > > causes the following sequence: > > > > > > group_value == 0b11 > > > cleared == 2 > > > s->pending = 0 > > > set->int_status == 0b00 > > > > > > It seems the pending interrupt for GPIOA1 is lost? > > > > > Thanks for review and input. > > I should check "int_status" bit of write data in write callback function. If 1 > clear status flag(group value), else should not change group value. > > I am checking and testing this issue and will update to you or directly resend > the new patch series. > > Happy to take a look in a v2 of the series :) > > > > > + > > > > /****************** Setup functions ******************/ > > > > > > Bit of a nitpick, but I'm not personally a fan of banner comments like this. > > > > > Did you mean change as following? > > > > A. > > > > /************ Setup functions *****************/ > > > > 1. /* Setup functions */ > > 2. /* > > * Setup functions > > */ > > Either is fine, but I prefer 1. > Thanks for suggestion. Will update it in V2 Thanks-Jamin > Cheers, > > Andrew ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 5/5] aspeed/soc: Support GPIO for AST2700 2024-09-23 9:42 [PATCH 0/5] Support GPIO for AST2700 Jamin Lin via ` (3 preceding siblings ...) 2024-09-23 9:42 ` [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support Jamin Lin via @ 2024-09-23 9:42 ` Jamin Lin via 4 siblings, 0 replies; 13+ messages in thread From: Jamin Lin via @ 2024-09-23 9:42 UTC (permalink / raw) To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery, Joel Stanley, open list:ASPEED BMCs, open list:All patches CC here Cc: jamin_lin, troy_lee, yunlin.tang Add GPIO model for AST2700 GPIO support. The GPIO controller registers base address is start at 0x14C0_B000 and its address space is 0x1000. The AST2700 GPIO controller interrupt is connected to GICINT130_INTC at bit 18. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> --- hw/arm/aspeed_ast27x0.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index 761ee11657..dca660eb6b 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -62,6 +62,7 @@ static const hwaddr aspeed_soc_ast2700_memmap[] = { [ASPEED_GIC_REDIST] = 0x12280000, [ASPEED_DEV_ADC] = 0x14C00000, [ASPEED_DEV_I2C] = 0x14C0F000, + [ASPEED_DEV_GPIO] = 0x14C0B000, }; #define AST2700_MAX_IRQ 288 @@ -87,8 +88,7 @@ static const int aspeed_soc_ast2700_irqmap[] = { [ASPEED_DEV_ADC] = 130, [ASPEED_DEV_XDMA] = 5, [ASPEED_DEV_EMMC] = 15, - [ASPEED_DEV_GPIO] = 11, - [ASPEED_DEV_GPIO_1_8V] = 130, + [ASPEED_DEV_GPIO] = 130, [ASPEED_DEV_RTC] = 13, [ASPEED_DEV_TIMER1] = 16, [ASPEED_DEV_TIMER2] = 17, @@ -124,7 +124,7 @@ static const int aspeed_soc_ast2700_gic128_intcmap[] = { static const int aspeed_soc_ast2700_gic130_intcmap[] = { [ASPEED_DEV_I2C] = 0, [ASPEED_DEV_ADC] = 16, - [ASPEED_DEV_GPIO_1_8V] = 18, + [ASPEED_DEV_GPIO] = 18, }; /* GICINT 131 */ @@ -373,6 +373,9 @@ static void aspeed_soc_ast2700_init(Object *obj) snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); object_initialize_child(obj, "i2c", &s->i2c, typename); + + snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); + object_initialize_child(obj, "gpio", &s->gpio, typename); } /* @@ -658,6 +661,15 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); } + /* GPIO */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { + return; + } + aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, + sc->memmap[ASPEED_DEV_GPIO]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, + aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); + create_unimplemented_device("ast2700.dpmcu", 0x11000000, 0x40000); create_unimplemented_device("ast2700.iomem0", 0x12000000, 0x01000000); create_unimplemented_device("ast2700.iomem1", 0x14000000, 0x01000000); -- 2.34.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
end of thread, other threads:[~2024-09-25 2:56 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-09-23 9:42 [PATCH 0/5] Support GPIO for AST2700 Jamin Lin via 2024-09-23 9:42 ` [PATCH 1/5] hw/gpio/aspeed: Fix coding style Jamin Lin via 2024-09-23 9:42 ` [PATCH 2/5] hw/gpio/aspeed: Support to set the different memory size Jamin Lin via 2024-09-23 9:42 ` [PATCH 3/5] hw/gpio/aspeed: Support different memory region ops Jamin Lin via 2024-09-23 9:42 ` [PATCH 4/5] hw/gpio/aspeed: Add AST2700 support Jamin Lin via 2024-09-24 1:11 ` Andrew Jeffery 2024-09-24 3:03 ` Jamin Lin 2024-09-24 6:48 ` Jamin Lin 2024-09-25 0:00 ` Andrew Jeffery 2024-09-25 2:54 ` Jamin Lin 2024-09-24 23:55 ` Andrew Jeffery 2024-09-25 2:55 ` Jamin Lin 2024-09-23 9:42 ` [PATCH 5/5] aspeed/soc: Support GPIO for AST2700 Jamin Lin via
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