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From: Richard Henderson <richard.henderson@linaro.org>
To: "Catherine A. Frederick" <agrecascino123@gmail.com>,
	qemu-devel@nongnu.org
Subject: Re: [RFC] Various questions about TCG implementation, DRM patches dealing with pointers over guest-host barrier.
Date: Tue, 19 May 2020 07:51:55 -0700	[thread overview]
Message-ID: <8573dda3-a4f4-2590-678d-d45cfb62ced6@linaro.org> (raw)
In-Reply-To: <9d75f1f6-3440-8dec-9266-4841362844d0@gmail.com>

On 5/17/20 4:05 PM, Catherine A. Frederick wrote:
> - I've been implementing an instruction scheduler(list scheduler, with priority
> given to most successors) for TCG and currently if I replace instructions in
> s->ops(the TCG context) I get a crash later in tcg_reg_alloc_op, even if the
> instruction stream is identical. Is there anything else I need to move when I
> do this?

If you're getting a crash in tcg_reg_alloc_op, are you updating liveness info?
 Where are you inserting your scheduler in the list of passes?

> - Is insn_start necessary to have in order(and what does it do?)? These
> currently are serializing instructions in my scheduler and significantly limit
> my reordering as they create lots of dependencies every few instructions.

insn_start is required for unwinding from exceptions.  You can consider it a
barrier for call and qemu_ld/st.  Anything else cannot raise an exception and
can be moved.


r~


      parent reply	other threads:[~2020-05-19 14:56 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-17 23:05 [RFC] Various questions about TCG implementation, DRM patches dealing with pointers over guest-host barrier Catherine A. Frederick
2020-05-18 10:21 ` Peter Maydell
2020-05-18 10:52   ` Alex Bennée
2020-05-19 14:51 ` Richard Henderson [this message]

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