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[74.87.59.235]) by smtp.gmail.com with ESMTPSA id y5-20020a17090a134500b0023317104415sm1413037pjf.17.2023.02.10.11.49.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 10 Feb 2023 11:49:29 -0800 (PST) Message-ID: <858e9f86-672c-9be3-1826-0267b43969b1@linaro.org> Date: Fri, 10 Feb 2023 09:49:13 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH 12/22] target/arm: NSTable is RES0 for the RME EL3 regime To: Peter Maydell Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, yier.jin@huawei.com, jonathan.cameron@huawei.com, leonardo.garcia@linaro.org References: <20230124000027.3565716-1-richard.henderson@linaro.org> <20230124000027.3565716-13-richard.henderson@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.149, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/10/23 01:36, Peter Maydell wrote: > On Tue, 24 Jan 2023 at 00:01, Richard Henderson > wrote: >> >> Test in_space instead of in_secure so that we don't switch >> out of Root space. Handle the output space change immediately, >> rather than try and combine the NSTable and NS bits later. >> >> Signed-off-by: Richard Henderson >> --- >> target/arm/ptw.c | 31 ++++++++++++++----------------- >> 1 file changed, 14 insertions(+), 17 deletions(-) >> >> diff --git a/target/arm/ptw.c b/target/arm/ptw.c >> index c1b0b8e610..ddafb1f329 100644 >> --- a/target/arm/ptw.c >> +++ b/target/arm/ptw.c >> @@ -1240,7 +1240,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, >> { >> ARMCPU *cpu = env_archcpu(env); >> ARMMMUIdx mmu_idx = ptw->in_mmu_idx; >> - bool is_secure = ptw->in_secure; >> int32_t level; >> ARMVAParameters param; >> uint64_t ttbr; >> @@ -1256,7 +1255,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, >> uint64_t descaddrmask; >> bool aarch64 = arm_el_is_aa64(env, el); >> uint64_t descriptor, new_descriptor; >> - bool nstable; >> >> /* TODO: This code does not support shareability levels. */ >> if (aarch64) { >> @@ -1417,29 +1415,29 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, >> descaddrmask = MAKE_64BIT_MASK(0, 40); >> } >> descaddrmask &= ~indexmask_grainsize; >> - >> - /* >> - * Secure accesses start with the page table in secure memory and >> - * can be downgraded to non-secure at any step. Non-secure accesses >> - * remain non-secure. We implement this by just ORing in the NSTable/NS >> - * bits at each step. >> - */ >> - tableattrs = is_secure ? 0 : (1 << 4); >> + tableattrs = 0; >> >> next_level: >> descaddr |= (address >> (stride * (4 - level))) & indexmask; >> descaddr &= ~7ULL; >> - nstable = extract32(tableattrs, 4, 1); >> - if (nstable && ptw->in_secure) { >> - /* >> - * Stage2_S -> Stage2 or Phys_S -> Phys_NS >> - * Assert that the non-secure idx are even, and relative order. >> - */ >> + >> + /* >> + * Process the NSTable bit from the previous level. This changes >> + * the table address space and the output space from Secure to >> + * NonSecure. With RME, the EL3 translation regime does not change >> + * from Root to NonSecure. >> + */ > > To check my understanding, this means that the bit that the spec > describes as FEAT_RME changing the behaviour of NSTable in the EL3 > stage 1 translation regime is implemented by us by having the > in_space for EL3 be different for FEAT_RME and not-FEAT_RME ? Correct -- space is Secure for non-RME EL3, and Root for RME EL3. >> attrs = new_descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(50, 14)); >> if (!regime_is_stage2(mmu_idx)) { >> - attrs |= nstable << 5; /* NS */ > > This removes the code where we copy the NSTable bit across to attrs, > but there's still code below here that assumes it can get the combined > NS bit from bit 5 of attrs, isn't there? (It passes it to get_S1prot().) Oops. This gets fixed in patch 14. Some reordering needed... r~