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Content-Language: en-US To: Helge Deller , qemu-devel@nongnu.org References: <20220131213529.17404-1-deller@gmx.de> <20220131213529.17404-4-deller@gmx.de> From: Richard Henderson In-Reply-To: <20220131213529.17404-4-deller@gmx.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::435 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sven Schnelle Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/1/22 08:35, Helge Deller wrote: > Almost all PA-RISC machines have either a button that is labeled with 'TOC' or > a BMC/GSP function to trigger a TOC. TOC is a non-maskable interrupt that is > sent to the processor. This can be used for diagnostic purposes like obtaining > a stack trace/register dump or to enter KDB/KGDB in Linux. > > This patch adds support for such an emulated TOC button. > > It wires up the qemu monitor "nmi" command to trigger a TOC. For that it > provides the hppa_nmi function which is assigned to the nmi_monitor_handler > function pointer. When called it raises the EXCP_TOC hardware interrupt in the > hppa_cpu_do_interrupt() function. The interrupt function then calls the > architecturally defined TOC function in SeaBIOS-hppa firmware (at fixed address > 0xf0000000). > > According to the PA-RISC PDC specification, the SeaBIOS firmware then writes > the CPU registers into PIM (processor internal memmory) for later analysis. In > order to write all registers it needs to know the contents of the CPU "shadow > registers" and the IASQ- and IAOQ-back values. The IAOQ/IASQ values are > provided by qemu in shadow registers when entering the SeaBIOS TOC function. > This patch adds a new aritificial opcode "getshadowregs" (0xfffdead2) which > restores the original values of the shadow registers. With this opcode SeaBIOS > can store those registers as well into PIM before calling an OS-provided TOC > handler. > > To trigger a TOC, switch to the qemu monitor with Ctrl-A C, and type in the > command "nmi". After the TOC started the OS-debugger, exit the qemu monitor > with Ctrl-A C. > > Signed-off-by: Helge Deller > --- > hw/hppa/machine.c | 35 ++++++++++++++++++++++++++++++++++- > target/hppa/cpu.c | 2 +- > target/hppa/cpu.h | 5 +++++ > target/hppa/helper.h | 1 + > target/hppa/insns.decode | 1 + > target/hppa/int_helper.c | 19 ++++++++++++++++++- > target/hppa/op_helper.c | 7 ++++++- > target/hppa/translate.c | 10 ++++++++++ > 8 files changed, 76 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson r~