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From: Marc Zyngier <maz@kernel.org>
To: Alex Williamson <alex.williamson@redhat.com>
Cc: chenxiang <chenxiang66@hisilicon.com>, <kvm@vger.kernel.org>,
	<qemu-devel@nongnu.org>, <linuxarm@huawei.com>
Subject: Re: [PATCH v2] vfio/pci: Verify each MSI vector to avoid invalid MSI vectors
Date: Thu, 24 Nov 2022 13:19:22 +0000	[thread overview]
Message-ID: <861qpso5gl.wl-maz@kernel.org> (raw)
In-Reply-To: <20221123125514.5bf83fa8.alex.williamson@redhat.com>

On Wed, 23 Nov 2022 19:55:14 +0000,
Alex Williamson <alex.williamson@redhat.com> wrote:
> 
> On Wed, 23 Nov 2022 12:08:05 +0000
> Marc Zyngier <maz@kernel.org> wrote:
> 
> > On Wed, 23 Nov 2022 01:42:36 +0000,
> > chenxiang <chenxiang66@hisilicon.com> wrote:
> > > 
> > > +static int vfio_pci_verify_msi_entry(struct vfio_pci_core_device *vdev,
> > > +		struct eventfd_ctx *trigger)
> > > +{
> > > +	struct kvm *kvm = vdev->vdev.kvm;
> > > +	struct kvm_kernel_irqfd *tmp;
> > > +	struct kvm_kernel_irq_routing_entry irq_entry;
> > > +	int ret = -ENODEV;
> > > +
> > > +	spin_lock_irq(&kvm->irqfds.lock);
> > > +	list_for_each_entry(tmp, &kvm->irqfds.items, list) {
> > > +		if (trigger == tmp->eventfd) {
> > > +			ret = 0;
> > > +			break;
> > > +		}
> > > +	}
> > > +	spin_unlock_irq(&kvm->irqfds.lock);
> > > +	if (ret)
> > > +		return ret;
> > > +	irq_entry = tmp->irq_entry;
> > > +	return kvm_verify_msi(kvm, &irq_entry);  
> > 
> > How does this work on !arm64? Why do we need an on-stack version of
> > tmp->irq_entry?
> 
> Not only on !arm64, but in any scenario that doesn't involve KVM.
> There cannot be a hard dependency between vfio and kvm.  Thanks,

Yup, good point.

> 
> Alex
> 
> PS - What driver/device actually cares about more than 1 MSI vector and
> doesn't implement MSI-X?

Unfortunately, there is a metric ton of crap that fits in that
description:

01:00.0 Network controller: Broadcom Inc. and subsidiaries Device 4433 (rev 07)
	Subsystem: Apple Inc. Device 4387
	Device tree node: /sys/firmware/devicetree/base/soc/pcie@690000000/pci@0,0/wifi@0,0
	Flags: bus master, fast devsel, latency 0, IRQ 97, IOMMU group 4
	Memory at 6c1400000 (64-bit, non-prefetchable) [size=64K]
	Memory at 6c0000000 (64-bit, non-prefetchable) [size=16M]
	Capabilities: [48] Power Management version 3
	Capabilities: [58] MSI: Enable+ Count=1/32 Maskable- 64bit+

... and no MSI-X in sight. Pass this to a VM, and you'll see exactly
what is described here. And that's not old stuff either. This is brand
new HW.

Do we need to care? I don't think so.

	M.

-- 
Without deviation from the norm, progress is not possible.


  reply	other threads:[~2022-11-24 13:20 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-23  1:42 [PATCH v2] vfio/pci: Verify each MSI vector to avoid invalid MSI vectors chenxiang via
2022-11-23 12:08 ` Marc Zyngier
2022-11-23 19:55   ` Alex Williamson
2022-11-24 13:19     ` Marc Zyngier [this message]
2022-11-26  6:33   ` chenxiang (M) via
2022-11-26 10:58     ` Marc Zyngier
2022-11-24 18:00 ` Jason Gunthorpe
2022-11-26 11:15   ` Marc Zyngier
2022-11-28 18:01     ` Jason Gunthorpe
2022-11-26  1:21 ` kernel test robot
2022-11-26  3:12 ` kernel test robot
2022-11-26  3:52 ` kernel test robot

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