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([2602:47:d483:7301:72f0:1ea7:85d2:141e]) by smtp.gmail.com with ESMTPSA id n9-20020a170902968900b001b03a1a3151sm11331257plp.70.2023.08.23.12.05.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 23 Aug 2023 12:05:04 -0700 (PDT) Message-ID: <862d1957-cd73-0367-8e9c-adba16a55ab1@linaro.org> Date: Wed, 23 Aug 2023 12:05:02 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [RFC PATCH 2/5] HACK: target/arm/tcg: Add some more caches to cpu=max Content-Language: en-US To: Jonathan Cameron , =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: qemu-devel@nongnu.org, Gavin Shan , linuxarm@huawei.com, James Morse , "peter . maydell @ linaro . org" , zhao1.liu@linux.intel.com, Shameerali Kolothum Thodi , Yicong Yang References: <20230808115713.2613-1-Jonathan.Cameron@huawei.com> <20230808115713.2613-3-Jonathan.Cameron@huawei.com> <87y1ierkuh.fsf@linaro.org> <20230823155949.000071d2@Huawei.com> From: Richard Henderson In-Reply-To: <20230823155949.000071d2@Huawei.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -47 X-Spam_score: -4.8 X-Spam_bar: ---- X-Spam_report: (-4.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.684, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/23/23 07:59, Jonathan Cameron via wrote: > On Mon, 14 Aug 2023 11:13:58 +0100 > Alex Bennée wrote: > >> Jonathan Cameron writes: >> >>> Used to drive the MPAM cache intialization and to exercise more >>> of the PPTT cache entry generation code. Perhaps a default >>> L3 cache is acceptable for max? >>> >>> Signed-off-by: Jonathan Cameron >>> --- >>> target/arm/tcg/cpu64.c | 12 ++++++++++++ >>> 1 file changed, 12 insertions(+) >>> >>> diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c >>> index 8019f00bc3..2af67739f6 100644 >>> --- a/target/arm/tcg/cpu64.c >>> +++ b/target/arm/tcg/cpu64.c >>> @@ -711,6 +711,17 @@ void aarch64_max_tcg_initfn(Object *obj) >>> uint64_t t; >>> uint32_t u; >>> >>> + /* >>> + * Expanded cache set >>> + */ >>> + cpu->clidr = 0x8204923; /* 4 4 4 4 3 in 3 bit fields */ >>> + cpu->ccsidr[0] = 0x000000ff0000001aull; /* 64KB L1 dcache */ >>> + cpu->ccsidr[1] = 0x000000ff0000001aull; /* 64KB L1 icache */ >>> + cpu->ccsidr[2] = 0x000007ff0000003aull; /* 1MB L2 unified cache */ >>> + cpu->ccsidr[4] = 0x000007ff0000007cull; /* 2MB L3 cache 128B line */ >>> + cpu->ccsidr[6] = 0x00007fff0000007cull; /* 16MB L4 cache 128B line */ >>> + cpu->ccsidr[8] = 0x0007ffff0000007cull; /* 2048MB L5 cache 128B line */ >>> + >> >> I think Peter in another thread wondered if we should have a generic >> function for expanding the cache idr registers based on a abstract lane >> definition. >> > > Great! > > This response? > https://lore.kernel.org/qemu-devel/CAFEAcA_Lzj1LEutMro72fCfqiCWtOpd+5b-YPcfKv8Bg1f+rCg@mail.gmail.com/ Followed up with https://lore.kernel.org/qemu-devel/20230811214031.171020-6-richard.henderson@linaro.org/ r~