From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH for-8.0 v3 34/45] tcg: Introduce tcg_target_call_oarg_reg
Date: Tue, 22 Nov 2022 06:41:57 -0300 [thread overview]
Message-ID: <86410eda-e0aa-89b8-6089-51bb75c4841f@gmail.com> (raw)
In-Reply-To: <20221111074101.2069454-35-richard.henderson@linaro.org>
On 11/11/22 04:40, Richard Henderson wrote:
> Replace the flat array tcg_target_call_oarg_regs[] with
> a function call including the TCGCallReturnKind.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
For ppc and common code bits:
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
> tcg/tcg.c | 9 ++++++---
> tcg/aarch64/tcg-target.c.inc | 10 +++++++---
> tcg/arm/tcg-target.c.inc | 10 +++++++---
> tcg/i386/tcg-target.c.inc | 16 ++++++++++------
> tcg/loongarch64/tcg-target.c.inc | 10 ++++++----
> tcg/mips/tcg-target.c.inc | 10 ++++++----
> tcg/ppc/tcg-target.c.inc | 10 ++++++----
> tcg/riscv/tcg-target.c.inc | 10 ++++++----
> tcg/s390x/tcg-target.c.inc | 9 ++++++---
> tcg/sparc64/tcg-target.c.inc | 12 ++++++------
> tcg/tci/tcg-target.c.inc | 12 ++++++------
> 11 files changed, 72 insertions(+), 46 deletions(-)
>
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index b61551913b..97c97158cd 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -148,6 +148,7 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
> TCGReg base, intptr_t ofs);
> static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target,
> const TCGHelperInfo *info);
> +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot);
> static bool tcg_target_const_match(int64_t val, TCGType type, int ct);
> #ifdef TCG_TARGET_NEED_LDST_LABELS
> static int tcg_out_ldst_finalize(TCGContext *s);
> @@ -718,14 +719,16 @@ static void init_call_layout(TCGHelperInfo *info)
> case dh_typecode_s64:
> info->nr_out = 64 / TCG_TARGET_REG_BITS;
> info->out_kind = TCG_CALL_RET_NORMAL;
> - assert(info->nr_out <= ARRAY_SIZE(tcg_target_call_oarg_regs));
> + /* Query the last register now to trigger any assert early. */
> + tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1);
> break;
> case dh_typecode_i128:
> info->nr_out = 128 / TCG_TARGET_REG_BITS;
> info->out_kind = TCG_CALL_RET_NORMAL; /* TODO */
> switch (/* TODO */ TCG_CALL_RET_NORMAL) {
> case TCG_CALL_RET_NORMAL:
> - assert(info->nr_out <= ARRAY_SIZE(tcg_target_call_oarg_regs));
> + /* Query the last register now to trigger any assert early. */
> + tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1);
> break;
> case TCG_CALL_RET_BY_REF:
> /*
> @@ -4579,7 +4582,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op)
> case TCG_CALL_RET_NORMAL:
> for (i = 0; i < nb_oargs; i++) {
> TCGTemp *ts = arg_temp(op->args[i]);
> - TCGReg reg = tcg_target_call_oarg_regs[i];
> + TCGReg reg = tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, i);
>
> /* ENV should not be modified. */
> tcg_debug_assert(!temp_readonly(ts));
> diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
> index 2279a14c11..dfe569dd8c 100644
> --- a/tcg/aarch64/tcg-target.c.inc
> +++ b/tcg/aarch64/tcg-target.c.inc
> @@ -63,9 +63,13 @@ static const int tcg_target_call_iarg_regs[8] = {
> TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3,
> TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7
> };
> -static const int tcg_target_call_oarg_regs[1] = {
> - TCG_REG_X0
> -};
> +
> +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
> +{
> + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
> + tcg_debug_assert(slot >= 0 && slot <= 1);
> + return TCG_REG_X0 + slot;
> +}
>
> #define TCG_REG_TMP TCG_REG_X30
> #define TCG_VEC_TMP TCG_REG_V31
> diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
> index 2950a29d49..add90ddeb4 100644
> --- a/tcg/arm/tcg-target.c.inc
> +++ b/tcg/arm/tcg-target.c.inc
> @@ -79,9 +79,13 @@ static const int tcg_target_reg_alloc_order[] = {
> static const int tcg_target_call_iarg_regs[4] = {
> TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
> };
> -static const int tcg_target_call_oarg_regs[2] = {
> - TCG_REG_R0, TCG_REG_R1
> -};
> +
> +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
> +{
> + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
> + tcg_debug_assert(slot >= 0 && slot <= 3);
> + return TCG_REG_R0 + slot;
> +}
>
> #define TCG_REG_TMP TCG_REG_R12
> #define TCG_VEC_TMP TCG_REG_Q15
> diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
> index 6a021dda8b..ab6881a4f3 100644
> --- a/tcg/i386/tcg-target.c.inc
> +++ b/tcg/i386/tcg-target.c.inc
> @@ -109,12 +109,16 @@ static const int tcg_target_call_iarg_regs[] = {
> #endif
> };
>
> -static const int tcg_target_call_oarg_regs[] = {
> - TCG_REG_EAX,
> -#if TCG_TARGET_REG_BITS == 32
> - TCG_REG_EDX
> -#endif
> -};
> +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
> +{
> + switch (kind) {
> + case TCG_CALL_RET_NORMAL:
> + tcg_debug_assert(slot >= 0 && slot <= 1);
> + return slot ? TCG_REG_EDX : TCG_REG_EAX;
> + default:
> + g_assert_not_reached();
> + }
> +}
>
> /* Constants we accept. */
> #define TCG_CT_CONST_S32 0x100
> diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
> index 54b1dcd911..f6b0ed00bb 100644
> --- a/tcg/loongarch64/tcg-target.c.inc
> +++ b/tcg/loongarch64/tcg-target.c.inc
> @@ -114,10 +114,12 @@ static const int tcg_target_call_iarg_regs[] = {
> TCG_REG_A7,
> };
>
> -static const int tcg_target_call_oarg_regs[] = {
> - TCG_REG_A0,
> - TCG_REG_A1,
> -};
> +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
> +{
> + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
> + tcg_debug_assert(slot >= 0 && slot <= 1);
> + return TCG_REG_A0 + slot;
> +}
>
> #ifndef CONFIG_SOFTMMU
> #define USE_GUEST_BASE (guest_base != 0)
> diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
> index 22b5463f0f..92883176c6 100644
> --- a/tcg/mips/tcg-target.c.inc
> +++ b/tcg/mips/tcg-target.c.inc
> @@ -136,10 +136,12 @@ static const TCGReg tcg_target_call_iarg_regs[] = {
> #endif
> };
>
> -static const TCGReg tcg_target_call_oarg_regs[2] = {
> - TCG_REG_V0,
> - TCG_REG_V1
> -};
> +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
> +{
> + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
> + tcg_debug_assert(slot >= 0 && slot <= 1);
> + return TCG_REG_V0 + slot;
> +}
>
> static const tcg_insn_unit *tb_ret_addr;
> static const tcg_insn_unit *bswap32_addr;
> diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
> index d9e4ba8883..781ecfe161 100644
> --- a/tcg/ppc/tcg-target.c.inc
> +++ b/tcg/ppc/tcg-target.c.inc
> @@ -186,10 +186,12 @@ static const int tcg_target_call_iarg_regs[] = {
> TCG_REG_R10
> };
>
> -static const int tcg_target_call_oarg_regs[] = {
> - TCG_REG_R3,
> - TCG_REG_R4
> -};
> +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
> +{
> + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
> + tcg_debug_assert(slot >= 0 && slot <= 1);
> + return TCG_REG_R3 + slot;
> +}
>
> static const int tcg_target_callee_save_regs[] = {
> #ifdef _CALL_DARWIN
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 6072945ccb..417736cae7 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -113,10 +113,12 @@ static const int tcg_target_call_iarg_regs[] = {
> TCG_REG_A7,
> };
>
> -static const int tcg_target_call_oarg_regs[] = {
> - TCG_REG_A0,
> - TCG_REG_A1,
> -};
> +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
> +{
> + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
> + tcg_debug_assert(slot >= 0 && slot <= 1);
> + return TCG_REG_A0 + slot;
> +}
>
> #define TCG_CT_CONST_ZERO 0x100
> #define TCG_CT_CONST_S12 0x200
> diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
> index 8663a963a6..50655e9d1d 100644
> --- a/tcg/s390x/tcg-target.c.inc
> +++ b/tcg/s390x/tcg-target.c.inc
> @@ -390,9 +390,12 @@ static const int tcg_target_call_iarg_regs[] = {
> TCG_REG_R6,
> };
>
> -static const int tcg_target_call_oarg_regs[] = {
> - TCG_REG_R2,
> -};
> +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
> +{
> + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
> + tcg_debug_assert(slot == 0);
> + return TCG_REG_R2;
> +}
>
> #define S390_CC_EQ 8
> #define S390_CC_LT 4
> diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc
> index f6a8a8e605..9b5afb8248 100644
> --- a/tcg/sparc64/tcg-target.c.inc
> +++ b/tcg/sparc64/tcg-target.c.inc
> @@ -133,12 +133,12 @@ static const int tcg_target_call_iarg_regs[6] = {
> TCG_REG_O5,
> };
>
> -static const int tcg_target_call_oarg_regs[] = {
> - TCG_REG_O0,
> - TCG_REG_O1,
> - TCG_REG_O2,
> - TCG_REG_O3,
> -};
> +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
> +{
> + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
> + tcg_debug_assert(slot >= 0 && slot <= 3);
> + return TCG_REG_O0 + slot;
> +}
>
> #define INSN_OP(x) ((x) << 30)
> #define INSN_OP2(x) ((x) << 22)
> diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
> index 633345d74b..cd53cb6b6b 100644
> --- a/tcg/tci/tcg-target.c.inc
> +++ b/tcg/tci/tcg-target.c.inc
> @@ -200,12 +200,12 @@ static const int tcg_target_reg_alloc_order[] = {
> /* No call arguments via registers. All will be stored on the "stack". */
> static const int tcg_target_call_iarg_regs[] = { };
>
> -static const int tcg_target_call_oarg_regs[] = {
> - TCG_REG_R0,
> -#if TCG_TARGET_REG_BITS == 32
> - TCG_REG_R1
> -#endif
> -};
> +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
> +{
> + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
> + tcg_debug_assert(slot >= 0 && slot < 64 / TCG_TARGET_REG_BITS);
> + return TCG_REG_R0 + slot;
> +}
>
> #ifdef CONFIG_DEBUG_TCG
> static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
next prev parent reply other threads:[~2022-11-22 9:42 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-11 7:40 [PATCH for-8.0 v3 00/45] tcg: Support for Int128 with helpers Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 01/45] meson: Move CONFIG_TCG_INTERPRETER to config_host Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 02/45] tcg: Tidy tcg_reg_alloc_op Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 03/45] tcg: Introduce paired register allocation Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 04/45] tcg/s390x: Use register pair allocation for div and mulu2 Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 05/45] tcg/arm: Use register pair allocation for qemu_{ld, st}_i64 Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 06/45] tcg: Remove TCG_TARGET_STACK_GROWSUP Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 07/45] accel/tcg: Set cflags_next_tb in cpu_common_initfn Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 08/45] target/sparc: Avoid TCGV_{LOW,HIGH} Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 09/45] tcg: Move TCG_{LOW,HIGH} to tcg-internal.h Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 10/45] tcg: Add temp_subindex to TCGTemp Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 11/45] tcg: Simplify calls to temp_sync vs mem_coherent Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 12/45] tcg: Allocate TCGTemp pairs in host memory order Richard Henderson
2022-11-22 11:25 ` Philippe Mathieu-Daudé
2022-11-11 7:40 ` [PATCH for-8.0 v3 13/45] tcg: Move TCG_TYPE_COUNT outside enum Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 14/45] tcg: Introduce tcg_type_size Richard Henderson
2022-11-22 11:30 ` Philippe Mathieu-Daudé
2022-11-22 16:54 ` Richard Henderson
2022-11-22 18:14 ` Philippe Mathieu-Daudé
2022-11-22 18:15 ` Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 15/45] tcg: Introduce TCGCallReturnKind and TCGCallArgumentKind Richard Henderson
2022-11-22 11:33 ` Philippe Mathieu-Daudé
2022-11-11 7:40 ` [PATCH for-8.0 v3 16/45] tcg: Replace TCG_TARGET_CALL_ALIGN_ARGS with TCG_TARGET_CALL_ARG_I64 Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 17/45] tcg: Replace TCG_TARGET_EXTEND_ARGS with TCG_TARGET_CALL_ARG_I32 Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 18/45] tcg: Use TCG_CALL_ARG_EVEN for TCI special case Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 19/45] accel/tcg/plugin: Don't search for the function pointer index Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 20/45] accel/tcg/plugin: Avoid duplicate copy in copy_call Richard Henderson
2022-11-22 15:21 ` Philippe Mathieu-Daudé
2022-11-11 7:40 ` [PATCH for-8.0 v3 21/45] accel/tcg/plugin: Use copy_op in append_{udata, mem}_cb Richard Henderson
2022-11-22 15:22 ` Philippe Mathieu-Daudé
2022-11-11 7:40 ` [PATCH for-8.0 v3 22/45] tci: MAX_OPC_PARAM_IARGS is no longer used Richard Henderson
2022-11-22 15:25 ` Philippe Mathieu-Daudé
2022-11-11 7:40 ` [PATCH for-8.0 v3 23/45] tcg: Vary the allocation size for TCGOp Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 24/45] tcg: Use output_pref wrapper function Richard Henderson
2022-11-22 15:28 ` Philippe Mathieu-Daudé
2022-11-11 7:40 ` [PATCH for-8.0 v3 25/45] tcg: Reorg function calls Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 26/45] tcg: Move ffi_cif pointer into TCGHelperInfo Richard Henderson
2022-11-22 18:08 ` [PATCH 0/3] tcg: Move ffi_cif pointer into TCGHelperInfo (splitted) Philippe Mathieu-Daudé
2022-11-22 18:08 ` [PATCH 1/3] tcg: Convert typecode_to_ffi from array to function Philippe Mathieu-Daudé
2022-11-22 18:08 ` [PATCH 2/3] tcg: Factor init_ffi_layouts() out of tcg_context_init() Philippe Mathieu-Daudé
2022-11-22 18:08 ` [PATCH 3/3] tcg: Move ffi_cif pointer into TCGHelperInfo Philippe Mathieu-Daudé
2022-11-23 16:22 ` Philippe Mathieu-Daudé
2022-11-11 7:40 ` [PATCH for-8.0 v3 27/45] tcg/aarch64: Merge tcg_out_callr into tcg_out_call Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 28/45] tcg: Add TCGHelperInfo argument to tcg_out_call Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 29/45] tcg: Define TCG_TYPE_I128 and related helper macros Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 30/45] tcg: Handle dh_typecode_i128 with TCG_CALL_{RET, ARG}_NORMAL Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 31/45] tcg: Allocate objects contiguously in temp_allocate_frame Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 32/45] tcg: Introduce tcg_out_addi_ptr Richard Henderson
2022-11-22 9:45 ` Daniel Henrique Barboza
2022-11-11 7:40 ` [PATCH for-8.0 v3 33/45] tcg: Add TCG_CALL_{RET,ARG}_BY_REF Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 34/45] tcg: Introduce tcg_target_call_oarg_reg Richard Henderson
2022-11-22 9:41 ` Daniel Henrique Barboza [this message]
2022-11-11 7:40 ` [PATCH for-8.0 v3 35/45] tcg: Add TCG_CALL_RET_BY_VEC Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 36/45] include/qemu/int128: Use Int128 structure for TCI Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 37/45] tcg/i386: Add TCG_TARGET_CALL_{RET, ARG}_I128 Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 38/45] tcg/tci: Fix big-endian return register ordering Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 39/45] tcg/tci: Add TCG_TARGET_CALL_{RET,ARG}_I128 Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 40/45] tcg: " Richard Henderson
2022-11-22 9:47 ` Daniel Henrique Barboza
2022-11-11 7:40 ` [PATCH for-8.0 v3 41/45] tcg: Add temp allocation for TCGv_i128 Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 42/45] tcg: Add basic data movement " Richard Henderson
2022-11-11 7:40 ` [PATCH for-8.0 v3 43/45] tcg: Add guest load/store primitives " Richard Henderson
2022-11-11 7:41 ` [PATCH for-8.0 v3 44/45] tcg: Add tcg_gen_{non}atomic_cmpxchg_i128 Richard Henderson
2022-11-11 7:41 ` [PATCH for-8.0 v3 45/45] tcg: Split out tcg_gen_nonatomic_cmpxchg_i{32, 64} Richard Henderson
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