From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
Alistair Francis <alistair23@gmail.com>
Cc: Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bin.meng@windriver.com>,
"open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: TCG op for 32 bit only cpu on qemu-riscv64
Date: Mon, 7 Jun 2021 08:59:05 -0700 [thread overview]
Message-ID: <86461776-b805-42a6-6c64-bca5f1be6dd1@linaro.org> (raw)
In-Reply-To: <e82c9f94-4367-2ed6-7c7c-846e8a270876@c-sky.com>
On 6/7/21 2:22 AM, LIU Zhiwei wrote:
>
> I am implementing RVP to get rid of TARGET_RISCV64. After we have recognized an
> instruction only used by a 32-bit CPU,
>
> 1) Should we only use the lowest 32bits of the 64bits register in RV64?
>
> TCGv s;
> TCGv_i32 s32;
> s = tcg_new_temp();
> s32 = tcg_new_temp_i32();
> gen_get_gpr(src1, a->rs1);
> tcg_gen_trunc_tl_i32(s32, s);
>
> Then we can use TCGv_i32 s32 to stand for rs1 register.
Changing from _tl to _i32 is wrong for most things, because you'll just have to
convert back in order to store the result.
Most often you'll get the correct results by just using _tl as is. One
operation I can think of right away which probably requires extra attention is
right-shift. In which case just sign- or zero-extend the input first.
r~
next prev parent reply other threads:[~2021-06-07 16:03 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-07 3:07 TCG op for 32 bit only cpu on qemu-riscv64 LIU Zhiwei
2021-06-07 6:22 ` Alistair Francis
2021-06-07 9:22 ` LIU Zhiwei
2021-06-07 15:59 ` Richard Henderson [this message]
2021-06-07 15:52 ` Richard Henderson
2021-06-10 1:43 ` LIU Zhiwei
2021-06-10 13:29 ` Richard Henderson
2021-06-11 2:33 ` LIU Zhiwei
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