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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id em15sm11521836pjb.43.2021.06.07.08.59.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Jun 2021 08:59:06 -0700 (PDT) Subject: Re: TCG op for 32 bit only cpu on qemu-riscv64 To: LIU Zhiwei , Alistair Francis References: <97935519-42c8-71c8-3d87-30aa4cafc909@c-sky.com> From: Richard Henderson Message-ID: <86461776-b805-42a6-6c64-bca5f1be6dd1@linaro.org> Date: Mon, 7 Jun 2021 08:59:05 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , Bin Meng , "open list:RISC-V TCG CPUs" , QEMU Developers Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/7/21 2:22 AM, LIU Zhiwei wrote: > > I am implementing RVP to get rid of TARGET_RISCV64. After we have recognized an > instruction only used by a 32-bit CPU, > > 1) Should we only use the lowest 32bits of the 64bits register in RV64? > > TCGv s; > TCGv_i32 s32; > s = tcg_new_temp(); > s32 = tcg_new_temp_i32(); > gen_get_gpr(src1, a->rs1); > tcg_gen_trunc_tl_i32(s32, s); > > Then we can use TCGv_i32 s32  to stand for rs1 register. Changing from _tl to _i32 is wrong for most things, because you'll just have to convert back in order to store the result. Most often you'll get the correct results by just using _tl as is. One operation I can think of right away which probably requires extra attention is right-shift. In which case just sign- or zero-extend the input first. r~