* [PATCH 1/6] hw/ppc: Add VMSTATE information for LPC model
2025-12-11 22:09 [PATCH 0/6] hw/ppc: Snapshot support for several ppc devices Caleb Schlossin
@ 2025-12-11 22:09 ` Caleb Schlossin
2025-12-12 17:12 ` Miles Glenn
2025-12-11 22:09 ` [PATCH 2/6] hw/ppc: Add pnv_spi vmstate support Caleb Schlossin
` (5 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Caleb Schlossin @ 2025-12-11 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, npiggin, adityag, milesg, alistair, kowal, chalapathi.v,
calebs, angeloj
The PNV LPC model needs snapshot/migration support. Added a VMSTATE
descriptor to save model data and an associated post_load() method.
Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
---
hw/ppc/pnv_lpc.c | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index f6beba0917..7f11fd312a 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -30,6 +30,7 @@
#include "hw/ppc/pnv_lpc.h"
#include "hw/ppc/pnv_xscom.h"
#include "hw/ppc/fdt.h"
+#include "migration/vmstate.h"
#include <libfdt.h>
@@ -777,11 +778,49 @@ static const TypeInfo pnv_lpc_power9_info = {
.class_init = pnv_lpc_power9_class_init,
};
+static int vmstate_pnv_lpc_post_load(void *opaque, int version_id)
+{
+ PnvLpcController *lpc = PNV_LPC(opaque);
+
+ memory_region_set_alias_offset(&lpc->opb_isa_fw,
+ lpc->lpc_hc_fw_seg_idsel * LPC_FW_OPB_SIZE);
+ pnv_lpc_eval_serirq_routes(lpc);
+
+ pnv_lpc_eval_irqs(lpc);
+ return 0;
+}
+
+static const VMStateDescription vmstate_pnv_lpc = {
+ .name = TYPE_PNV_LPC,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .post_load = vmstate_pnv_lpc_post_load,
+ .fields = (const VMStateField[]) {
+ VMSTATE_UINT64(eccb_stat_reg, PnvLpcController),
+ VMSTATE_UINT32(eccb_data_reg, PnvLpcController),
+ VMSTATE_UINT32(opb_irq_route0, PnvLpcController),
+ VMSTATE_UINT32(opb_irq_route1, PnvLpcController),
+ VMSTATE_UINT32(opb_irq_stat, PnvLpcController),
+ VMSTATE_UINT32(opb_irq_mask, PnvLpcController),
+ VMSTATE_UINT32(opb_irq_pol, PnvLpcController),
+ VMSTATE_UINT32(opb_irq_input, PnvLpcController),
+ VMSTATE_UINT32(lpc_hc_irq_inputs, PnvLpcController),
+ VMSTATE_UINT32(lpc_hc_fw_seg_idsel, PnvLpcController),
+ VMSTATE_UINT32(lpc_hc_irqser_ctrl, PnvLpcController),
+ VMSTATE_UINT32(lpc_hc_irqmask, PnvLpcController),
+ VMSTATE_UINT32(lpc_hc_irqstat, PnvLpcController),
+ VMSTATE_UINT32(lpc_hc_error_addr, PnvLpcController),
+ VMSTATE_UINT32(lpc_hc_fw_rd_acc_size, PnvLpcController),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static void pnv_lpc_power10_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->desc = "PowerNV LPC Controller POWER10";
+ dc->vmsd = &vmstate_pnv_lpc;
}
static const TypeInfo pnv_lpc_power10_info = {
--
2.47.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 1/6] hw/ppc: Add VMSTATE information for LPC model
2025-12-11 22:09 ` [PATCH 1/6] hw/ppc: Add VMSTATE information for LPC model Caleb Schlossin
@ 2025-12-12 17:12 ` Miles Glenn
0 siblings, 0 replies; 16+ messages in thread
From: Miles Glenn @ 2025-12-12 17:12 UTC (permalink / raw)
To: Caleb Schlossin, qemu-devel
Cc: qemu-ppc, npiggin, adityag, alistair, kowal, chalapathi.v,
angeloj
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
On Thu, 2025-12-11 at 16:09 -0600, Caleb Schlossin wrote:
> The PNV LPC model needs snapshot/migration support. Added a VMSTATE
> descriptor to save model data and an associated post_load() method.
>
> Signed-off-by: Michael Kowal <kowal@linux.ibm.com>
> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
> ---
> hw/ppc/pnv_lpc.c | 39 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
> index f6beba0917..7f11fd312a 100644
> --- a/hw/ppc/pnv_lpc.c
> +++ b/hw/ppc/pnv_lpc.c
> @@ -30,6 +30,7 @@
> #include "hw/ppc/pnv_lpc.h"
> #include "hw/ppc/pnv_xscom.h"
> #include "hw/ppc/fdt.h"
> +#include "migration/vmstate.h"
>
> #include <libfdt.h>
>
> @@ -777,11 +778,49 @@ static const TypeInfo pnv_lpc_power9_info = {
> .class_init = pnv_lpc_power9_class_init,
> };
>
> +static int vmstate_pnv_lpc_post_load(void *opaque, int version_id)
> +{
> + PnvLpcController *lpc = PNV_LPC(opaque);
> +
> + memory_region_set_alias_offset(&lpc->opb_isa_fw,
> + lpc->lpc_hc_fw_seg_idsel * LPC_FW_OPB_SIZE);
> + pnv_lpc_eval_serirq_routes(lpc);
> +
> + pnv_lpc_eval_irqs(lpc);
> + return 0;
> +}
> +
> +static const VMStateDescription vmstate_pnv_lpc = {
> + .name = TYPE_PNV_LPC,
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .post_load = vmstate_pnv_lpc_post_load,
> + .fields = (const VMStateField[]) {
> + VMSTATE_UINT64(eccb_stat_reg, PnvLpcController),
> + VMSTATE_UINT32(eccb_data_reg, PnvLpcController),
> + VMSTATE_UINT32(opb_irq_route0, PnvLpcController),
> + VMSTATE_UINT32(opb_irq_route1, PnvLpcController),
> + VMSTATE_UINT32(opb_irq_stat, PnvLpcController),
> + VMSTATE_UINT32(opb_irq_mask, PnvLpcController),
> + VMSTATE_UINT32(opb_irq_pol, PnvLpcController),
> + VMSTATE_UINT32(opb_irq_input, PnvLpcController),
> + VMSTATE_UINT32(lpc_hc_irq_inputs, PnvLpcController),
> + VMSTATE_UINT32(lpc_hc_fw_seg_idsel, PnvLpcController),
> + VMSTATE_UINT32(lpc_hc_irqser_ctrl, PnvLpcController),
> + VMSTATE_UINT32(lpc_hc_irqmask, PnvLpcController),
> + VMSTATE_UINT32(lpc_hc_irqstat, PnvLpcController),
> + VMSTATE_UINT32(lpc_hc_error_addr, PnvLpcController),
> + VMSTATE_UINT32(lpc_hc_fw_rd_acc_size, PnvLpcController),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> static void pnv_lpc_power10_class_init(ObjectClass *klass, const void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
>
> dc->desc = "PowerNV LPC Controller POWER10";
> + dc->vmsd = &vmstate_pnv_lpc;
> }
>
> static const TypeInfo pnv_lpc_power10_info = {
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 2/6] hw/ppc: Add pnv_spi vmstate support
2025-12-11 22:09 [PATCH 0/6] hw/ppc: Snapshot support for several ppc devices Caleb Schlossin
2025-12-11 22:09 ` [PATCH 1/6] hw/ppc: Add VMSTATE information for LPC model Caleb Schlossin
@ 2025-12-11 22:09 ` Caleb Schlossin
2025-12-12 17:29 ` Miles Glenn
2025-12-11 22:09 ` [PATCH 3/6] hw/ppc: Add pnv_i2c " Caleb Schlossin
` (4 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Caleb Schlossin @ 2025-12-11 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, npiggin, adityag, milesg, alistair, kowal, chalapathi.v,
calebs, angeloj
- Add support for needed PnvSpi structure variables
Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
---
hw/ssi/pnv_spi.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/hw/ssi/pnv_spi.c b/hw/ssi/pnv_spi.c
index f40e8836b9..389a2cca6b 100644
--- a/hw/ssi/pnv_spi.c
+++ b/hw/ssi/pnv_spi.c
@@ -13,6 +13,7 @@
#include "hw/ssi/pnv_spi.h"
#include "hw/ssi/pnv_spi_regs.h"
#include "hw/ssi/ssi.h"
+#include "migration/vmstate.h"
#include <libfdt.h>
#include "hw/irq.h"
#include "trace.h"
@@ -1199,6 +1200,31 @@ static int pnv_spi_dt_xscom(PnvXScomInterface *dev, void *fdt,
return 0;
}
+static const VMStateDescription pnv_spi_vmstate = {
+ .name = TYPE_PNV_SPI,
+ .version_id = 1,
+ .fields = (const VMStateField[]) {
+ VMSTATE_UINT8(fail_count, PnvSpi),
+ VMSTATE_UINT8(transfer_len, PnvSpi),
+ VMSTATE_UINT8(responder_select, PnvSpi),
+ VMSTATE_BOOL(shift_n1_done, PnvSpi),
+ VMSTATE_UINT8(loop_counter_1, PnvSpi),
+ VMSTATE_UINT8(loop_counter_2, PnvSpi),
+ VMSTATE_UINT8(N1_bits, PnvSpi),
+ VMSTATE_UINT8(N2_bits, PnvSpi),
+ VMSTATE_UINT8(N1_bytes, PnvSpi),
+ VMSTATE_UINT8(N2_bytes, PnvSpi),
+ VMSTATE_UINT8(N1_tx, PnvSpi),
+ VMSTATE_UINT8(N2_tx, PnvSpi),
+ VMSTATE_UINT8(N1_rx, PnvSpi),
+ VMSTATE_UINT8(N2_rx, PnvSpi),
+ VMSTATE_UINT64_ARRAY(regs, PnvSpi, PNV_SPI_REGS),
+ VMSTATE_UINT8_ARRAY(seq_op, PnvSpi, PNV_SPI_REG_SIZE),
+ VMSTATE_UINT64(status, PnvSpi),
+ VMSTATE_END_OF_LIST(),
+ },
+};
+
static void pnv_spi_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -1209,6 +1235,7 @@ static void pnv_spi_class_init(ObjectClass *klass, const void *data)
dc->desc = "PowerNV SPI";
dc->realize = pnv_spi_realize;
device_class_set_legacy_reset(dc, do_reset);
+ dc->vmsd = &pnv_spi_vmstate;
device_class_set_props(dc, pnv_spi_properties);
}
--
2.47.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 2/6] hw/ppc: Add pnv_spi vmstate support
2025-12-11 22:09 ` [PATCH 2/6] hw/ppc: Add pnv_spi vmstate support Caleb Schlossin
@ 2025-12-12 17:29 ` Miles Glenn
0 siblings, 0 replies; 16+ messages in thread
From: Miles Glenn @ 2025-12-12 17:29 UTC (permalink / raw)
To: Caleb Schlossin, qemu-devel
Cc: qemu-ppc, npiggin, adityag, alistair, kowal, chalapathi.v,
angeloj
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
On Thu, 2025-12-11 at 16:09 -0600, Caleb Schlossin wrote:
> - Add support for needed PnvSpi structure variables
>
> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
> ---
> hw/ssi/pnv_spi.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/hw/ssi/pnv_spi.c b/hw/ssi/pnv_spi.c
> index f40e8836b9..389a2cca6b 100644
> --- a/hw/ssi/pnv_spi.c
> +++ b/hw/ssi/pnv_spi.c
> @@ -13,6 +13,7 @@
> #include "hw/ssi/pnv_spi.h"
> #include "hw/ssi/pnv_spi_regs.h"
> #include "hw/ssi/ssi.h"
> +#include "migration/vmstate.h"
> #include <libfdt.h>
> #include "hw/irq.h"
> #include "trace.h"
> @@ -1199,6 +1200,31 @@ static int pnv_spi_dt_xscom(PnvXScomInterface *dev, void *fdt,
> return 0;
> }
>
> +static const VMStateDescription pnv_spi_vmstate = {
> + .name = TYPE_PNV_SPI,
> + .version_id = 1,
> + .fields = (const VMStateField[]) {
> + VMSTATE_UINT8(fail_count, PnvSpi),
> + VMSTATE_UINT8(transfer_len, PnvSpi),
> + VMSTATE_UINT8(responder_select, PnvSpi),
> + VMSTATE_BOOL(shift_n1_done, PnvSpi),
> + VMSTATE_UINT8(loop_counter_1, PnvSpi),
> + VMSTATE_UINT8(loop_counter_2, PnvSpi),
> + VMSTATE_UINT8(N1_bits, PnvSpi),
> + VMSTATE_UINT8(N2_bits, PnvSpi),
> + VMSTATE_UINT8(N1_bytes, PnvSpi),
> + VMSTATE_UINT8(N2_bytes, PnvSpi),
> + VMSTATE_UINT8(N1_tx, PnvSpi),
> + VMSTATE_UINT8(N2_tx, PnvSpi),
> + VMSTATE_UINT8(N1_rx, PnvSpi),
> + VMSTATE_UINT8(N2_rx, PnvSpi),
> + VMSTATE_UINT64_ARRAY(regs, PnvSpi, PNV_SPI_REGS),
> + VMSTATE_UINT8_ARRAY(seq_op, PnvSpi, PNV_SPI_REG_SIZE),
> + VMSTATE_UINT64(status, PnvSpi),
> + VMSTATE_END_OF_LIST(),
> + },
> +};
> +
> static void pnv_spi_class_init(ObjectClass *klass, const void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -1209,6 +1235,7 @@ static void pnv_spi_class_init(ObjectClass *klass, const void *data)
> dc->desc = "PowerNV SPI";
> dc->realize = pnv_spi_realize;
> device_class_set_legacy_reset(dc, do_reset);
> + dc->vmsd = &pnv_spi_vmstate;
> device_class_set_props(dc, pnv_spi_properties);
> }
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/6] hw/ppc: Add pnv_i2c vmstate support
2025-12-11 22:09 [PATCH 0/6] hw/ppc: Snapshot support for several ppc devices Caleb Schlossin
2025-12-11 22:09 ` [PATCH 1/6] hw/ppc: Add VMSTATE information for LPC model Caleb Schlossin
2025-12-11 22:09 ` [PATCH 2/6] hw/ppc: Add pnv_spi vmstate support Caleb Schlossin
@ 2025-12-11 22:09 ` Caleb Schlossin
2025-12-12 17:16 ` Miles Glenn
2025-12-11 22:09 ` [PATCH 4/6] hw/ppc: pnv_adu.c added " Caleb Schlossin
` (3 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Caleb Schlossin @ 2025-12-11 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, npiggin, adityag, milesg, alistair, kowal, chalapathi.v,
calebs, angeloj
- Add vmstate support for i2c registers
Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
---
hw/ppc/pnv_i2c.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/hw/ppc/pnv_i2c.c b/hw/ppc/pnv_i2c.c
index 60de479491..1018078228 100644
--- a/hw/ppc/pnv_i2c.c
+++ b/hw/ppc/pnv_i2c.c
@@ -19,6 +19,7 @@
#include "hw/ppc/pnv_i2c.h"
#include "hw/ppc/pnv_xscom.h"
#include "hw/ppc/fdt.h"
+#include "migration/vmstate.h"
#include <libfdt.h>
@@ -549,6 +550,15 @@ static const Property pnv_i2c_properties[] = {
DEFINE_PROP_UINT32("num-busses", PnvI2C, num_busses, 1),
};
+static const VMStateDescription pnv_i2c_vmstate = {
+ .name = TYPE_PNV_I2C,
+ .version_id = 1,
+ .fields = (const VMStateField[]) {
+ VMSTATE_UINT64_ARRAY(regs, PnvI2C, PNV_I2C_REGS),
+ VMSTATE_END_OF_LIST(),
+ },
+};
+
static void pnv_i2c_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -561,6 +571,7 @@ static void pnv_i2c_class_init(ObjectClass *klass, const void *data)
dc->desc = "PowerNV I2C";
dc->realize = pnv_i2c_realize;
+ dc->vmsd = &pnv_i2c_vmstate;
device_class_set_props(dc, pnv_i2c_properties);
}
--
2.47.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 3/6] hw/ppc: Add pnv_i2c vmstate support
2025-12-11 22:09 ` [PATCH 3/6] hw/ppc: Add pnv_i2c " Caleb Schlossin
@ 2025-12-12 17:16 ` Miles Glenn
0 siblings, 0 replies; 16+ messages in thread
From: Miles Glenn @ 2025-12-12 17:16 UTC (permalink / raw)
To: Caleb Schlossin, qemu-devel
Cc: qemu-ppc, npiggin, adityag, alistair, kowal, chalapathi.v,
angeloj
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
On Thu, 2025-12-11 at 16:09 -0600, Caleb Schlossin wrote:
> - Add vmstate support for i2c registers
>
> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
> ---
> hw/ppc/pnv_i2c.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/hw/ppc/pnv_i2c.c b/hw/ppc/pnv_i2c.c
> index 60de479491..1018078228 100644
> --- a/hw/ppc/pnv_i2c.c
> +++ b/hw/ppc/pnv_i2c.c
> @@ -19,6 +19,7 @@
> #include "hw/ppc/pnv_i2c.h"
> #include "hw/ppc/pnv_xscom.h"
> #include "hw/ppc/fdt.h"
> +#include "migration/vmstate.h"
>
> #include <libfdt.h>
>
> @@ -549,6 +550,15 @@ static const Property pnv_i2c_properties[] = {
> DEFINE_PROP_UINT32("num-busses", PnvI2C, num_busses, 1),
> };
>
> +static const VMStateDescription pnv_i2c_vmstate = {
> + .name = TYPE_PNV_I2C,
> + .version_id = 1,
> + .fields = (const VMStateField[]) {
> + VMSTATE_UINT64_ARRAY(regs, PnvI2C, PNV_I2C_REGS),
> + VMSTATE_END_OF_LIST(),
> + },
> +};
> +
> static void pnv_i2c_class_init(ObjectClass *klass, const void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -561,6 +571,7 @@ static void pnv_i2c_class_init(ObjectClass *klass, const void *data)
>
> dc->desc = "PowerNV I2C";
> dc->realize = pnv_i2c_realize;
> + dc->vmsd = &pnv_i2c_vmstate;
> device_class_set_props(dc, pnv_i2c_properties);
> }
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 4/6] hw/ppc: pnv_adu.c added vmstate support
2025-12-11 22:09 [PATCH 0/6] hw/ppc: Snapshot support for several ppc devices Caleb Schlossin
` (2 preceding siblings ...)
2025-12-11 22:09 ` [PATCH 3/6] hw/ppc: Add pnv_i2c " Caleb Schlossin
@ 2025-12-11 22:09 ` Caleb Schlossin
2025-12-12 17:17 ` Miles Glenn
2025-12-11 22:09 ` [PATCH 5/6] hw/ppc: pnv_core.c add " Caleb Schlossin
` (2 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Caleb Schlossin @ 2025-12-11 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, npiggin, adityag, milesg, alistair, kowal, chalapathi.v,
calebs, angeloj
- Added vmstate support for ADU model
Signed-off-by: Angelo Jaramillo <angeloj@linux.ibm.com>
Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
---
hw/ppc/pnv_adu.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/hw/ppc/pnv_adu.c b/hw/ppc/pnv_adu.c
index 005fbda475..bd2a9e233a 100644
--- a/hw/ppc/pnv_adu.c
+++ b/hw/ppc/pnv_adu.c
@@ -23,6 +23,7 @@
#include "hw/ppc/pnv_chip.h"
#include "hw/ppc/pnv_lpc.h"
#include "hw/ppc/pnv_xscom.h"
+#include "migration/vmstate.h"
#include "trace.h"
#define ADU_LPC_BASE_REG 0x40
@@ -189,6 +190,16 @@ static const Property pnv_adu_properties[] = {
DEFINE_PROP_LINK("lpc", PnvADU, lpc, TYPE_PNV_LPC, PnvLpcController *),
};
+static const VMStateDescription pnv_adu_vmstate = {
+ .name = TYPE_PNV_ADU,
+ .version_id = 1,
+ .fields = (const VMStateField[]) {
+ VMSTATE_UINT64(lpc_cmd_reg, PnvADU),
+ VMSTATE_UINT64(lpc_data_reg, PnvADU),
+ VMSTATE_END_OF_LIST(),
+ },
+};
+
static void pnv_adu_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -197,6 +208,7 @@ static void pnv_adu_class_init(ObjectClass *klass, const void *data)
dc->desc = "PowerNV ADU";
device_class_set_props(dc, pnv_adu_properties);
dc->user_creatable = false;
+ dc->vmsd = &pnv_adu_vmstate;
}
static const TypeInfo pnv_adu_type_info = {
--
2.47.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 4/6] hw/ppc: pnv_adu.c added vmstate support
2025-12-11 22:09 ` [PATCH 4/6] hw/ppc: pnv_adu.c added " Caleb Schlossin
@ 2025-12-12 17:17 ` Miles Glenn
0 siblings, 0 replies; 16+ messages in thread
From: Miles Glenn @ 2025-12-12 17:17 UTC (permalink / raw)
To: Caleb Schlossin, qemu-devel
Cc: qemu-ppc, npiggin, adityag, alistair, kowal, chalapathi.v,
angeloj
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
On Thu, 2025-12-11 at 16:09 -0600, Caleb Schlossin wrote:
> - Added vmstate support for ADU model
>
> Signed-off-by: Angelo Jaramillo <angeloj@linux.ibm.com>
> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
> ---
> hw/ppc/pnv_adu.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/hw/ppc/pnv_adu.c b/hw/ppc/pnv_adu.c
> index 005fbda475..bd2a9e233a 100644
> --- a/hw/ppc/pnv_adu.c
> +++ b/hw/ppc/pnv_adu.c
> @@ -23,6 +23,7 @@
> #include "hw/ppc/pnv_chip.h"
> #include "hw/ppc/pnv_lpc.h"
> #include "hw/ppc/pnv_xscom.h"
> +#include "migration/vmstate.h"
> #include "trace.h"
>
> #define ADU_LPC_BASE_REG 0x40
> @@ -189,6 +190,16 @@ static const Property pnv_adu_properties[] = {
> DEFINE_PROP_LINK("lpc", PnvADU, lpc, TYPE_PNV_LPC, PnvLpcController *),
> };
>
> +static const VMStateDescription pnv_adu_vmstate = {
> + .name = TYPE_PNV_ADU,
> + .version_id = 1,
> + .fields = (const VMStateField[]) {
> + VMSTATE_UINT64(lpc_cmd_reg, PnvADU),
> + VMSTATE_UINT64(lpc_data_reg, PnvADU),
> + VMSTATE_END_OF_LIST(),
> + },
> +};
> +
> static void pnv_adu_class_init(ObjectClass *klass, const void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -197,6 +208,7 @@ static void pnv_adu_class_init(ObjectClass *klass, const void *data)
> dc->desc = "PowerNV ADU";
> device_class_set_props(dc, pnv_adu_properties);
> dc->user_creatable = false;
> + dc->vmsd = &pnv_adu_vmstate;
> }
>
> static const TypeInfo pnv_adu_type_info = {
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 5/6] hw/ppc: pnv_core.c add vmstate support
2025-12-11 22:09 [PATCH 0/6] hw/ppc: Snapshot support for several ppc devices Caleb Schlossin
` (3 preceding siblings ...)
2025-12-11 22:09 ` [PATCH 4/6] hw/ppc: pnv_adu.c added " Caleb Schlossin
@ 2025-12-11 22:09 ` Caleb Schlossin
2025-12-12 17:23 ` Miles Glenn
2025-12-11 22:09 ` [PATCH 6/6] hw/ppc: pnv_chiptod.c " Caleb Schlossin
2025-12-15 6:08 ` [PATCH 0/6] hw/ppc: Snapshot support for several ppc devices Aditya Gupta
6 siblings, 1 reply; 16+ messages in thread
From: Caleb Schlossin @ 2025-12-11 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, npiggin, adityag, milesg, alistair, kowal, chalapathi.v,
calebs, angeloj
- Removed VMSTATE for big_core, lpar_per_core, hwid, hrmor, and pir.
- Removed quad_id vmstate
Signed-off-by: Angelo Jaramillo <angeloj@linux.ibm.com>
Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
---
hw/ppc/pnv_core.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index fb2dfc7ba2..03b64f0013 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -31,6 +31,7 @@
#include "hw/ppc/xics.h"
#include "hw/qdev-properties.h"
#include "helper_regs.h"
+#include "migration/vmstate.h"
static const char *pnv_core_cpu_typename(PnvCore *pc)
{
@@ -478,6 +479,15 @@ static void pnv_core_power11_class_init(ObjectClass *oc, const void *data)
pnv_core_power10_class_init(oc, data);
}
+static const VMStateDescription pnv_core_vmstate = {
+ .name = TYPE_PNV_CORE,
+ .version_id = 1,
+ .fields = (const VMStateField[]) {
+ VMSTATE_UINT64_ARRAY(scratch, PnvCore, 8),
+ VMSTATE_END_OF_LIST(),
+ },
+};
+
static void pnv_core_class_init(ObjectClass *oc, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
@@ -486,6 +496,7 @@ static void pnv_core_class_init(ObjectClass *oc, const void *data)
dc->unrealize = pnv_core_unrealize;
device_class_set_props(dc, pnv_core_properties);
dc->user_creatable = false;
+ dc->vmsd = &pnv_core_vmstate;
}
#define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
@@ -737,12 +748,23 @@ static void pnv_quad_power11_class_init(ObjectClass *oc, const void *data)
pnv_quad_power10_class_init(oc, data);
}
+static const VMStateDescription pnv_quad_vmstate = {
+ .name = TYPE_PNV_QUAD,
+ .version_id = 1,
+ .fields = (const VMStateField[]) {
+ VMSTATE_BOOL(special_wakeup_done, PnvQuad),
+ VMSTATE_BOOL_ARRAY(special_wakeup, PnvQuad, 4),
+ VMSTATE_END_OF_LIST(),
+ },
+};
+
static void pnv_quad_class_init(ObjectClass *oc, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
device_class_set_props(dc, pnv_quad_properties);
dc->user_creatable = false;
+ dc->vmsd = &pnv_quad_vmstate;
}
static const TypeInfo pnv_quad_infos[] = {
--
2.47.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 5/6] hw/ppc: pnv_core.c add vmstate support
2025-12-11 22:09 ` [PATCH 5/6] hw/ppc: pnv_core.c add " Caleb Schlossin
@ 2025-12-12 17:23 ` Miles Glenn
2025-12-15 13:09 ` Caleb Schlossin
0 siblings, 1 reply; 16+ messages in thread
From: Miles Glenn @ 2025-12-12 17:23 UTC (permalink / raw)
To: Caleb Schlossin, qemu-devel
Cc: qemu-ppc, npiggin, adityag, alistair, kowal, chalapathi.v,
angeloj
On Thu, 2025-12-11 at 16:09 -0600, Caleb Schlossin wrote:
> - Removed VMSTATE for big_core, lpar_per_core, hwid, hrmor, and pir.
> - Removed quad_id vmstate
>
The commit title and description don't seem to match. This commit is
only adding vmstate and not removing anything.
-Glenn
> Signed-off-by: Angelo Jaramillo <angeloj@linux.ibm.com>
> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
> ---
> hw/ppc/pnv_core.c | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index fb2dfc7ba2..03b64f0013 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -31,6 +31,7 @@
> #include "hw/ppc/xics.h"
> #include "hw/qdev-properties.h"
> #include "helper_regs.h"
> +#include "migration/vmstate.h"
>
> static const char *pnv_core_cpu_typename(PnvCore *pc)
> {
> @@ -478,6 +479,15 @@ static void pnv_core_power11_class_init(ObjectClass *oc, const void *data)
> pnv_core_power10_class_init(oc, data);
> }
>
> +static const VMStateDescription pnv_core_vmstate = {
> + .name = TYPE_PNV_CORE,
> + .version_id = 1,
> + .fields = (const VMStateField[]) {
> + VMSTATE_UINT64_ARRAY(scratch, PnvCore, 8),
> + VMSTATE_END_OF_LIST(),
> + },
> +};
> +
> static void pnv_core_class_init(ObjectClass *oc, const void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> @@ -486,6 +496,7 @@ static void pnv_core_class_init(ObjectClass *oc, const void *data)
> dc->unrealize = pnv_core_unrealize;
> device_class_set_props(dc, pnv_core_properties);
> dc->user_creatable = false;
> + dc->vmsd = &pnv_core_vmstate;
> }
>
> #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
> @@ -737,12 +748,23 @@ static void pnv_quad_power11_class_init(ObjectClass *oc, const void *data)
> pnv_quad_power10_class_init(oc, data);
> }
>
> +static const VMStateDescription pnv_quad_vmstate = {
> + .name = TYPE_PNV_QUAD,
> + .version_id = 1,
> + .fields = (const VMStateField[]) {
> + VMSTATE_BOOL(special_wakeup_done, PnvQuad),
> + VMSTATE_BOOL_ARRAY(special_wakeup, PnvQuad, 4),
> + VMSTATE_END_OF_LIST(),
> + },
> +};
> +
> static void pnv_quad_class_init(ObjectClass *oc, const void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
>
> device_class_set_props(dc, pnv_quad_properties);
> dc->user_creatable = false;
> + dc->vmsd = &pnv_quad_vmstate;
> }
>
> static const TypeInfo pnv_quad_infos[] = {
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 5/6] hw/ppc: pnv_core.c add vmstate support
2025-12-12 17:23 ` Miles Glenn
@ 2025-12-15 13:09 ` Caleb Schlossin
0 siblings, 0 replies; 16+ messages in thread
From: Caleb Schlossin @ 2025-12-15 13:09 UTC (permalink / raw)
To: milesg, qemu-devel
Cc: qemu-ppc, npiggin, adityag, alistair, kowal, chalapathi.v,
angeloj
Good point, I'll fix the commit msg on the next set of patches.
- Caleb
On 12/12/25 11:23 AM, Miles Glenn wrote:
> On Thu, 2025-12-11 at 16:09 -0600, Caleb Schlossin wrote:
>> - Removed VMSTATE for big_core, lpar_per_core, hwid, hrmor, and pir.
>> - Removed quad_id vmstate
>>
>
> The commit title and description don't seem to match. This commit is
> only adding vmstate and not removing anything.
>
> -Glenn
>
>> Signed-off-by: Angelo Jaramillo <angeloj@linux.ibm.com>
>> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
>> ---
>> hw/ppc/pnv_core.c | 22 ++++++++++++++++++++++
>> 1 file changed, 22 insertions(+)
>>
>> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
>> index fb2dfc7ba2..03b64f0013 100644
>> --- a/hw/ppc/pnv_core.c
>> +++ b/hw/ppc/pnv_core.c
>> @@ -31,6 +31,7 @@
>> #include "hw/ppc/xics.h"
>> #include "hw/qdev-properties.h"
>> #include "helper_regs.h"
>> +#include "migration/vmstate.h"
>>
>> static const char *pnv_core_cpu_typename(PnvCore *pc)
>> {
>> @@ -478,6 +479,15 @@ static void pnv_core_power11_class_init(ObjectClass *oc, const void *data)
>> pnv_core_power10_class_init(oc, data);
>> }
>>
>> +static const VMStateDescription pnv_core_vmstate = {
>> + .name = TYPE_PNV_CORE,
>> + .version_id = 1,
>> + .fields = (const VMStateField[]) {
>> + VMSTATE_UINT64_ARRAY(scratch, PnvCore, 8),
>> + VMSTATE_END_OF_LIST(),
>> + },
>> +};
>> +
>> static void pnv_core_class_init(ObjectClass *oc, const void *data)
>> {
>> DeviceClass *dc = DEVICE_CLASS(oc);
>> @@ -486,6 +496,7 @@ static void pnv_core_class_init(ObjectClass *oc, const void *data)
>> dc->unrealize = pnv_core_unrealize;
>> device_class_set_props(dc, pnv_core_properties);
>> dc->user_creatable = false;
>> + dc->vmsd = &pnv_core_vmstate;
>> }
>>
>> #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
>> @@ -737,12 +748,23 @@ static void pnv_quad_power11_class_init(ObjectClass *oc, const void *data)
>> pnv_quad_power10_class_init(oc, data);
>> }
>>
>> +static const VMStateDescription pnv_quad_vmstate = {
>> + .name = TYPE_PNV_QUAD,
>> + .version_id = 1,
>> + .fields = (const VMStateField[]) {
>> + VMSTATE_BOOL(special_wakeup_done, PnvQuad),
>> + VMSTATE_BOOL_ARRAY(special_wakeup, PnvQuad, 4),
>> + VMSTATE_END_OF_LIST(),
>> + },
>> +};
>> +
>> static void pnv_quad_class_init(ObjectClass *oc, const void *data)
>> {
>> DeviceClass *dc = DEVICE_CLASS(oc);
>>
>> device_class_set_props(dc, pnv_quad_properties);
>> dc->user_creatable = false;
>> + dc->vmsd = &pnv_quad_vmstate;
>> }
>>
>> static const TypeInfo pnv_quad_infos[] = {
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 6/6] hw/ppc: pnv_chiptod.c add vmstate support
2025-12-11 22:09 [PATCH 0/6] hw/ppc: Snapshot support for several ppc devices Caleb Schlossin
` (4 preceding siblings ...)
2025-12-11 22:09 ` [PATCH 5/6] hw/ppc: pnv_core.c add " Caleb Schlossin
@ 2025-12-11 22:09 ` Caleb Schlossin
2025-12-12 17:28 ` Miles Glenn
2025-12-15 6:08 ` [PATCH 0/6] hw/ppc: Snapshot support for several ppc devices Aditya Gupta
6 siblings, 1 reply; 16+ messages in thread
From: Caleb Schlossin @ 2025-12-11 22:09 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-ppc, npiggin, adityag, milesg, alistair, kowal, chalapathi.v,
calebs, angeloj
- Added pre_save and post_load methods to handle slave_pc_target and tod_state
Signed-off-by: Angelo Jaramillo <angeloj@linux.ibm.com>
Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
---
hw/ppc/pnv_chiptod.c | 38 ++++++++++++++++++++++++++++++++++++
include/hw/ppc/pnv_chiptod.h | 2 ++
2 files changed, 40 insertions(+)
diff --git a/hw/ppc/pnv_chiptod.c b/hw/ppc/pnv_chiptod.c
index f887a18cde..9dc5942ca0 100644
--- a/hw/ppc/pnv_chiptod.c
+++ b/hw/ppc/pnv_chiptod.c
@@ -37,6 +37,7 @@
#include "hw/ppc/pnv_core.h"
#include "hw/ppc/pnv_xscom.h"
#include "hw/ppc/pnv_chiptod.h"
+#include "migration/vmstate.h"
#include "trace.h"
#include <libfdt.h>
@@ -341,6 +342,8 @@ static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr,
" TOD_TX_TTYPE_CTRL_REG val 0x%" PRIx64
" invalid slave address\n", val);
}
+ /* Write slave_pc_target to a uint64_t variable for vmstate support. */
+ chiptod->tx_ttype_ctrl = val;
break;
case TOD_ERROR_REG:
chiptod->tod_error &= ~val;
@@ -613,6 +616,40 @@ static void pnv_chiptod_unrealize(DeviceState *dev)
qemu_unregister_reset(pnv_chiptod_reset, chiptod);
}
+static int vmstate_pnv_chiptod_pre_save(void *opaque)
+{
+ PnvChipTOD *chiptod = PNV_CHIPTOD(opaque);
+ chiptod->tod_state_val = (uint8_t)chiptod->tod_state;
+ return 0;
+}
+
+static int vmstate_pnv_chiptod_post_load(void *opaque)
+{
+ PnvChipTOD *chiptod = PNV_CHIPTOD(opaque);
+ if (chiptod->tx_ttype_ctrl != 0) {
+ pnv_chiptod_xscom_write(chiptod, TOD_TX_TTYPE_CTRL_REG << 3,
+ chiptod->tx_ttype_ctrl, 8);
+ }
+ chiptod->tod_state = (enum tod_state)chiptod->tod_state_val;
+ return 0;
+}
+
+static const VMStateDescription pnv_chiptod_vmstate = {
+ .name = TYPE_PNV_CHIPTOD,
+ .version_id = 1,
+ .pre_save = vmstate_pnv_chiptod_pre_save,
+ .pre_load = vmstate_pnv_chiptod_post_load,
+ .fields = (const VMStateField[]) {
+ VMSTATE_BOOL(primary, PnvChipTOD),
+ VMSTATE_BOOL(secondary, PnvChipTOD),
+ VMSTATE_UINT64(tod_error, PnvChipTOD),
+ VMSTATE_UINT64(pss_mss_ctrl_reg, PnvChipTOD),
+ VMSTATE_UINT64(tx_ttype_ctrl, PnvChipTOD),
+ VMSTATE_UINT8(tod_state_val, PnvChipTOD),
+ VMSTATE_END_OF_LIST(),
+ },
+};
+
static void pnv_chiptod_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -621,6 +658,7 @@ static void pnv_chiptod_class_init(ObjectClass *klass, const void *data)
dc->unrealize = pnv_chiptod_unrealize;
dc->desc = "PowerNV ChipTOD Controller";
dc->user_creatable = false;
+ dc->vmsd = &pnv_chiptod_vmstate;
}
static const TypeInfo pnv_chiptod_type_info = {
diff --git a/include/hw/ppc/pnv_chiptod.h b/include/hw/ppc/pnv_chiptod.h
index 466b06560a..3e5e3b02b2 100644
--- a/include/hw/ppc/pnv_chiptod.h
+++ b/include/hw/ppc/pnv_chiptod.h
@@ -41,6 +41,8 @@ struct PnvChipTOD {
uint64_t tod_error;
uint64_t pss_mss_ctrl_reg;
PnvCore *slave_pc_target;
+ uint64_t tx_ttype_ctrl;
+ uint8_t tod_state_val;
};
struct PnvChipTODClass {
--
2.47.3
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH 6/6] hw/ppc: pnv_chiptod.c add vmstate support
2025-12-11 22:09 ` [PATCH 6/6] hw/ppc: pnv_chiptod.c " Caleb Schlossin
@ 2025-12-12 17:28 ` Miles Glenn
0 siblings, 0 replies; 16+ messages in thread
From: Miles Glenn @ 2025-12-12 17:28 UTC (permalink / raw)
To: Caleb Schlossin, qemu-devel
Cc: qemu-ppc, npiggin, adityag, alistair, kowal, chalapathi.v,
angeloj
Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
On Thu, 2025-12-11 at 16:09 -0600, Caleb Schlossin wrote:
> - Added pre_save and post_load methods to handle slave_pc_target and tod_state
>
> Signed-off-by: Angelo Jaramillo <angeloj@linux.ibm.com>
> Signed-off-by: Caleb Schlossin <calebs@linux.ibm.com>
> ---
> hw/ppc/pnv_chiptod.c | 38 ++++++++++++++++++++++++++++++++++++
> include/hw/ppc/pnv_chiptod.h | 2 ++
> 2 files changed, 40 insertions(+)
>
> diff --git a/hw/ppc/pnv_chiptod.c b/hw/ppc/pnv_chiptod.c
> index f887a18cde..9dc5942ca0 100644
> --- a/hw/ppc/pnv_chiptod.c
> +++ b/hw/ppc/pnv_chiptod.c
> @@ -37,6 +37,7 @@
> #include "hw/ppc/pnv_core.h"
> #include "hw/ppc/pnv_xscom.h"
> #include "hw/ppc/pnv_chiptod.h"
> +#include "migration/vmstate.h"
> #include "trace.h"
>
> #include <libfdt.h>
> @@ -341,6 +342,8 @@ static void pnv_chiptod_xscom_write(void *opaque, hwaddr addr,
> " TOD_TX_TTYPE_CTRL_REG val 0x%" PRIx64
> " invalid slave address\n", val);
> }
> + /* Write slave_pc_target to a uint64_t variable for vmstate support. */
> + chiptod->tx_ttype_ctrl = val;
> break;
> case TOD_ERROR_REG:
> chiptod->tod_error &= ~val;
> @@ -613,6 +616,40 @@ static void pnv_chiptod_unrealize(DeviceState *dev)
> qemu_unregister_reset(pnv_chiptod_reset, chiptod);
> }
>
> +static int vmstate_pnv_chiptod_pre_save(void *opaque)
> +{
> + PnvChipTOD *chiptod = PNV_CHIPTOD(opaque);
> + chiptod->tod_state_val = (uint8_t)chiptod->tod_state;
> + return 0;
> +}
> +
> +static int vmstate_pnv_chiptod_post_load(void *opaque)
> +{
> + PnvChipTOD *chiptod = PNV_CHIPTOD(opaque);
> + if (chiptod->tx_ttype_ctrl != 0) {
> + pnv_chiptod_xscom_write(chiptod, TOD_TX_TTYPE_CTRL_REG << 3,
> + chiptod->tx_ttype_ctrl, 8);
> + }
> + chiptod->tod_state = (enum tod_state)chiptod->tod_state_val;
> + return 0;
> +}
> +
> +static const VMStateDescription pnv_chiptod_vmstate = {
> + .name = TYPE_PNV_CHIPTOD,
> + .version_id = 1,
> + .pre_save = vmstate_pnv_chiptod_pre_save,
> + .pre_load = vmstate_pnv_chiptod_post_load,
> + .fields = (const VMStateField[]) {
> + VMSTATE_BOOL(primary, PnvChipTOD),
> + VMSTATE_BOOL(secondary, PnvChipTOD),
> + VMSTATE_UINT64(tod_error, PnvChipTOD),
> + VMSTATE_UINT64(pss_mss_ctrl_reg, PnvChipTOD),
> + VMSTATE_UINT64(tx_ttype_ctrl, PnvChipTOD),
> + VMSTATE_UINT8(tod_state_val, PnvChipTOD),
> + VMSTATE_END_OF_LIST(),
> + },
> +};
> +
> static void pnv_chiptod_class_init(ObjectClass *klass, const void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> @@ -621,6 +658,7 @@ static void pnv_chiptod_class_init(ObjectClass *klass, const void *data)
> dc->unrealize = pnv_chiptod_unrealize;
> dc->desc = "PowerNV ChipTOD Controller";
> dc->user_creatable = false;
> + dc->vmsd = &pnv_chiptod_vmstate;
> }
>
> static const TypeInfo pnv_chiptod_type_info = {
> diff --git a/include/hw/ppc/pnv_chiptod.h b/include/hw/ppc/pnv_chiptod.h
> index 466b06560a..3e5e3b02b2 100644
> --- a/include/hw/ppc/pnv_chiptod.h
> +++ b/include/hw/ppc/pnv_chiptod.h
> @@ -41,6 +41,8 @@ struct PnvChipTOD {
> uint64_t tod_error;
> uint64_t pss_mss_ctrl_reg;
> PnvCore *slave_pc_target;
> + uint64_t tx_ttype_ctrl;
> + uint8_t tod_state_val;
> };
>
> struct PnvChipTODClass {
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 0/6] hw/ppc: Snapshot support for several ppc devices
2025-12-11 22:09 [PATCH 0/6] hw/ppc: Snapshot support for several ppc devices Caleb Schlossin
` (5 preceding siblings ...)
2025-12-11 22:09 ` [PATCH 6/6] hw/ppc: pnv_chiptod.c " Caleb Schlossin
@ 2025-12-15 6:08 ` Aditya Gupta
2025-12-15 13:19 ` Caleb Schlossin
6 siblings, 1 reply; 16+ messages in thread
From: Aditya Gupta @ 2025-12-15 6:08 UTC (permalink / raw)
To: Caleb Schlossin
Cc: qemu-devel, qemu-ppc, npiggin, milesg, alistair, kowal,
chalapathi.v, angeloj
Hello Caleb,
On 25/12/11 04:09PM, Caleb Schlossin wrote:
> Add snapshot support for several ppc devices for the powernv machines.
>
> * Adding LPC, ADU, SPI, I2C, core, and chipTOD
>
> No specific ordering of the patches as this is ongoing development to
> support the PowerVM team. Additional patches for other (non-ppc) devices
> will be coming in separate patch submissions.
Thanks for the patches, can you tell more background on this ? Because
afaik PowerNV doesn't seem to have vmstate mostly, are these enough to
store/restore full PowerNV context ?
The patches look good overall, though I am yet to review in detail.
Some minor nits, LPC only sets vmstate for Power10's LPC, and many
devices vmstate don't have pre/post load handlers, assuming just the
vmstate info is enough in those cases ?
Thanks,
- Aditya G
>
> Thanks,
> Caleb
>
> Michael Kowal (1):
> hw/ppc: Add VMSTATE information for LPC model
>
> Caleb Schlossin (2):
> hw/ppc: Add pnv_spi vmstate support
> hw/ppc: Add pnv_i2c vmstate support
>
> Angelo Jaramillo (3):
> hw/ppc: pnv_adu.c added vmstate support
> hw/ppc: pnv_core.c add vmstate support
> hw/ppc: pnv_chiptod.c add vmstate support
>
>
> hw/ppc/pnv_adu.c | 12 +++++++++++
> hw/ppc/pnv_chiptod.c | 38 +++++++++++++++++++++++++++++++++++
> hw/ppc/pnv_core.c | 22 ++++++++++++++++++++
> hw/ppc/pnv_i2c.c | 11 ++++++++++
> hw/ppc/pnv_lpc.c | 39 ++++++++++++++++++++++++++++++++++++
> hw/ssi/pnv_spi.c | 27 +++++++++++++++++++++++++
> include/hw/ppc/pnv_chiptod.h | 2 ++
> 7 files changed, 151 insertions(+)
>
> --
> 2.47.3
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [PATCH 0/6] hw/ppc: Snapshot support for several ppc devices
2025-12-15 6:08 ` [PATCH 0/6] hw/ppc: Snapshot support for several ppc devices Aditya Gupta
@ 2025-12-15 13:19 ` Caleb Schlossin
0 siblings, 0 replies; 16+ messages in thread
From: Caleb Schlossin @ 2025-12-15 13:19 UTC (permalink / raw)
To: Aditya Gupta
Cc: qemu-devel, qemu-ppc, npiggin, milesg, alistair, kowal,
chalapathi.v, angeloj
Aditya,
My team has gotten snapshot support working with PowerNV and I'm now working on trying to upstream the smaller (less complicated) devices. Other, more complicated, support will be send upstream separately (PHB, XIVE, etc.).
Regarding LPC, all we had been focused on testing was Power10. If you'd like me to add support for Power8 and Power9, I can work on that in the next patch set.
- Caleb
On 12/15/25 12:08 AM, Aditya Gupta wrote:
> Hello Caleb,
>
> On 25/12/11 04:09PM, Caleb Schlossin wrote:
>> Add snapshot support for several ppc devices for the powernv machines.
>>
>> * Adding LPC, ADU, SPI, I2C, core, and chipTOD
>>
>> No specific ordering of the patches as this is ongoing development to
>> support the PowerVM team. Additional patches for other (non-ppc) devices
>> will be coming in separate patch submissions.
>
> Thanks for the patches, can you tell more background on this ? Because
> afaik PowerNV doesn't seem to have vmstate mostly, are these enough to
> store/restore full PowerNV context ?
>
> The patches look good overall, though I am yet to review in detail.
> Some minor nits, LPC only sets vmstate for Power10's LPC, and many
> devices vmstate don't have pre/post load handlers, assuming just the
> vmstate info is enough in those cases ?
>
> Thanks,
> - Aditya G
>
>>
>> Thanks,
>> Caleb
>>
>> Michael Kowal (1):
>> hw/ppc: Add VMSTATE information for LPC model
>>
>> Caleb Schlossin (2):
>> hw/ppc: Add pnv_spi vmstate support
>> hw/ppc: Add pnv_i2c vmstate support
>>
>> Angelo Jaramillo (3):
>> hw/ppc: pnv_adu.c added vmstate support
>> hw/ppc: pnv_core.c add vmstate support
>> hw/ppc: pnv_chiptod.c add vmstate support
>>
>>
>> hw/ppc/pnv_adu.c | 12 +++++++++++
>> hw/ppc/pnv_chiptod.c | 38 +++++++++++++++++++++++++++++++++++
>> hw/ppc/pnv_core.c | 22 ++++++++++++++++++++
>> hw/ppc/pnv_i2c.c | 11 ++++++++++
>> hw/ppc/pnv_lpc.c | 39 ++++++++++++++++++++++++++++++++++++
>> hw/ssi/pnv_spi.c | 27 +++++++++++++++++++++++++
>> include/hw/ppc/pnv_chiptod.h | 2 ++
>> 7 files changed, 151 insertions(+)
>>
>> --
>> 2.47.3
>>
^ permalink raw reply [flat|nested] 16+ messages in thread