From: Dave Jiang <dave.jiang@intel.com>
To: wangyuquan <wangyuquan1236@phytium.com.cn>,
jonathan.cameron@huawei.com, fan.ni@samsung.com, mst@redhat.com,
marcel.apfelbaum@gmail.com
Cc: qemu-devel@nongnu.org, linux-cxl@vger.kernel.org
Subject: Re: [RFC PATCH v3 0/2] cxl: Support creation of a new CXL Host Bridge
Date: Fri, 25 Jul 2025 09:32:41 -0700 [thread overview]
Message-ID: <86a015d5-7b49-4b23-8a26-2155871bd08e@intel.com> (raw)
In-Reply-To: <20250617040649.81303-1-wangyuquan1236@phytium.com.cn>
On 6/16/25 9:06 PM, wangyuquan wrote:
> v2 -> v3:
> - Update the commit message
> - Fix some alignment and space problems
> - Add a SPDX header for the new file
> - Remove unnecessary comments
> - Add CXL_HOST_BRIDGE config
> v1 -> v2:
> - Move the code of new bridge to hw/pci-host/cxl.c
> - Fix and simplify some logic on handling the different bridge types
Hi Yuquan, can you please add qemu to your patch subject prefix in the future? i.e. [QEMU PATCH v4 0/2]. It would help the maintainers on linux-cxl to know they are not kernel patches. Thank you!
>
> Background
> ==========
> Currently the base CXL support for arm platforms is only on Jonathan's
> patches[1]. Some platform like SBSA-REF can be more like a real machine,
> thus the support of CXL could be meaningful. However, the pxb-cxl-host
> realization on this platform seems not satisfying their requirements[2].
>
> New CXL HOST design
> ===================
> Defines a new CXL host bridge type (TYPE_CXL_HOST). This is an
> independent CXL host bridge which combined GPEX features (ECAM, MMIO
> windows and irq) and CXL Host Bridge Component Registers (CHBCR).
>
> The root bus path of CXL_HOST is "0001:00", that would not affect the
> original pcie host topology. In the previous, the pxb-cxl-host with
> any CXL root ports and CXL endpoint devices would occupy the BDF
> number of the original pcie domain. This new type provide a solution
> to resolve the problem.
>
> Remaining problems
> ==================
> I tried to use 'object_resolve_path' but it could not work in
> 'cxl_fmws_link_targets', so I used 'TYPE_DEVICE' to match that.
>
> Link:
> [1]: https://lore.kernel.org/linux-cxl/20220616141950.23374-1-Jonathan.Cameron@huawei.com/
> [2]: https://lists.nongnu.org/archive/html/qemu-arm/2024-11/msg00522.html
>
> Yuquan Wang (2):
> pci-host/cxl: Support creation of a new CXL Host Bridge
> hw/pxb-cxl: Rename the pxb cxl host bridge
>
> hw/cxl/cxl-host-stubs.c | 3 +
> hw/cxl/cxl-host.c | 64 ++++++++---
> hw/pci-bridge/pci_expander_bridge.c | 8 +-
> hw/pci-host/Kconfig | 4 +
> hw/pci-host/cxl.c | 152 ++++++++++++++++++++++++++
> hw/pci-host/meson.build | 1 +
> include/hw/cxl/cxl.h | 7 +-
> include/hw/cxl/cxl_host.h | 3 +
> include/hw/pci-host/cxl_host_bridge.h | 23 ++++
> 9 files changed, 244 insertions(+), 21 deletions(-)
> create mode 100644 hw/pci-host/cxl.c
> create mode 100644 include/hw/pci-host/cxl_host_bridge.h
>
prev parent reply other threads:[~2025-07-25 16:36 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-17 4:06 [RFC PATCH v3 0/2] cxl: Support creation of a new CXL Host Bridge wangyuquan
2025-06-17 4:06 ` [RFC PATCH v3 1/2] hw/pxb-cxl: Rename the pxb cxl host bridge wangyuquan
2025-07-25 15:16 ` Jonathan Cameron via
2025-06-17 4:06 ` [RFC PATCH v3 2/2] pci-host/cxl: Support creation of a new CXL Host Bridge wangyuquan
2025-07-25 15:40 ` Jonathan Cameron via
2025-07-25 16:32 ` Dave Jiang [this message]
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