From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [PULL v2 00/14] target-arm queue
Date: Thu, 6 Jul 2023 18:19:24 +0100 [thread overview]
Message-ID: <86bb5275-3e56-9b25-d75c-b9d8509447bf@linaro.org> (raw)
In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org>
On 7/6/23 14:24, Peter Maydell wrote:
> Changes v1->v2 (fixing CI failures in v1, added a couple of
> extra patches in an attempt to avoid having to do a last
> minute arm pullreq next week):
> * new patch to hopefully fix the build issue with the SVE/SME sysregs test
> * dropped the IC IVAU test case patch
> * new patch: fix over-length shift
> * new patches: define neoverse-v1
>
> thanks
> -- PMM
>
> The following changes since commit 2a6ae69154542caa91dd17c40fd3f5ffbec300de:
>
> Merge tag 'pull-maintainer-ominbus-030723-1' ofhttps://gitlab.com/stsquad/qemu into staging (2023-07-04 08:36:44 +0200)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230706
>
> for you to fetch changes up to c41077235168140cdd4a34fce9bd95c3d30efe9c:
>
> target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case (2023-07-06 13:36:51 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * Add raw_writes ops for register whose write induce TLB maintenance
> * hw/arm/sbsa-ref: use XHCI to replace EHCI
> * Avoid splitting Zregs across lines in dump
> * Dump ZA[] when active
> * Fix SME full tile indexing
> * Handle IC IVAU to improve compatibility with JITs
> * xlnx-canfd-test: Fix code coverity issues
> * gdbstub: Guard M-profile code with CONFIG_TCG
> * allwinner-sramc: Set class_size
> * target/xtensa: Assert that interrupt level is within bounds
> * Avoid over-length shift in arm_cpu_sve_finalize() error case
> * Define new 'neoverse-v1' CPU type
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate.
r~
prev parent reply other threads:[~2023-07-06 17:19 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-06 13:24 [PULL v2 00/14] target-arm queue Peter Maydell
2023-07-06 13:24 ` [PULL 01/14] target/arm: Add raw_writes ops for register whose write induce TLB maintenance Peter Maydell
2023-07-06 13:25 ` [PULL 02/14] hw/arm/sbsa-ref: use XHCI to replace EHCI Peter Maydell
2023-07-06 13:25 ` [PULL 03/14] tests/tcg/aarch64/sysregs.c: Use S syntax for id_aa64zfr0_el1 and id_aa64smfr0_el1 Peter Maydell
2023-07-06 13:25 ` [PULL 04/14] target/arm: Avoid splitting Zregs across lines in dump Peter Maydell
2023-07-06 13:25 ` [PULL 05/14] target/arm: Dump ZA[] when active Peter Maydell
2023-07-06 13:25 ` [PULL 06/14] target/arm: Fix SME full tile indexing Peter Maydell
2023-07-06 13:25 ` [PULL 07/14] target/arm: Handle IC IVAU to improve compatibility with JITs Peter Maydell
2023-07-06 13:25 ` [PULL 08/14] tests/qtest: xlnx-canfd-test: Fix code coverity issues Peter Maydell
2023-07-06 13:25 ` [PULL 09/14] target/arm: gdbstub: Guard M-profile code with CONFIG_TCG Peter Maydell
2023-07-06 13:25 ` [PULL 10/14] hw: arm: allwinner-sramc: Set class_size Peter Maydell
2023-07-06 13:25 ` [PULL 11/14] target/xtensa: Assert that interrupt level is within bounds Peter Maydell
2023-07-06 13:25 ` [PULL 12/14] target/arm: Suppress more TCG unimplemented features in ID registers Peter Maydell
2023-07-06 13:25 ` [PULL 13/14] target/arm: Define neoverse-v1 Peter Maydell
2023-07-06 13:25 ` [PULL 14/14] target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case Peter Maydell
2023-07-06 17:19 ` Richard Henderson [this message]
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