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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PULL v2 00/14] target-arm queue Content-Language: en-US To: Peter Maydell , qemu-devel@nongnu.org References: <20230706132512.3534397-1-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20230706132512.3534397-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::92e; envelope-from=richard.henderson@linaro.org; helo=mail-ua1-x92e.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.091, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 7/6/23 14:24, Peter Maydell wrote: > Changes v1->v2 (fixing CI failures in v1, added a couple of > extra patches in an attempt to avoid having to do a last > minute arm pullreq next week): > * new patch to hopefully fix the build issue with the SVE/SME sysregs test > * dropped the IC IVAU test case patch > * new patch: fix over-length shift > * new patches: define neoverse-v1 > > thanks > -- PMM > > The following changes since commit 2a6ae69154542caa91dd17c40fd3f5ffbec300de: > > Merge tag 'pull-maintainer-ominbus-030723-1' ofhttps://gitlab.com/stsquad/qemu into staging (2023-07-04 08:36:44 +0200) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230706 > > for you to fetch changes up to c41077235168140cdd4a34fce9bd95c3d30efe9c: > > target/arm: Avoid over-length shift in arm_cpu_sve_finalize() error case (2023-07-06 13:36:51 +0100) > > ---------------------------------------------------------------- > target-arm queue: > * Add raw_writes ops for register whose write induce TLB maintenance > * hw/arm/sbsa-ref: use XHCI to replace EHCI > * Avoid splitting Zregs across lines in dump > * Dump ZA[] when active > * Fix SME full tile indexing > * Handle IC IVAU to improve compatibility with JITs > * xlnx-canfd-test: Fix code coverity issues > * gdbstub: Guard M-profile code with CONFIG_TCG > * allwinner-sramc: Set class_size > * target/xtensa: Assert that interrupt level is within bounds > * Avoid over-length shift in arm_cpu_sve_finalize() error case > * Define new 'neoverse-v1' CPU type Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate. r~