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In-Reply-To: <20130508150412.GB31148@hall.aurel32.net> (Aurelien Jarno's
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Subject: Re: [Qemu-devel] [PATCH] PPC: Depend behavior of cmp instructions
	only on instruction encoding
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To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org

Aurelien Jarno <aurelien@aurel32.net> writes:

  As it seems you have good contact with IBM, could you please ask them
  to fix their manuals?
=20=20
What flaw have your found?

  At least Freescale CPUs match what IBM documentation says.

Which ones?  Freescale 7447 and Freescale e500 disagree.  (Or at least
some versions of these chips, perhaps newer e500 steppings ignore the L
bit.)

  IBM CPUs don't.
=20=20
Which ones?

  No it's not correct, it doesn't match neither Freescale nor IBM
  behaviour. It also means the same code executed on a 32-bit emulated CPU
  run with qemu-system-ppc will behave differently than when run with
  qemu-system-ppc64. This is fine for now as we are in freeze period, but
  should be fixed afterwards.
=20=20
I think one should check if it is a 64-bit CPU vs 32-bit CPU, as your
patch did.  (If I read it correctly; while I am an expert in the area, I
am very little familiar with qemu's innards.)  Except that it should
probably not cast an exception (but I think either way there is no
calamity).

--=20
Torbj=C3=B6rn