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[90.26.70.43]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42b35ad7c16sm9848860f8f.15.2025.11.10.07.02.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Nov 2025 07:02:27 -0800 (PST) Message-ID: <86f568ff-edb8-4920-bd51-fc86e0637094@linaro.org> Date: Mon, 10 Nov 2025 16:02:26 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 06/13] hw/arm/fsl-imx8mm: Add GPIO controllers Content-Language: en-US To: Gaurav Sharma , qemu-devel@nongnu.org Cc: pbonzini@redhat.com, peter.maydell@linaro.org References: <20251110112257.184578-1-gaurav.sharma_7@nxp.com> <20251110112257.184578-7-gaurav.sharma_7@nxp.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20251110112257.184578-7-gaurav.sharma_7@nxp.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/11/25 12:22, Gaurav Sharma wrote: > Enabled GPIO controller emulation > Also updated the GPIO IRQ lines of iMX8MM > > Signed-off-by: Gaurav Sharma > --- > docs/system/arm/imx8mm-evk.rst | 1 + > hw/arm/fsl-imx8mm.c | 54 ++++++++++++++++++++++++++++++++++ > include/hw/arm/fsl-imx8mm.h | 14 +++++++++ > 3 files changed, 69 insertions(+) > diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c > index ea5799b2cc..222d3bac1c 100644 > --- a/hw/arm/fsl-imx8mm.c > +++ b/hw/arm/fsl-imx8mm.c > @@ -177,6 +177,11 @@ static void fsl_imx8mm_init(Object *obj) > object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); > } > > + for (i = 0; i < FSL_IMX8MM_NUM_GPIOS; i++) { > + g_autofree char *name = g_strdup_printf("gpio%d", i + 1); > + object_initialize_child(obj, name, &s->gpio[i], TYPE_IMX_GPIO); > + } > + > for (i = 0; i < FSL_IMX8MM_NUM_USDHCS; i++) { > g_autofree char *name = g_strdup_printf("usdhc%d", i + 1); > object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); > @@ -350,6 +355,54 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error **errp) > qdev_get_gpio_in(gicdev, serial_table[i].irq)); > } > > + /* GPIOs */ > + for (i = 0; i < FSL_IMX8MM_NUM_GPIOS; i++) { static const? > + struct { > + hwaddr addr; > + unsigned int irq_low; > + unsigned int irq_high; > + } gpio_table[FSL_IMX8MM_NUM_GPIOS] = { > + { > + fsl_imx8mm_memmap[FSL_IMX8MM_GPIO1].addr, > + FSL_IMX8MM_GPIO1_LOW_IRQ, > + FSL_IMX8MM_GPIO1_HIGH_IRQ > + }, > + { > + fsl_imx8mm_memmap[FSL_IMX8MM_GPIO2].addr, > + FSL_IMX8MM_GPIO2_LOW_IRQ, > + FSL_IMX8MM_GPIO2_HIGH_IRQ > + }, > + { > + fsl_imx8mm_memmap[FSL_IMX8MM_GPIO3].addr, > + FSL_IMX8MM_GPIO3_LOW_IRQ, > + FSL_IMX8MM_GPIO3_HIGH_IRQ > + }, > + { > + fsl_imx8mm_memmap[FSL_IMX8MM_GPIO4].addr, > + FSL_IMX8MM_GPIO4_LOW_IRQ, > + FSL_IMX8MM_GPIO4_HIGH_IRQ > + }, > + { > + fsl_imx8mm_memmap[FSL_IMX8MM_GPIO5].addr, > + FSL_IMX8MM_GPIO5_LOW_IRQ, > + FSL_IMX8MM_GPIO5_HIGH_IRQ > + }, > + }; > + object_property_set_bool(OBJECT(&s->gpio[i]), "has-edge-sel", true, > + &error_abort); > + object_property_set_bool(OBJECT(&s->gpio[i]), "has-upper-pin-irq", > + true, &error_abort); > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) { > + return; > + } > + > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0, > + qdev_get_gpio_in(gicdev, gpio_table[i].irq_low)); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1, > + qdev_get_gpio_in(gicdev, gpio_table[i].irq_high)); > + } Reviewed-by: Philippe Mathieu-Daudé