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Thu, 15 May 2025 16:15:15 +0000 (GMT) Message-ID: <86fec34079e7fc3b6c16afa276cc9f3df96d19b7.camel@linux.ibm.com> Subject: Re: [PATCH 47/50] ppc/xive2: Implement POOL LGS push TIMA op From: Miles Glenn To: Nicholas Piggin , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, =?ISO-8859-1?Q?Fr=E9d=E9ric?= Barrat , Michael Kowal , Caleb Schlossin Date: Thu, 15 May 2025 11:15:14 -0500 In-Reply-To: <20250512031100.439842-48-npiggin@gmail.com> References: <20250512031100.439842-1-npiggin@gmail.com> <20250512031100.439842-48-npiggin@gmail.com> Organization: IBM Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-27.el8_10) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: pVDJH722tF4OSLxkZq8LUNNpBnlbynnf X-Authority-Analysis: v=2.4 cv=ecg9f6EH c=1 sm=1 tr=0 ts=68261316 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=VnNF1IyMAAAA:8 a=pGLkceISAAAA:8 a=s_r7pROeAOtUuJ4LlHUA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: sWj9nOHGWMhpG8DCtRFHwOr91UzppYgY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTE1MDE2MCBTYWx0ZWRfXzu/achqSD7cV qpRNW0QwOLuTUDDenTYUDVLLQcNjXu/4J1NvTL6O2HV8MLYkTkedvDlptyfZpqlwD4OSxpNcldr v1JE8erSEcpaql6zkYnujvdHU+7SWooZD23GuW5nEURKjWRle0kzMOXsaEy8gonrPK+dZOLRBOC zsmwngIvc1gxo9MAEe8a0nAhzYF8rZK7QofyWGGMSjjZ29wgfh7DXqY6SzhNZqZrD9TaOJgR4Ct LQd2DPgXCHtLu/QdaL2ISAjBkakIBArnLc3S3IR2h+eTYH5zhgvCWhNzel6FeQaf2hIHbG/8f9t xu8WFotPc5tftG6/Pl+O13l0VSDZYDw+X9t4Gn1xo5n3aNb2G0sWZyWaMsiEbuYOF8LIvJiYmyP Jcj0XQvhJi6Afeu/Um59xOSPpnw+vfp3ARUHiYU7PjUGHr+dzRLEQHePu8n2Vfm89y3fdwUn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-15_07,2025-05-15_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 impostorscore=0 spamscore=0 clxscore=1015 malwarescore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 suspectscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505070000 definitions=main-2505150160 Received-SPF: pass client-ip=148.163.158.5; envelope-from=milesg@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: milesg@linux.ibm.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Reviewed-by: Glenn Miles On Mon, 2025-05-12 at 13:10 +1000, Nicholas Piggin wrote: > Implement set LGS for the POOL ring. > > Signed-off-by: Nicholas Piggin > --- > hw/intc/xive.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index dc64edf13d..807a1c1c34 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -532,6 +532,12 @@ static void xive_tm_set_os_lgs(XivePresenter *xptr, XiveTCTX *tctx, > xive_tctx_set_lgs(tctx, TM_QW1_OS, value & 0xff); > } > > +static void xive_tm_set_pool_lgs(XivePresenter *xptr, XiveTCTX *tctx, > + hwaddr offset, uint64_t value, unsigned size) > +{ > + xive_tctx_set_lgs(tctx, TM_QW2_HV_POOL, value & 0xff); > +} > + > /* > * Adjust the PIPR to allow a CPU to process event queues of other > * priorities during one physical interrupt cycle. > @@ -737,6 +743,8 @@ static const XiveTmOp xive2_tm_operations[] = { > xive2_tm_push_pool_ctx, NULL }, > { XIVE_TM_HV_PAGE, TM_QW2_HV_POOL + TM_WORD2, 8, true, true, > xive2_tm_push_pool_ctx, NULL }, > + { XIVE_TM_HV_PAGE, TM_QW2_HV_POOL + TM_LGS, 1, true, true, > + xive_tm_set_pool_lgs, NULL }, > { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, true, true, > xive2_tm_set_hv_cppr, NULL }, > { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, true, true,