From: WANG Xuerui <i.qemu@xen0n.name>
To: Xiaojuan Yang <yangxiaojuan@loongson.cn>, qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, thuth@redhat.com, mst@redhat.com,
david@gibson.dropbear.id.au, mark.cave-ayland@ilande.co.uk,
richard.henderson@linaro.org, laurent@vivier.eu,
peterx@redhat.com, f4bug@amsat.org, alex.bennee@linaro.org,
alistair.francis@wdc.com, maobibo@loongson.cn,
gaosong@loongson.cn, pbonzini@redhat.com, bmeng.cn@gmail.com,
philmd@redhat.com, chenhuacai@loongson.cn
Subject: Re: [PATCH 00/31] Add Loongarch softmmu support.
Date: Tue, 19 Oct 2021 22:52:08 +0800 [thread overview]
Message-ID: <871839b9-c0eb-c6f0-47b6-bd045884e622@xen0n.name> (raw)
In-Reply-To: <1634628917-10031-1-git-send-email-yangxiaojuan@loongson.cn>
Hi Xiaojuan,
On 10/19/21 15:34, Xiaojuan Yang wrote:
> This series patch add softmmu support for LoongArch.
> Base on the linux-user emulation support V7 patch.
>
> The latest kernel:
> * https://github.com/loongson/linux/tree/loongarch-next
> The manual:
> * https://github.com/loongson/LoongArch-Documentation/releases/tag/2021.10.11
>
> Patch 1 Add a readme for code download and supply binary for test.
> Patch 2-3 define CSR registers and set the init/reset value.
> Patch 4-5 Add cpu related functions.
> Patch 6-12 Add Privileged instruction simulation used by LoongArch.
> Patch 13 Emulate a virt pci host based on the LoongArch 7A1000.
> Patch 14 Emulate a virt 3a5000 board different from host.
> Patch 15-20 Emulate the interrupt controller used by the virt board.
> Patch 21-22 Add devices used by the board.
> Patch 23-25 Add bios and smbios support needed for the start.
> Patch 26 Add a simple acpi model.
> Patch 27 Enable mttcg mode.
> Patch 28-29 Support for numa more than 4 cpus.
> Patch 30-31 Add some functions for debug.
>
> Xiaojuan Yang (31):
> target/loongarch: Upate the README for the softmmu.
Nit: "Update", also remove the trailing period -- QEMU style doesn't
mandate full sentences for title line of commit messages AFAIK. Other
places should be fixed as well.
> target/loongarch: Add CSR registers definition
> target/loongarch: Set default csr values.
> target/loongarch: Add basic vmstate description of CPU.
> target/loongarch: Implement qmp_query_cpu_definitions()
> target/loongarch: Add mmu support for Loongarch CPU.
> target/loongarch: Add loongarch csr/iocsr instruction support
And please use consistent casing for "LoongArch", "CSR", "IOCSR", "MMU",
"TLB" etc etc -- again fix everywhere you can.
> target/loongarch: Add tlb instruction support
> target/loongarch: Add other core instructions support
> target/loongarch: Add loongarch interrupt and exception handle
> target/loongarch: Add stabletimer support
> target/loongarch: Add timer related instructions support.
> hw/pci-host: Add ls7a1000 PCIe Host bridge support for Loongson
> Platform
> hw/loongarch: Add a virt loongarch 3A5000 board support
> hw/loongarch: Add loongarch cpu interrupt support(CPUINTC)
> hw/loongarch: Add loongarch ipi interrupt support(IPI)
> hw/intc: Add loongarch ls7a interrupt controller support(PCH-PIC)
> hw/intc: Add loongarch ls7a msi interrupt controller support(PCH-MSI)
> hw/intc: Add loongarch extioi interrupt controller(EIOINTC)
> hw/loongarch: Add irq hierarchy for the system
> hw/loongarch: Add some devices support for 3A5000.
> hw/loongarch: Add loongarch ls7a rtc device support
> hw/loongarch: Add default bios startup support.
> hw/loongarch: Add -kernel and -initrd options support
> hw/loongarch: Add loongarch smbios support
> hw/loongarch: Add loongarch acpi support
> hw/loongarch: Add mttcg mode support
> hw/loongarch: use machine->possible_cpus for storing possible topology
> info
> hw/loongarch: Add numa support.
> target/loongarch: Add gdb support.
> target/loongarch: Add privilege instructions diassembly
>
> .../devices/loongarch64-softmmu/default.mak | 3 +
> configs/targets/loongarch64-softmmu.mak | 4 +
> disas/loongarch.c | 173 ++++
> gdb-xml/loongarch-base64.xml | 43 +
> gdb-xml/loongarch-fpu64.xml | 57 ++
> hw/Kconfig | 1 +
> hw/acpi/Kconfig | 4 +
> hw/acpi/ls7a.c | 351 +++++++
> hw/acpi/meson.build | 1 +
> hw/intc/Kconfig | 12 +
> hw/intc/loongarch_extioi.c | 589 +++++++++++
> hw/intc/loongarch_pch_msi.c | 74 ++
> hw/intc/loongarch_pch_pic.c | 284 ++++++
> hw/intc/meson.build | 3 +
> hw/loongarch/Kconfig | 22 +
> hw/loongarch/acpi-build.c | 661 +++++++++++++
> hw/loongarch/fw_cfg.c | 34 +
> hw/loongarch/fw_cfg.h | 16 +
> hw/loongarch/ipi.c | 147 +++
> hw/loongarch/loongarch_int.c | 62 ++
> hw/loongarch/ls3a5000_virt.c | 638 ++++++++++++
> hw/loongarch/meson.build | 7 +
> hw/meson.build | 1 +
> hw/pci-host/Kconfig | 4 +
> hw/pci-host/ls7a.c | 224 +++++
> hw/pci-host/meson.build | 1 +
> hw/rtc/Kconfig | 3 +
> hw/rtc/ls7a_rtc.c | 327 +++++++
> hw/rtc/meson.build | 1 +
> include/exec/poison.h | 2 +
> include/hw/acpi/ls7a.h | 54 ++
> include/hw/intc/loongarch_extioi.h | 102 ++
> include/hw/intc/loongarch_pch_msi.h | 17 +
> include/hw/intc/loongarch_pch_pic.h | 50 +
> include/hw/loongarch/gipi.h | 38 +
> include/hw/loongarch/loongarch.h | 79 ++
> include/hw/pci-host/ls7a.h | 67 ++
> include/sysemu/arch_init.h | 1 +
> linux-user/loongarch64/cpu_loop.c | 3 +-
> pc-bios/loongarch_bios.bin | Bin 0 -> 4128768 bytes
> qapi/machine-target.json | 6 +-
> qapi/machine.json | 2 +-
> softmmu/qdev-monitor.c | 3 +-
> target/Kconfig | 1 +
> target/loongarch/Kconfig | 2 +
> target/loongarch/README | 134 +++
> target/loongarch/cpu-csr.h | 493 ++++++++++
> target/loongarch/cpu.c | 448 ++++++++-
> target/loongarch/cpu.h | 56 +-
> target/loongarch/csr_helper.c | 765 +++++++++++++++
> target/loongarch/gdbstub.c | 95 ++
> target/loongarch/helper.h | 24 +
> target/loongarch/insn_trans/trans_core.c | 302 ++++++
> target/loongarch/insn_trans/trans_extra.c | 2 +
> target/loongarch/insns.decode | 45 +
> target/loongarch/internals.h | 93 ++
> target/loongarch/machine.c | 253 +++++
> target/loongarch/meson.build | 10 +
> target/loongarch/op_helper.c | 77 +-
> target/loongarch/ramdisk | Bin 0 -> 3077952 bytes
> target/loongarch/stabletimer.c | 71 ++
> target/loongarch/tlb_helper.c | 918 ++++++++++++++++++
> target/loongarch/translate.c | 8 +-
> target/loongarch/vmlinux | Bin 0 -> 24565536 bytes
Well, it might not be exactly nice to add ~30MiB of blob right here, via
mailing list? IIUC everyone here can only see 17 of your 31 patches,
maybe the blob-containing mail and subsequent ones all got blocked?
And perhaps it's not okay to put blobs inside target/ in the first
place, a quick `tree` look at main branch reveals no such file. You may
host these blobs (better yet, properly open-sourced repos) elsewhere and
link to them in README instead.
> 64 files changed, 7955 insertions(+), 13 deletions(-)
> create mode 100644 configs/devices/loongarch64-softmmu/default.mak
> create mode 100644 configs/targets/loongarch64-softmmu.mak
> create mode 100644 gdb-xml/loongarch-base64.xml
> create mode 100644 gdb-xml/loongarch-fpu64.xml
> create mode 100644 hw/acpi/ls7a.c
> create mode 100644 hw/intc/loongarch_extioi.c
> create mode 100644 hw/intc/loongarch_pch_msi.c
> create mode 100644 hw/intc/loongarch_pch_pic.c
> create mode 100644 hw/loongarch/Kconfig
> create mode 100644 hw/loongarch/acpi-build.c
> create mode 100644 hw/loongarch/fw_cfg.c
> create mode 100644 hw/loongarch/fw_cfg.h
> create mode 100644 hw/loongarch/ipi.c
> create mode 100644 hw/loongarch/loongarch_int.c
> create mode 100644 hw/loongarch/ls3a5000_virt.c
> create mode 100644 hw/loongarch/meson.build
> create mode 100644 hw/pci-host/ls7a.c
> create mode 100644 hw/rtc/ls7a_rtc.c
While I haven't seen the entirety of the series, these files got created
but MAINTAINERS is not updated. Please update the corresponding entries.
> create mode 100644 include/hw/acpi/ls7a.h
> create mode 100644 include/hw/intc/loongarch_extioi.h
> create mode 100644 include/hw/intc/loongarch_pch_msi.h
> create mode 100644 include/hw/intc/loongarch_pch_pic.h
> create mode 100644 include/hw/loongarch/gipi.h
> create mode 100644 include/hw/loongarch/loongarch.h
> create mode 100644 include/hw/pci-host/ls7a.h
> create mode 100644 pc-bios/loongarch_bios.bin
> create mode 100644 target/loongarch/Kconfig
> create mode 100644 target/loongarch/cpu-csr.h
> create mode 100644 target/loongarch/csr_helper.c
> create mode 100644 target/loongarch/gdbstub.c
> create mode 100644 target/loongarch/insn_trans/trans_core.c
> create mode 100644 target/loongarch/machine.c
> create mode 100644 target/loongarch/ramdisk
> create mode 100644 target/loongarch/stabletimer.c
> create mode 100644 target/loongarch/tlb_helper.c
> create mode 100755 target/loongarch/vmlinux
>
next prev parent reply other threads:[~2021-10-19 16:25 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-19 7:34 [PATCH 00/31] Add Loongarch softmmu support Xiaojuan Yang
2021-10-19 7:34 ` [PATCH 02/31] target/loongarch: Add CSR registers definition Xiaojuan Yang
2021-10-19 19:10 ` Richard Henderson
2021-10-19 7:34 ` [PATCH 03/31] target/loongarch: Set default csr values Xiaojuan Yang
2021-10-19 19:18 ` Richard Henderson
2021-10-19 7:34 ` [PATCH 04/31] target/loongarch: Add basic vmstate description of CPU Xiaojuan Yang
2021-10-19 19:35 ` Richard Henderson
2021-10-19 7:34 ` [PATCH 05/31] target/loongarch: Implement qmp_query_cpu_definitions() Xiaojuan Yang
2021-10-19 20:25 ` Richard Henderson
2021-10-19 7:34 ` [PATCH 08/31] target/loongarch: Add tlb instruction support Xiaojuan Yang
2021-10-20 4:19 ` Richard Henderson
2021-10-29 7:01 ` yangxiaojuan
2021-10-29 17:48 ` Richard Henderson
2021-10-19 7:34 ` [PATCH 09/31] target/loongarch: Add other core instructions support Xiaojuan Yang
2021-10-20 4:45 ` Richard Henderson
2021-10-19 7:34 ` [PATCH 10/31] target/loongarch: Add loongarch interrupt and exception handle Xiaojuan Yang
2021-10-20 4:59 ` Richard Henderson
2021-10-19 7:34 ` [PATCH 11/31] target/loongarch: Add stabletimer support Xiaojuan Yang
2021-10-19 7:34 ` [PATCH 12/31] target/loongarch: Add timer related instructions support Xiaojuan Yang
2021-10-20 5:17 ` Richard Henderson
2021-10-19 7:34 ` [PATCH 13/31] hw/pci-host: Add ls7a1000 PCIe Host bridge support for Loongson Platform Xiaojuan Yang
2021-10-19 7:35 ` [PATCH 14/31] hw/loongarch: Add a virt loongarch 3A5000 board support Xiaojuan Yang
2021-10-19 7:35 ` [PATCH 15/31] hw/loongarch: Add loongarch cpu interrupt support(CPUINTC) Xiaojuan Yang
2021-10-19 7:35 ` [PATCH 16/31] hw/loongarch: Add loongarch ipi interrupt support(IPI) Xiaojuan Yang
2021-10-19 7:35 ` [PATCH 17/31] hw/intc: Add loongarch ls7a interrupt controller support(PCH-PIC) Xiaojuan Yang
2021-10-19 7:35 ` [PATCH 18/31] hw/intc: Add loongarch ls7a msi interrupt controller support(PCH-MSI) Xiaojuan Yang
2021-10-19 7:35 ` [PATCH 19/31] hw/intc: Add loongarch extioi interrupt controller(EIOINTC) Xiaojuan Yang
2021-10-19 7:35 ` [PATCH 20/31] hw/loongarch: Add irq hierarchy for the system Xiaojuan Yang
2021-10-19 14:52 ` WANG Xuerui [this message]
[not found] ` <7d933f8d.228e.17c9b556e98.Coremail.yangxiaojuan@loongson.cn>
2021-10-20 5:11 ` [PATCH 00/31] Add Loongarch softmmu support WANG Xuerui
[not found] ` <1634628917-10031-24-git-send-email-yangxiaojuan@loongson.cn>
2021-10-19 16:19 ` [PATCH 23/31] hw/loongarch: Add default bios startup support Michael S. Tsirkin
[not found] ` <1634628917-10031-2-git-send-email-yangxiaojuan@loongson.cn>
2021-10-19 18:56 ` [PATCH 01/31] target/loongarch: Upate the README for the softmmu Richard Henderson
2021-10-22 2:25 ` yangxiaojuan
[not found] ` <1634628917-10031-7-git-send-email-yangxiaojuan@loongson.cn>
2021-10-19 21:11 ` [PATCH 06/31] target/loongarch: Add mmu support for Loongarch CPU Richard Henderson
[not found] ` <1634628917-10031-8-git-send-email-yangxiaojuan@loongson.cn>
2021-10-20 1:36 ` [PATCH 07/31] target/loongarch: Add loongarch csr/iocsr instruction support Richard Henderson
2021-10-29 6:26 ` yangxiaojuan
2021-10-29 17:38 ` Richard Henderson
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