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Wed, 11 Oct 2023 16:34:11 +0100 (BST) References: <20231011070335.14398-1-akihiko.odaki@daynix.com> <20231011070335.14398-2-akihiko.odaki@daynix.com> User-agent: mu4e 1.11.22; emacs 29.1.50 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Akihiko Odaki Cc: Mikhail Tyutin , Aleksandr Anenkov , qemu-devel@nongnu.org, Philippe =?utf-8?Q?Mathieu-?= =?utf-8?Q?Daud=C3=A9?= , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "open list:RISC-V TCG CPUs" Subject: Re: [PATCH v9 01/23] target/riscv: Move MISA limits to class Date: Wed, 11 Oct 2023 16:23:15 +0100 In-reply-to: <20231011070335.14398-2-akihiko.odaki@daynix.com> Message-ID: <871qe1p40c.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Akihiko Odaki writes: > MISA limits are common for all instances of a RISC-V CPU class so they > are better put into class. > > Signed-off-by: Akihiko Odaki > --- > target/riscv/cpu-qom.h | 2 + > target/riscv/cpu.h | 2 - > hw/riscv/boot.c | 2 +- > target/riscv/cpu.c | 212 +++++++++++++++++++++++++++------------ > target/riscv/csr.c | 3 +- > target/riscv/gdbstub.c | 12 ++- > target/riscv/machine.c | 11 +- > target/riscv/translate.c | 3 +- > 8 files changed, 167 insertions(+), 80 deletions(-) > > diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h > index 04af50983e..266a07f5be 100644 > --- a/target/riscv/cpu-qom.h > +++ b/target/riscv/cpu-qom.h > @@ -67,5 +67,7 @@ struct RISCVCPUClass { > /*< public >*/ > DeviceRealize parent_realize; > ResettablePhases parent_phases; > + uint32_t misa_mxl_max; /* max mxl for this cpu */ > + uint32_t misa_ext_mask; /* max ext for this cpu */ > }; > #endif /* RISCV_CPU_QOM_H */ > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index ef9cf21c0c..9f9cb6cd2a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -155,9 +155,7 @@ struct CPUArchState { >=20=20 > /* RISCVMXL, but uint32_t for vmstate migration */ > uint32_t misa_mxl; /* current mxl */ > - uint32_t misa_mxl_max; /* max mxl for this cpu */ > uint32_t misa_ext; /* current extensions */ > - uint32_t misa_ext_mask; /* max ext for this cpu */ > uint32_t xl; /* current xlen */ >=20=20 > /* 128-bit helpers upper part return value */ > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 52bf8e67de..b7cf08f479 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -36,7 +36,7 @@ >=20=20 > bool riscv_is_32bit(RISCVHartArrayState *harts) > { > - return harts->harts[0].env.misa_mxl_max =3D=3D MXL_RV32; > + return RISCV_CPU_GET_CLASS(&harts->harts[0])->misa_mxl_max =3D=3D > MXL_RV32; I'm going to defer to the RISCV maintainers here. While I agree the class is a good place for these parameters that are shared across multiple vCPUS there is a cost to RISCV_CPU_GET_CLASS() casting. You might notice we have this comment in include/hw/core/cpu.h: /* * The class checkers bring in CPU_GET_CLASS() which is potentially * expensive given the eventual call to * object_class_dynamic_cast_assert(). Because of this the CPUState * has a cached value for the class in cs->cc which is set up in * cpu_exec_realizefn() for use in hot code paths. */ typedef struct CPUClass CPUClass; DECLARE_CLASS_CHECKERS(CPUClass, CPU, TYPE_CPU) However I think you need to check the assumption that you will never see multiple cores with different RISCV properties. --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro