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Fri, 16 Sep 2022 16:34:33 +0100 (BST) References: <20220914160955.812151-1-alex.bennee@linaro.org> <20220914160955.812151-4-alex.bennee@linaro.org> <6aebb38e-551e-e241-bda7-4b748e672c29@amsat.org> User-agent: mu4e 1.9.0; emacs 28.1.91 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: Richard Henderson , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Peter Maydell Subject: Re: [RFC PATCH 3/4] hw/intc/gic: use MxTxAttrs to divine accessing CPU Date: Fri, 16 Sep 2022 16:28:14 +0100 In-reply-to: <6aebb38e-551e-e241-bda7-4b748e672c29@amsat.org> Message-ID: <871qsb8h9y.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Philippe Mathieu-Daud=C3=A9 writes: > On 15/9/22 10:16, Richard Henderson wrote: >> On 9/14/22 17:09, Alex Benn=C3=A9e wrote: >>> Now that MxTxAttrs encodes a CPU we should use that to figure it out. >>> This solves edge cases like accessing via gdbstub or qtest. >>> >>> Signed-off-by: Alex Benn=C3=A9e >>> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/124 >>> --- >>> =C2=A0 hw/intc/arm_gic.c | 39 ++++++++++++++++++++++----------------- >>> =C2=A0 1 file changed, 22 insertions(+), 17 deletions(-) >>> >>> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c >>> index 492b2421ab..7feedac735 100644 >>> --- a/hw/intc/arm_gic.c >>> +++ b/hw/intc/arm_gic.c >>> @@ -56,17 +56,22 @@ static const uint8_t gic_id_gicv2[] =3D { >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0x04, 0x00, 0x00, 0x00, 0x90, 0xb4, 0x2b= , 0x00, 0x0d, 0xf0, >>> 0x05, 0xb1 >>> =C2=A0 }; >>> -static inline int gic_get_current_cpu(GICState *s) >>> +static inline int gic_get_current_cpu(GICState *s, MemTxAttrs attrs) >>> =C2=A0 { >>> -=C2=A0=C2=A0=C2=A0 if (!qtest_enabled() && s->num_cpu > 1) { >>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return current_cpu->cpu_ind= ex; >>> -=C2=A0=C2=A0=C2=A0 } >>> -=C2=A0=C2=A0=C2=A0 return 0; >>> +=C2=A0=C2=A0=C2=A0 /* >>> +=C2=A0=C2=A0=C2=A0=C2=A0 * Something other than a CPU accessing the GI= C would be a bug as >>> +=C2=A0=C2=A0=C2=A0=C2=A0 * would a CPU index higher than the GICState = expects to be >>> +=C2=A0=C2=A0=C2=A0=C2=A0 * handling >>> +=C2=A0=C2=A0=C2=A0=C2=A0 */ >>> +=C2=A0=C2=A0=C2=A0 g_assert(attrs.requester_cpu =3D=3D 1); >> Better without "=3D=3D 1" -- this field ought to be boolean. > > Boolean so far, but this could get more types (such DMA...). > Maybe we could already add an enum definitions, i.e.: > > typedef enum MemTxRequesterType { > MEMTXATTRS_CPU, > MEMTXATTRS_MSI, > } MemTxRequesterType; > > and name the field MemTxAttrs::requester_type. I pondered boolean but wasn't sure if that would blow up the size of MemTxAttrs so went for the bitfield. However I can certainly rename to requester_is_cpu and make a boolean assertion. I'd hold off adding an enum until we actually have more than two requester types. --=20 Alex Benn=C3=A9e