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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Peter  Maydell" , qemu-devel , Philippe =?utf-8?Q?Mathieu-Daud?= =?utf-8?Q?=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" casmac writes: > Hello ,=20 > >   thanks for the hints. I modified one parameter of  memory_reg= ion_init_ram() call ,and the slow-path problem disappeared.=20 > >   What I did is , change the RAM size from the exact memory size nee= ded to hold the object file section(s), to the size that TI C3X user manual= memory mapping specifies.=20 > >   The former size is significantly smaller. But I did not specify th= e memory mapping else where in the program, so still unsure about the cause= of conflict.=20 > Well you should be modelling the system - not what is actually loaded. > >     One intresting fact is that this somehow depends on th= e linker > > command file. The object file generated by the following linker comm= and > > file(per_instr.lds) > > will "trigger" the problem. But QEMU work well with the object file > > linked by the other linker command file (ok.lds). > >     What cause get_page_addr_code_hostp() function to retu= rn -1? I have > > no clue at all. Any advise is appreciated!! > > Maybe the "execute from small-MMU-region RAM" problem? > > See: > https://www.mail-archive.com/qemu-devel@nongnu.org/msg549660.html That is the change that introduced the ability to do this. On some SoCs you often run small amounts of boot code from device memory (or on-chip chache) while the main system memory is setup. Usually it's not a large amount of code so doing it one instruction at a time isn't a massive burden. You have to do it this way because the underlying instruction may change each time you read that memory. In normal system RAM we have architectural hints such as flushing events which eventually end up as tlb-flush events that ensure code is re-translated when needed. --=20 Alex Benn=C3=A9e