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From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
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Date: Wed, 07 Feb 2018 15:17:40 +0000
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Subject: Re: [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3,
 SM3, SM4 and SHA-512 instruction support
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>, QEMU Developers <qemu-devel@nongnu.org>


Peter Maydell <peter.maydell@linaro.org> writes:

> On 7 February 2018 at 14:57, Alex Benn=C3=A9e <alex.bennee@linaro.org> wr=
ote:
>>
>> Ard Biesheuvel <ard.biesheuvel@linaro.org> writes:
>>
>>> Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instruction=
s to
>>> AArch64 user mode emulation.
>>
>> So another problem I've come across is I can't turn this off. I ended up
>> doing that in my FP16 series because otherwise existing RISU tests get
>> broken. However having an optional flag for each little set of
>> instructions seems overkill.
>
> Why do the existing tests break? Are they checking UNDEF
> for previously-reserved bits of the encoding space?

Yeah. Maybe the easiest solution is to find the undefs and re-generate
everything.

>
>> Have you run any RISU tests? If you want you can add this to the
>> aarch64.risu to generate some test patterns.
>
> I wrote some risu patterns for testing these. I was going
> to send the patch out tomorrow...
>
> (I used the tag A64_C82 rather than A64_V.)

Ohh that is a useful use for that tag...

>
> thanks
> -- PMM


--
Alex Benn=C3=A9e