From: "Alex Bennée" <alex.bennee@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org, peter.maydell@linaro.org
Subject: Re: [Qemu-devel] [PATCH v11 01/20] tcg: Allow multiple word entries into the constant pool
Date: Tue, 06 Feb 2018 08:51:24 +0000 [thread overview]
Message-ID: <871shyxzzn.fsf@linaro.org> (raw)
In-Reply-To: <20180126045742.5487-2-richard.henderson@linaro.org>
Richard Henderson <richard.henderson@linaro.org> writes:
> This will be required for storing vector constants.
>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> tcg/tcg-pool.inc.c | 115 +++++++++++++++++++++++++++++++++++++++++++----------
> 1 file changed, 93 insertions(+), 22 deletions(-)
>
> diff --git a/tcg/tcg-pool.inc.c b/tcg/tcg-pool.inc.c
> index 8a85131405..ecf7c9282b 100644
> --- a/tcg/tcg-pool.inc.c
> +++ b/tcg/tcg-pool.inc.c
> @@ -22,39 +22,110 @@
>
> typedef struct TCGLabelPoolData {
> struct TCGLabelPoolData *next;
> - tcg_target_ulong data;
> tcg_insn_unit *label;
> - intptr_t addend;
> - int type;
> + int32_t addend;
> + uint16_t rtype;
> + uint16_t nlong;
> + tcg_target_ulong data[];
> } TCGLabelPoolData;
>
>
> -static void new_pool_label(TCGContext *s, tcg_target_ulong data, int type,
> - tcg_insn_unit *label, intptr_t addend)
> +static TCGLabelPoolData *new_pool_alloc(TCGContext *s, int nlong, int rtype,
> + tcg_insn_unit *label, int addend)
> {
> - TCGLabelPoolData *n = tcg_malloc(sizeof(*n));
> - TCGLabelPoolData *i, **pp;
> + TCGLabelPoolData *n = tcg_malloc(sizeof(TCGLabelPoolData)
> + + sizeof(tcg_target_ulong) * nlong);
>
> - n->data = data;
> n->label = label;
> - n->type = type;
> n->addend = addend;
> + n->rtype = rtype;
> + n->nlong = nlong;
> + return n;
> +}
> +
> +static void new_pool_insert(TCGContext *s, TCGLabelPoolData *n)
> +{
> + TCGLabelPoolData *i, **pp;
> + int nlong = n->nlong;
>
> /* Insertion sort on the pool. */
> - for (pp = &s->pool_labels; (i = *pp) && i->data < data; pp = &i->next) {
> - continue;
> + for (pp = &s->pool_labels; (i = *pp) != NULL; pp = &i->next) {
> + if (nlong > i->nlong) {
> + break;
> + }
> + if (nlong < i->nlong) {
> + continue;
> + }
> + if (memcmp(n->data, i->data, sizeof(tcg_target_ulong) * nlong) >= 0) {
> + break;
> + }
> }
> n->next = *pp;
> *pp = n;
> }
>
> +/* The "usual" for generic integer code. */
> +static inline void new_pool_label(TCGContext *s, tcg_target_ulong d, int rtype,
> + tcg_insn_unit *label, int addend)
> +{
> + TCGLabelPoolData *n = new_pool_alloc(s, 1, rtype, label, addend);
> + n->data[0] = d;
> + new_pool_insert(s, n);
> +}
> +
> +/* For v64 or v128, depending on the host. */
> +static inline void new_pool_l2(TCGContext *s, int rtype, tcg_insn_unit *label,
> + int addend, tcg_target_ulong d0,
> + tcg_target_ulong d1)
> +{
> + TCGLabelPoolData *n = new_pool_alloc(s, 2, rtype, label, addend);
> + n->data[0] = d0;
> + n->data[1] = d1;
> + new_pool_insert(s, n);
> +}
> +
> +/* For v128 or v256, depending on the host. */
> +static inline void new_pool_l4(TCGContext *s, int rtype, tcg_insn_unit *label,
> + int addend, tcg_target_ulong d0,
> + tcg_target_ulong d1, tcg_target_ulong d2,
> + tcg_target_ulong d3)
> +{
> + TCGLabelPoolData *n = new_pool_alloc(s, 4, rtype, label, addend);
> + n->data[0] = d0;
> + n->data[1] = d1;
> + n->data[2] = d2;
> + n->data[3] = d3;
> + new_pool_insert(s, n);
> +}
> +
> +/* For v256, for 32-bit host. */
> +static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label,
> + int addend, tcg_target_ulong d0,
> + tcg_target_ulong d1, tcg_target_ulong d2,
> + tcg_target_ulong d3, tcg_target_ulong d4,
> + tcg_target_ulong d5, tcg_target_ulong d6,
> + tcg_target_ulong d7)
> +{
> + TCGLabelPoolData *n = new_pool_alloc(s, 8, rtype, label, addend);
> + n->data[0] = d0;
> + n->data[1] = d1;
> + n->data[2] = d2;
> + n->data[3] = d3;
> + n->data[4] = d4;
> + n->data[5] = d5;
> + n->data[6] = d6;
> + n->data[7] = d7;
> + new_pool_insert(s, n);
> +}
> +
> /* To be provided by cpu/tcg-target.inc.c. */
> static void tcg_out_nop_fill(tcg_insn_unit *p, int count);
>
> static bool tcg_out_pool_finalize(TCGContext *s)
> {
> TCGLabelPoolData *p = s->pool_labels;
> - tcg_target_ulong d, *a;
> + TCGLabelPoolData *l = NULL;
> + void *a;
>
> if (p == NULL) {
> return true;
> @@ -62,24 +133,24 @@ static bool tcg_out_pool_finalize(TCGContext *s)
>
> /* ??? Round up to qemu_icache_linesize, but then do not round
> again when allocating the next TranslationBlock structure. */
> - a = (void *)ROUND_UP((uintptr_t)s->code_ptr, sizeof(tcg_target_ulong));
> + a = (void *)ROUND_UP((uintptr_t)s->code_ptr,
> + sizeof(tcg_target_ulong) * p->nlong);
> tcg_out_nop_fill(s->code_ptr, (tcg_insn_unit *)a - s->code_ptr);
> s->data_gen_ptr = a;
>
> - /* Ensure the first comparison fails. */
> - d = p->data + 1;
> -
> for (; p != NULL; p = p->next) {
> - if (p->data != d) {
> - d = p->data;
> - if (unlikely((void *)a > s->code_gen_highwater)) {
> + size_t size = sizeof(tcg_target_ulong) * p->nlong;
> + if (!l || l->nlong != p->nlong || memcmp(l->data, p->data, size)) {
> + if (unlikely(a > s->code_gen_highwater)) {
> return false;
> }
> - *a++ = d;
> + memcpy(a, p->data, size);
> + a += size;
> + l = p;
> }
> - patch_reloc(p->label, p->type, (intptr_t)(a - 1), p->addend);
> + patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend);
> }
>
> - s->code_ptr = (void *)a;
> + s->code_ptr = a;
> return true;
> }
--
Alex Bennée
next prev parent reply other threads:[~2018-02-06 8:51 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-26 4:57 [Qemu-devel] [PATCH v11 00/20] tcg: generic vector operations Richard Henderson
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 01/20] tcg: Allow multiple word entries into the constant pool Richard Henderson
2018-02-06 8:51 ` Alex Bennée [this message]
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 02/20] tcg: Add types and basic operations for host vectors Richard Henderson
2018-02-06 8:53 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 03/20] tcg: Standardize integral arguments to expanders Richard Henderson
2018-02-06 8:57 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 04/20] tcg: Add generic vector expanders Richard Henderson
2018-02-06 10:59 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 05/20] tcg: Add generic vector ops for constant shifts Richard Henderson
2018-02-06 11:00 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 06/20] tcg: Add generic vector ops for comparisons Richard Henderson
2018-02-06 11:01 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 07/20] tcg: Add generic vector ops for multiplication Richard Henderson
2018-02-06 11:02 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 08/20] tcg: Add generic helpers for saturating arithmetic Richard Henderson
2018-02-06 11:03 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 09/20] tcg: Add generic vector helpers with a scalar operand Richard Henderson
2018-02-06 11:04 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 10/20] tcg/optimize: Handle vector opcodes during optimize Richard Henderson
2018-02-06 11:07 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 11/20] target/arm: Align vector registers Richard Henderson
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 12/20] target/arm: Use vector infrastructure for aa64 add/sub/logic Richard Henderson
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 13/20] target/arm: Use vector infrastructure for aa64 mov/not/neg Richard Henderson
2018-02-06 11:08 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 14/20] target/arm: Use vector infrastructure for aa64 dup/movi Richard Henderson
2018-02-06 11:09 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 15/20] target/arm: Use vector infrastructure for aa64 constant shifts Richard Henderson
2018-02-05 11:14 ` Peter Maydell
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 16/20] target/arm: Use vector infrastructure for aa64 compares Richard Henderson
2018-02-06 11:10 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 17/20] target/arm: Use vector infrastructure for aa64 multiplies Richard Henderson
2018-02-06 11:11 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 18/20] target/arm: Use vector infrastructure for aa64 orr/bic immediate Richard Henderson
2018-02-06 11:13 ` Alex Bennée
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 19/20] tcg/i386: Add vector operations Richard Henderson
2018-01-26 4:57 ` [Qemu-devel] [PATCH v11 20/20] tcg/aarch64: " Richard Henderson
2018-02-06 11:15 ` Alex Bennée
2018-01-26 17:25 ` [Qemu-devel] [PATCH v11 00/20] tcg: generic " no-reply
2018-02-06 11:24 ` Alex Bennée
2018-02-06 12:07 ` Philippe Mathieu-Daudé
2018-02-06 12:36 ` Alex Bennée
2018-02-06 16:24 ` Alex Bennée
2018-02-06 20:57 ` Alex Bennée
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