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From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
In-reply-to: <30d66407-ad33-bc8c-55c6-0a5d7009bed4@twiddle.net>
Date: Fri, 28 Apr 2017 08:47:05 +0100
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Subject: Re: [Qemu-devel] [PATCH v5 03/19] qemu/atomic: Loosen restrictions
 for 64-bit ILP32 hosts
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To: Richard Henderson <rth@twiddle.net>
Cc: qemu-devel@nongnu.org, cota@braap.org


Richard Henderson <rth@twiddle.net> writes:

> On 04/27/2017 06:10 PM, Alex Bennée wrote:
>>
>> Richard Henderson <rth@twiddle.net> writes:
>>
>>> We need to coordinate with the TCG_OVERSIZED_GUEST test in cputlb.c,
>>> and allow 64-bit atomics even though sizeof(void *) == 4.
>>
>> Hmm you say this here but we never actually do it. But the other changes
>> seem fine.
>
> I don't understand this comment.
>
>>> +#if defined(__x86_64__) || defined(__sparc__)
>>> +# define ATOMIC_REG_SIZE  8
>>> +#else
>>> +# define ATOMIC_REG_SIZE  sizeof(void *)
>>> +#endif
>
> How does this "never actually do it"?

I meant this is independent of the definition of TCG_OVERSIZED_GUEST:

#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
#define TCG_OVERSIZED_GUEST 1
#else
#define TCG_OVERSIZED_GUEST 0
#endif

So maybe the comment should be clearer for ATOMIC_REG_SIZE that it
should match TCG_TARGET_REG_BITS (and therefore sync with
TCG_OVERSIZED_GUEST) in the atomic.h comment.

--
Alex Bennée