Re: [Qemu-devel] [PATCH v4 2/3] target-arm: Rename check_s2_startlevel to check_s2_mmu_setup

["Alex Bennée" <alex.bennee@linaro.org>]

Edgar E. Iglesias <edgar.iglesias@gmail.com> writes:

> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Rename check_s2_startlevel to check_s2_mmu_setup in preparation
> for additional checks.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> ---
>  target-arm/helper.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 5d6f297..13e9933 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -6763,17 +6763,18 @@ typedef enum {
>  } MMUFaultType;
>
>  /*
> - * check_s2_startlevel
> + * check_s2_mmu_setup
>   * @cpu:        ARMCPU
>   * @is_aa64:    True if the translation regime is in AArch64 state
>   * @startlevel: Suggested starting level
>   * @inputsize:  Bitsize of IPAs
>   * @stride:     Page-table stride (See the ARM ARM)
>   *
> - * Returns true if the suggested starting level is OK and false otherwise.
> + * Returns true if the suggested S2 translation parameters are OK and
> + * false otherwise.
>   */
> -static bool check_s2_startlevel(ARMCPU *cpu, bool is_aa64, int level,
> -                                int inputsize, int stride)
> +static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
> +                               int inputsize, int stride)
>  {
>      const int grainsize = stride + 3;
>      int startsizecheck;
> @@ -7013,8 +7014,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
>          }
>
>          /* Check that the starting level is valid. */
> -        ok = check_s2_startlevel(cpu, va_size == 64, level,
> -                                 inputsize, stride);
> +        ok = check_s2_mmu_setup(cpu, va_size == 64, level, inputsize, stride);
>          if (!ok) {
>              /* AArch64 reports these as level 0 faults.
>               * AArch32 reports these as level 1 faults.


--
Alex Bennée