Any interest in the QEMU community attending DVCon Europe October 2024?

Any interest in the QEMU community attending DVCon Europe October 2024?

[Alex Bennée]

Hi,

Over recent years there has been a push to make QEMU more flexible for
EDA type applications. As long time developers know there are a number
of downstream forks of QEMU which have their own solutions for modelling
heterogeneous systems and integrating with hardware models. The work by
Philippe, Anton and others to build a single binary with composable
hardware is aiming at least to solve the heterogeneous modelling problem
in the upstream project.

While we do discuss these "TCG" topics during KVM Forum the project may
benefit from doing some outreach at some conferences where simulation
and emulation are the primary focus.

The Design and Verification Conference & Exhibition Europe (DVCon
Europe) is the premier European technical conference on system,
software, design, verification, validation and integration. This year it
will be on the 15-16 October 2024 in Munich. See: https://dvcon-europe.org/

There have been a number of papers and workshops on QEMU/KVM topics over
the years. Unfortunately the website doesn't provide slides or videos of
the talks but topics have included how QEMU can be used as a fast
instruction simulator alongside things such as SystemC models or
virtualisation can be leveraged to accelerate full system emulation.

The main tracks are fairly academic where engineering and research
papers are submitted and if accepted can then be presented at the
conference. This is probably over the top for QEMU related stuff but
their is a tutorial track (deadline for Abstracts 1st July) which could
be a good target for a introduction to the features and capabilities of
the QEMU upstream. I suspect there would be interest in the wider
modelling community to find out more about how to use the upstream
project directly.

There is a co-located "SystemC Evolution Day" on the 17th where there
might well be a strong overlap between SystemC users and QEMU. Mark
Burton is involved with that and is keen for proposals talking about
integrating SystemC models with QEMU. Please send a message to
mburton@quicinc.com if you're interested.

So is anyone interested?

Should we do more within the community to network and discuss our plans
for QEMU as a modelling solution?

Any other thoughts?

-- 
Alex Bennée
Virtualisation Tech Lead @ Linaro

Re: Any interest in the QEMU community attending DVCon Europe October 2024?

[Alex Bennée]

Alex Bennée <alex.bennee@linaro.org> writes:

> Hi,
>
> Over recent years there has been a push to make QEMU more flexible for
> EDA type applications. As long time developers know there are a number
> of downstream forks of QEMU which have their own solutions for modelling
> heterogeneous systems and integrating with hardware models. The work by
> Philippe, Anton and others to build a single binary with composable
> hardware is aiming at least to solve the heterogeneous modelling problem
> in the upstream project.
>
> While we do discuss these "TCG" topics during KVM Forum the project may
> benefit from doing some outreach at some conferences where simulation
> and emulation are the primary focus.
>
> The Design and Verification Conference & Exhibition Europe (DVCon
> Europe) is the premier European technical conference on system,
> software, design, verification, validation and integration. This year it
> will be on the 15-16 October 2024 in Munich. See: https://dvcon-europe.org/
>
> There have been a number of papers and workshops on QEMU/KVM topics over
> the years. Unfortunately the website doesn't provide slides or videos of
> the talks but topics have included how QEMU can be used as a fast
> instruction simulator alongside things such as SystemC models or
> virtualisation can be leveraged to accelerate full system emulation.
>
> The main tracks are fairly academic where engineering and research
> papers are submitted and if accepted can then be presented at the
> conference. This is probably over the top for QEMU related stuff but
> their is a tutorial track (deadline for Abstracts 1st July) which could
> be a good target for a introduction to the features and capabilities of
> the QEMU upstream. I suspect there would be interest in the wider
> modelling community to find out more about how to use the upstream
> project directly.
>
> There is a co-located "SystemC Evolution Day" on the 17th where there
> might well be a strong overlap between SystemC users and QEMU. Mark
> Burton is involved with that and is keen for proposals talking about
> integrating SystemC models with QEMU. Please send a message to
> mburton@quicinc.com if you're interested.
>
> So is anyone interested?
>
> Should we do more within the community to network and discuss our plans
> for QEMU as a modelling solution?
>
> Any other thoughts?

Gentle ping, any interest?

-- 
Alex Bennée
Virtualisation Tech Lead @ Linaro

Re: Any interest in the QEMU community attending DVCon Europe October 2024?

[ff]

> Le 5 mars 2024 à 16:50, Alex Bennée <alex.bennee@linaro.org> a écrit :
> 
> 
> Hi,
> 
> Over recent years there has been a push to make QEMU more flexible for
> EDA type applications. As long time developers know there are a number
> of downstream forks of QEMU which have their own solutions for modelling
> heterogeneous systems and integrating with hardware models. The work by
> Philippe, Anton and others to build a single binary with composable
> hardware is aiming at least to solve the heterogeneous modelling problem
> in the upstream project.
> 
> While we do discuss these "TCG" topics during KVM Forum the project may
> benefit from doing some outreach at some conferences where simulation
> and emulation are the primary focus.
> 
> The Design and Verification Conference & Exhibition Europe (DVCon
> Europe) is the premier European technical conference on system,
> software, design, verification, validation and integration. This year it
> will be on the 15-16 October 2024 in Munich. See: https://dvcon-europe.org/
> 
> There have been a number of papers and workshops on QEMU/KVM topics over
> the years. Unfortunately the website doesn't provide slides or videos of
> the talks but topics have included how QEMU can be used as a fast
> instruction simulator alongside things such as SystemC models or
> virtualisation can be leveraged to accelerate full system emulation.
> 
> The main tracks are fairly academic where engineering and research
> papers are submitted and if accepted can then be presented at the
> conference. This is probably over the top for QEMU related stuff but
> their is a tutorial track (deadline for Abstracts 1st July) which could
> be a good target for a introduction to the features and capabilities of
> the QEMU upstream. I suspect there would be interest in the wider
> modelling community to find out more about how to use the upstream
> project directly.
> 
> There is a co-located "SystemC Evolution Day" on the 17th where there
> might well be a strong overlap between SystemC users and QEMU. Mark
> Burton is involved with that and is keen for proposals talking about
> integrating SystemC models with QEMU. Please send a message to
> mburton@quicinc.com if you're interested.
> 
> So is anyone interested?
> 
> Should we do more within the community to network and discuss our plans
> for QEMU as a modelling solution?
> 
> Any other thoughts?

I would love to hear how Qemu can participate into heterogeneous simulations.
One case is where multiple Qemu instances collaborate with limited interactions,
One case is where there is with memory aliasing (cortex M/R see a « window » of the main memory with a different address for the same byte) between Qemu.
One case Qemu is integrated with  other simulators. An interface to handle aliasing,  MMIO, SMMU, GIC are required to allow all possible cases of which simulator emulate what.
> 
> --
> Alex Bennée
> Virtualisation Tech Lead @ Linaro