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Tsirkin" , Richard Henderson , Paolo Bonzini , Marcel Apfelbaum , Eduardo Habkost Subject: Re: [PATCH 1/2] hw/i386/x86: Fix PIC interrupt handling if APIC globally disabled In-Reply-To: <20240103084900.22856-2-shentey@gmail.com> (Bernhard Beschow's message of "Wed, 3 Jan 2024 09:48:59 +0100") References: <20240103084900.22856-1-shentey@gmail.com> <20240103084900.22856-2-shentey@gmail.com> User-Agent: mu4e 1.11.27; emacs 29.1 Date: Wed, 03 Jan 2024 09:12:24 +0000 Message-ID: <8734veixvr.fsf@draig.linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Bernhard Beschow writes: > QEMU populates the apic_state attribute of x86 CPUs if supported by real > hardware. Even when the APIC is globally disabled by a guest, this attrib= ute > stays populated. This means that the APIC code paths are still used in th= is > case. However, chapter 10.4.3 of [1] requires that: > > When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent = to an > IA-32 processor without an on-chip APIC. The CPUID feature flag for the= APIC > [...] is also set to 0. > > Fix this by checking the APIC feature flag rather than apic_state when de= ciding > whether PIC or APIC behavior is required. This fixes some real-world BIOS= es. > > Notice that presence of the CPUID_APIC flag implies that apic_state is no= n-NULL. > > [1] Intel 64 and IA-32 Architectures Software Developer's Manual, Vol. 3A: > System Programming Guide, Part 1 > > Signed-off-by: Bernhard Beschow > --- > hw/i386/x86.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/hw/i386/x86.c b/hw/i386/x86.c > index 2b6291ad8d..a753d1aeca 100644 > --- a/hw/i386/x86.c > +++ b/hw/i386/x86.c > @@ -516,10 +516,10 @@ static void x86_nmi(NMIState *n, int cpu_index, Err= or **errp) > CPU_FOREACH(cs) { > X86CPU *cpu =3D X86_CPU(cs); >=20=20 > - if (!cpu->apic_state) { > - cpu_interrupt(cs, CPU_INTERRUPT_NMI); > - } else { > + if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC) { You could assert the relationship between the feature and ->apic_state with: g_assert(cpu->apic_state) But probably unnecessary in the grand scheme of things. Anyway: Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro