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From: "Alex Bennée" <alex.bennee@linaro.org>
To: Alistair Francis <alistair.francis@xilinx.com>
Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org,
	qemu-devel@nongnu.org, crosthwaitepeter@gmail.com,
	edgar.iglesias@gmail.com, afaerber@suse.de,
	fred.konrad@greensocs.com
Subject: Re: [Qemu-devel] [PATCH v5 04/15] register: Add support for decoding information
Date: Tue, 22 Mar 2016 17:42:56 +0000	[thread overview]
Message-ID: <8737ris927.fsf@linaro.org> (raw)
In-Reply-To: <fd2181374ca1cdefccb8b388aa13465051227a49.1457470980.git.alistair.francis@xilinx.com>


Alistair Francis <alistair.francis@xilinx.com> writes:

> Allow defining of optional address decoding information in register
> definitions. This is useful for clients that want to associate
> registers with specific addresses.
>
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
> ---
> V3:
>  - Remove unused flags option
>
>  include/hw/register.h | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/include/hw/register.h b/include/hw/register.h
> index 726a914..bc2c96a 100644
> --- a/include/hw/register.h
> +++ b/include/hw/register.h
> @@ -39,6 +39,11 @@ typedef struct RegisterInfoArray RegisterInfoArray;
>   * allowing this function to modify the value before return to the client.
>   */
>
> +#define REG_DECODE_READ (1 << 0)
> +#define REG_DECODE_WRITE (1 << 1)
> +#define REG_DECODE_EXECUTE (1 << 2)
> +#define REG_DECODE_RW (REG_DECODE_READ | REG_DECODE_WRITE)
> +
>  struct RegisterAccessInfo {
>      const char *name;
>      uint64_t ro;

Without any other context I'm unsure of how these defines are going to
be used. Are these just bits at the bottom of an address?

Nothing in this patch series uses them so I suggest you drop this patch
for now.

--
Alex Bennée

  reply	other threads:[~2016-03-22 17:43 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-08 21:06 [Qemu-devel] [PATCH v5 00/15] data-driven device registers Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 01/15] bitops: Add MAKE_64BIT_MASK macro Alistair Francis
2016-03-22 15:26   ` Alex Bennée
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 02/15] register: Add Register API Alistair Francis
2016-03-22 16:28   ` Alex Bennée
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 03/15] register: Add Memory API glue Alistair Francis
2016-03-22 16:56   ` Alex Bennée
2016-03-24 23:03     ` Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 04/15] register: Add support for decoding information Alistair Francis
2016-03-22 17:42   ` Alex Bennée [this message]
2016-03-24 23:17     ` Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 05/15] register: Define REG and FIELD macros Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 06/15] register: QOMify Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 07/15] register: Add block initialise helper Alistair Francis
2016-03-22 17:11   ` Alex Bennée
2016-03-24 23:28     ` Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 08/15] dma: Add Xilinx Zynq devcfg device model Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 09/15] xilinx_zynq: Connect devcfg to the Zynq machine model Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 10/15] qdev: Define qdev_get_gpio_out Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 11/15] qdev: Add qdev_pass_all_gpios API Alistair Francis
2016-03-08 21:06 ` [Qemu-devel] [PATCH v5 12/15] irq: Add opaque setter routine Alistair Francis
2016-03-08 21:07 ` [Qemu-devel] [PATCH v5 13/15] register: Add GPIO API Alistair Francis
2016-03-08 21:07 ` [Qemu-devel] [PATCH v5 14/15] misc: Introduce ZynqMP IOU SLCR Alistair Francis
2016-03-22 17:44 ` [Qemu-devel] [PATCH v5 00/15] data-driven device registers Alex Bennée
2016-03-24 23:43   ` Alistair Francis

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