From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36039) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V7T1m-0002iK-RG for qemu-devel@nongnu.org; Thu, 08 Aug 2013 12:25:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V7T1h-0007Dk-Oh for qemu-devel@nongnu.org; Thu, 08 Aug 2013 12:25:30 -0400 Received: from mail-ie0-f176.google.com ([209.85.223.176]:35407) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V7T1h-0007Dd-Jw for qemu-devel@nongnu.org; Thu, 08 Aug 2013 12:25:25 -0400 Received: by mail-ie0-f176.google.com with SMTP id 9so2188615iec.21 for ; Thu, 08 Aug 2013 09:25:25 -0700 (PDT) From: Anthony Liguori In-Reply-To: References: <1375938949-22622-1-git-send-email-rusty@rustcorp.com.au> <1375938949-22622-2-git-send-email-rusty@rustcorp.com.au> <87li4cgvh1.fsf@codemonkey.ws> <5203AB19.9070505@suse.de> <87r4e4p4wj.fsf@codemonkey.ws> <20130808154507.GX14664@redhat.com> <87pptof9nn.fsf@codemonkey.ws> Date: Thu, 08 Aug 2013 11:25:22 -0500 Message-ID: <8738qkdua5.fsf@codemonkey.ws> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Subject: Re: [Qemu-devel] [PATCH 1/7] virtio: allow byte swapping for vring and config access List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Rusty Russell , Andreas =?utf-8?Q?F=C3=A4r?= =?utf-8?Q?ber?= , qemu-devel@nongnu.org Peter Maydell writes: > On 8 August 2013 17:07, Anthony Liguori wrote: >> It's the same processor. It still starts executing big endian >> instructions. A magic register value is tweaked and loads/stores are >> swapped. > > I dunno about PPC, but for ARM generally the boot-up state is > controlled by config signals which a SoC or board can hardwire, > so you can have a SoC which is configured to start in big-endian > mode. > >> CPU data structures are still read as big endian though. > > Do you have an example of what you mean by "CPU data structure"? MMU tlb hash table. If you grep ldl target-ppc/* you'll see that there are only a few cases where bswap occurs. >> The distinction is important in QEMU. ppc64 is still >> TARGET_WORDS_BIGENDIAN. > > Ideally TARGET_WORDS_BIGENDIAN would go away -- it is forcing > at compile time a setting which is actually a runtime one, > and a lot of the weirdness here flows from that. > >> We still want most stl_phys to treat integers >> as big endian. > > Any stl_phys() should [in an ideal design] be tied to a > "bus master" which has its own idea of which endianness > it is. That is, an stl_phys() for a DMA controller model > ought to use the endianness programmed for the DMA controller, > not whatever the CPU happens to be using. We have the DMA API that attempts to do this but maybe we need to generalize it a bit more... I think it's pretty true that we need a context and that the context for, say instruction fetch, is distinct from the context for load/store instructions. Regards, Anthony Liguori > > -- PMM