* [PATCH 01/15] arm/cpu: Add sysreg definitions in cpu-sysregs.h
2025-02-07 11:02 [PATCH 00/15] arm: rework id register storage Cornelia Huck
@ 2025-02-07 11:02 ` Cornelia Huck
2025-02-07 18:34 ` Richard Henderson
2025-02-18 15:22 ` Eric Auger
2025-02-07 11:02 ` [PATCH 02/15] arm/kvm: add accessors for storing host features into idregs Cornelia Huck
` (13 subsequent siblings)
14 siblings, 2 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-02-07 11:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
This new header contains macros that define aarch64 registers.
In a subsequent patch, this will be replaced by a more exhaustive
version that will be generated from linux arch/arm64/tools/sysreg
file. Those macros are sufficient to migrate the storage of those
ID regs from named fields in isar struct to an array cell.
[CH: reworked to use different structures]
[CH: moved accessors from the patches first using them to here,
dropped interaction with writable registers, which will happen
later]
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-sysregs.h | 131 +++++++++++++++++++++++++++++++++++++++
target/arm/cpu.h | 42 +++++++++++++
2 files changed, 173 insertions(+)
create mode 100644 target/arm/cpu-sysregs.h
diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
new file mode 100644
index 000000000000..de09ebae91a5
--- /dev/null
+++ b/target/arm/cpu-sysregs.h
@@ -0,0 +1,131 @@
+#ifndef ARM_CPU_SYSREGS_H
+#define ARM_CPU_SYSREGS_H
+
+/*
+ * Following is similar to the coprocessor regs encodings, but with an argument
+ * ordering that matches the ARM ARM. We also reuse the various CP_REG_ defines
+ * that actually are the same as the equivalent KVM_REG_ values.
+ */
+#define ENCODE_ID_REG(op0, op1, crn, crm, op2) \
+ (((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
+ ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
+ ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
+ ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
+ ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
+
+typedef enum ARMIDRegisterIdx {
+ ID_AA64PFR0_EL1_IDX,
+ ID_AA64PFR1_EL1_IDX,
+ ID_AA64SMFR0_EL1_IDX,
+ ID_AA64DFR0_EL1_IDX,
+ ID_AA64DFR1_EL1_IDX,
+ ID_AA64ISAR0_EL1_IDX,
+ ID_AA64ISAR1_EL1_IDX,
+ ID_AA64ISAR2_EL1_IDX,
+ ID_AA64MMFR0_EL1_IDX,
+ ID_AA64MMFR1_EL1_IDX,
+ ID_AA64MMFR2_EL1_IDX,
+ ID_AA64MMFR3_EL1_IDX,
+ ID_PFR0_EL1_IDX,
+ ID_PFR1_EL1_IDX,
+ ID_DFR0_EL1_IDX,
+ ID_MMFR0_EL1_IDX,
+ ID_MMFR1_EL1_IDX,
+ ID_MMFR2_EL1_IDX,
+ ID_MMFR3_EL1_IDX,
+ ID_ISAR0_EL1_IDX,
+ ID_ISAR1_EL1_IDX,
+ ID_ISAR2_EL1_IDX,
+ ID_ISAR3_EL1_IDX,
+ ID_ISAR4_EL1_IDX,
+ ID_ISAR5_EL1_IDX,
+ ID_MMFR4_EL1_IDX,
+ ID_ISAR6_EL1_IDX,
+ MVFR0_EL1_IDX,
+ MVFR1_EL1_IDX,
+ MVFR2_EL1_IDX,
+ ID_PFR2_EL1_IDX,
+ ID_DFR1_EL1_IDX,
+ ID_MMFR5_EL1_IDX,
+ ID_AA64ZFR0_EL1_IDX,
+ CTR_EL0_IDX,
+ NUM_ID_IDX,
+} ARMIDRegisterIdx;
+
+typedef enum ARMSysRegs {
+ SYS_ID_AA64PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 0),
+ SYS_ID_AA64PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 1),
+ SYS_ID_AA64SMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 5),
+ SYS_ID_AA64DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 0),
+ SYS_ID_AA64DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 1),
+ SYS_ID_AA64ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 0),
+ SYS_ID_AA64ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 1),
+ SYS_ID_AA64ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 2),
+ SYS_ID_AA64MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 0),
+ SYS_ID_AA64MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 1),
+ SYS_ID_AA64MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 2),
+ SYS_ID_AA64MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 3),
+ SYS_ID_PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 0),
+ SYS_ID_PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 1),
+ SYS_ID_DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 2),
+ SYS_ID_MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 4),
+ SYS_ID_MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 5),
+ SYS_ID_MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 6),
+ SYS_ID_MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 7),
+ SYS_ID_ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 0),
+ SYS_ID_ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 1),
+ SYS_ID_ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 2),
+ SYS_ID_ISAR3_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 3),
+ SYS_ID_ISAR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 4),
+ SYS_ID_ISAR5_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 5),
+ SYS_ID_MMFR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 6),
+ SYS_ID_ISAR6_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 7),
+ SYS_MVFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 0),
+ SYS_MVFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 1),
+ SYS_MVFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 2),
+ SYS_ID_PFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 4),
+ SYS_ID_DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 5),
+ SYS_ID_MMFR5_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 6),
+ SYS_ID_AA64ZFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 4),
+ SYS_CTR_EL0 = ENCODE_ID_REG(3, 3, 0, 0, 1),
+} ARMSysRegs;
+
+static const uint32_t id_register_sysreg[NUM_ID_IDX] = {
+ [ID_AA64PFR0_EL1_IDX] = SYS_ID_AA64PFR0_EL1,
+ [ID_AA64PFR1_EL1_IDX] = SYS_ID_AA64PFR1_EL1,
+ [ID_AA64SMFR0_EL1_IDX] = SYS_ID_AA64SMFR0_EL1,
+ [ID_AA64DFR0_EL1_IDX] = SYS_ID_AA64DFR0_EL1,
+ [ID_AA64DFR1_EL1_IDX] = SYS_ID_AA64DFR1_EL1,
+ [ID_AA64ISAR0_EL1_IDX] = SYS_ID_AA64ISAR0_EL1,
+ [ID_AA64ISAR1_EL1_IDX] = SYS_ID_AA64ISAR1_EL1,
+ [ID_AA64ISAR2_EL1_IDX] = SYS_ID_AA64ISAR2_EL1,
+ [ID_AA64MMFR0_EL1_IDX] = SYS_ID_AA64MMFR0_EL1,
+ [ID_AA64MMFR1_EL1_IDX] = SYS_ID_AA64MMFR1_EL1,
+ [ID_AA64MMFR2_EL1_IDX] = SYS_ID_AA64MMFR2_EL1,
+ [ID_AA64MMFR3_EL1_IDX] = SYS_ID_AA64MMFR3_EL1,
+ [ID_PFR0_EL1_IDX] = SYS_ID_PFR0_EL1,
+ [ID_PFR1_EL1_IDX] = SYS_ID_PFR1_EL1,
+ [ID_DFR0_EL1_IDX] = SYS_ID_DFR0_EL1,
+ [ID_MMFR0_EL1_IDX] = SYS_ID_MMFR0_EL1,
+ [ID_MMFR1_EL1_IDX] = SYS_ID_MMFR1_EL1,
+ [ID_MMFR2_EL1_IDX] = SYS_ID_MMFR2_EL1,
+ [ID_MMFR3_EL1_IDX] = SYS_ID_MMFR3_EL1,
+ [ID_ISAR0_EL1_IDX] = SYS_ID_ISAR0_EL1,
+ [ID_ISAR1_EL1_IDX] = SYS_ID_ISAR1_EL1,
+ [ID_ISAR2_EL1_IDX] = SYS_ID_ISAR2_EL1,
+ [ID_ISAR3_EL1_IDX] = SYS_ID_ISAR3_EL1,
+ [ID_ISAR4_EL1_IDX] = SYS_ID_ISAR4_EL1,
+ [ID_ISAR5_EL1_IDX] = SYS_ID_ISAR5_EL1,
+ [ID_MMFR4_EL1_IDX] = SYS_ID_MMFR4_EL1,
+ [ID_ISAR6_EL1_IDX] = SYS_ID_ISAR6_EL1,
+ [MVFR0_EL1_IDX] = SYS_MVFR0_EL1,
+ [MVFR1_EL1_IDX] = SYS_MVFR1_EL1,
+ [MVFR2_EL1_IDX] = SYS_MVFR2_EL1,
+ [ID_PFR2_EL1_IDX] = SYS_ID_PFR2_EL1,
+ [ID_DFR1_EL1_IDX] = SYS_ID_DFR1_EL1,
+ [ID_MMFR5_EL1_IDX] = SYS_ID_MMFR5_EL1,
+ [ID_AA64ZFR0_EL1_IDX] = SYS_ID_AA64ZFR0_EL1,
+ [CTR_EL0_IDX] = SYS_CTR_EL0,
+};
+
+#endif /* ARM_CPU_SYSREGS_H */
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 2213c277348d..4bbce34e268d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -30,6 +30,7 @@
#include "qapi/qapi-types-common.h"
#include "target/arm/multiprocessing.h"
#include "target/arm/gtimer.h"
+#include "target/arm/cpu-sysregs.h"
#ifdef TARGET_AARCH64
#define KVM_HAVE_MCE_INJECTION 1
@@ -832,6 +833,46 @@ typedef struct {
uint32_t map, init, supported;
} ARMVQMap;
+static inline uint64_t _get_idreg(uint64_t *idregs, uint32_t index)
+{
+ return idregs[index];
+}
+
+static inline void _set_idreg(uint64_t *idregs, uint32_t index, uint64_t value)
+{
+ idregs[index] = value;
+}
+
+/* REG is ID_XXX */
+#define FIELD_DP64_IDREG(ARRAY, REG, FIELD, VALUE) \
+{ \
+ uint64_t regval = _get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX); \
+ regval = FIELD_DP64(regval, REG, FIELD, VALUE); \
+ _set_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX, regval); \
+}
+
+#define FIELD_DP32_IDREG(ARRAY, REG, FIELD, VALUE) \
+{ \
+uint64_t regval = _get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX); \
+regval = FIELD_DP32(regval, REG, FIELD, VALUE); \
+_set_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX, regval); \
+}
+
+#define FIELD_EX64_IDREG(ARRAY, REG, FIELD) \
+FIELD_EX64(_get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX), REG, FIELD) \
+
+#define FIELD_EX32_IDREG(ARRAY, REG, FIELD) \
+FIELD_EX32(_get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX), REG, FIELD) \
+
+#define FIELD_SEX64_IDREG(ARRAY, REG, FIELD) \
+FIELD_SEX64(_get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX), REG, FIELD) \
+
+#define SET_IDREG(ARRAY, REG, VALUE) \
+_set_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX, VALUE)
+
+#define GET_IDREG(ARRAY, REG) \
+_get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX)
+
/**
* ARMCPU:
* @env: #CPUARMState
@@ -1040,6 +1081,7 @@ struct ArchCPU {
uint64_t id_aa64zfr0;
uint64_t id_aa64smfr0;
uint64_t reset_pmcr_el0;
+ uint64_t idregs[NUM_ID_IDX];
} isar;
uint64_t midr;
uint32_t revidr;
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 01/15] arm/cpu: Add sysreg definitions in cpu-sysregs.h
2025-02-07 11:02 ` [PATCH 01/15] arm/cpu: Add sysreg definitions in cpu-sysregs.h Cornelia Huck
@ 2025-02-07 18:34 ` Richard Henderson
2025-02-18 15:22 ` Eric Auger
1 sibling, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2025-02-07 18:34 UTC (permalink / raw)
To: Cornelia Huck, qemu-devel, qemu-arm, kvmarm
On 2/7/25 03:02, Cornelia Huck wrote:
> diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
> new file mode 100644
> index 000000000000..de09ebae91a5
> --- /dev/null
> +++ b/target/arm/cpu-sysregs.h
...
> +static const uint32_t id_register_sysreg[NUM_ID_IDX] = {
You can't place the data into a header like this.
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 2213c277348d..4bbce34e268d 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -30,6 +30,7 @@
> #include "qapi/qapi-types-common.h"
> #include "target/arm/multiprocessing.h"
> #include "target/arm/gtimer.h"
> +#include "target/arm/cpu-sysregs.h"
The data will be replicated into *every* user of cpu.h.
> +static inline uint64_t _get_idreg(uint64_t *idregs, uint32_t index)
> +{
> + return idregs[index];
> +}
> +
> +static inline void _set_idreg(uint64_t *idregs, uint32_t index, uint64_t value)
> +{
> + idregs[index] = value;
> +}
No leading underscores -- this is not a freestanding environment like the kernel.
We must respect the system implementation namespace.
> +/* REG is ID_XXX */
> +#define FIELD_DP64_IDREG(ARRAY, REG, FIELD, VALUE) \
> +{ \
> + uint64_t regval = _get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX); \
> + regval = FIELD_DP64(regval, REG, FIELD, VALUE); \
> + _set_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX, regval); \
> +}
> +
> +#define FIELD_DP32_IDREG(ARRAY, REG, FIELD, VALUE) \
> +{ \
> +uint64_t regval = _get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX); \
> +regval = FIELD_DP32(regval, REG, FIELD, VALUE); \
> +_set_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX, regval); \
> +}
> +
> +#define FIELD_EX64_IDREG(ARRAY, REG, FIELD) \
> +FIELD_EX64(_get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX), REG, FIELD) \
> +
> +#define FIELD_EX32_IDREG(ARRAY, REG, FIELD) \
> +FIELD_EX32(_get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX), REG, FIELD) \
> +
> +#define FIELD_SEX64_IDREG(ARRAY, REG, FIELD) \
> +FIELD_SEX64(_get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX), REG, FIELD) \
> +
> +#define SET_IDREG(ARRAY, REG, VALUE) \
> +_set_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX, VALUE)
> +
> +#define GET_IDREG(ARRAY, REG) \
> +_get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX)
The casts look wrong, and seem very likely to hide bugs.
The macros should be written to be type-safe.
Perhaps like this:
#define FIELD_EX64_IDREG(ISAR, REG, FIELD) \
({ const ARMISARegisters *i_ = (ISAR); \
FIELD_EX64(i_->idregs[REG ## _EL1_IDX], REG, FIELD); })
r~
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 01/15] arm/cpu: Add sysreg definitions in cpu-sysregs.h
2025-02-07 11:02 ` [PATCH 01/15] arm/cpu: Add sysreg definitions in cpu-sysregs.h Cornelia Huck
2025-02-07 18:34 ` Richard Henderson
@ 2025-02-18 15:22 ` Eric Auger
1 sibling, 0 replies; 29+ messages in thread
From: Eric Auger @ 2025-02-18 15:22 UTC (permalink / raw)
To: Cornelia Huck, eric.auger.pro, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini
Hi Connie,
On 2/7/25 12:02 PM, Cornelia Huck wrote:
> From: Eric Auger <eric.auger@redhat.com>
>
> This new header contains macros that define aarch64 registers.
> In a subsequent patch, this will be replaced by a more exhaustive
> version that will be generated from linux arch/arm64/tools/sysreg
> file. Those macros are sufficient to migrate the storage of those
> ID regs from named fields in isar struct to an array cell.
>
> [CH: reworked to use different structures]
> [CH: moved accessors from the patches first using them to here,
> dropped interaction with writable registers, which will happen
> later]
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
> ---
> target/arm/cpu-sysregs.h | 131 +++++++++++++++++++++++++++++++++++++++
> target/arm/cpu.h | 42 +++++++++++++
> 2 files changed, 173 insertions(+)
> create mode 100644 target/arm/cpu-sysregs.h
>
> diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
> new file mode 100644
> index 000000000000..de09ebae91a5
> --- /dev/null
> +++ b/target/arm/cpu-sysregs.h
> @@ -0,0 +1,131 @@
> +#ifndef ARM_CPU_SYSREGS_H
> +#define ARM_CPU_SYSREGS_H
> +
> +/*
> + * Following is similar to the coprocessor regs encodings, but with an argument
> + * ordering that matches the ARM ARM. We also reuse the various CP_REG_ defines
> + * that actually are the same as the equivalent KVM_REG_ values.
> + */
> +#define ENCODE_ID_REG(op0, op1, crn, crm, op2) \
> + (((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \
> + ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \
> + ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
> + ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
> + ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
> +
> +typedef enum ARMIDRegisterIdx {
> + ID_AA64PFR0_EL1_IDX,
> + ID_AA64PFR1_EL1_IDX,
> + ID_AA64SMFR0_EL1_IDX,
> + ID_AA64DFR0_EL1_IDX,
> + ID_AA64DFR1_EL1_IDX,
> + ID_AA64ISAR0_EL1_IDX,
> + ID_AA64ISAR1_EL1_IDX,
> + ID_AA64ISAR2_EL1_IDX,
> + ID_AA64MMFR0_EL1_IDX,
> + ID_AA64MMFR1_EL1_IDX,
> + ID_AA64MMFR2_EL1_IDX,
> + ID_AA64MMFR3_EL1_IDX,
> + ID_PFR0_EL1_IDX,
> + ID_PFR1_EL1_IDX,
> + ID_DFR0_EL1_IDX,
> + ID_MMFR0_EL1_IDX,
> + ID_MMFR1_EL1_IDX,
> + ID_MMFR2_EL1_IDX,
> + ID_MMFR3_EL1_IDX,
> + ID_ISAR0_EL1_IDX,
> + ID_ISAR1_EL1_IDX,
> + ID_ISAR2_EL1_IDX,
> + ID_ISAR3_EL1_IDX,
> + ID_ISAR4_EL1_IDX,
> + ID_ISAR5_EL1_IDX,
> + ID_MMFR4_EL1_IDX,
> + ID_ISAR6_EL1_IDX,
> + MVFR0_EL1_IDX,
> + MVFR1_EL1_IDX,
> + MVFR2_EL1_IDX,
> + ID_PFR2_EL1_IDX,
> + ID_DFR1_EL1_IDX,
> + ID_MMFR5_EL1_IDX,
> + ID_AA64ZFR0_EL1_IDX,
> + CTR_EL0_IDX,
> + NUM_ID_IDX,
> +} ARMIDRegisterIdx;
> +
> +typedef enum ARMSysRegs {
> + SYS_ID_AA64PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 0),
> + SYS_ID_AA64PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 1),
> + SYS_ID_AA64SMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 5),
> + SYS_ID_AA64DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 0),
> + SYS_ID_AA64DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 1),
> + SYS_ID_AA64ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 0),
> + SYS_ID_AA64ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 1),
> + SYS_ID_AA64ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 2),
> + SYS_ID_AA64MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 0),
> + SYS_ID_AA64MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 1),
> + SYS_ID_AA64MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 2),
> + SYS_ID_AA64MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 3),
> + SYS_ID_PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 0),
> + SYS_ID_PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 1),
> + SYS_ID_DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 2),
> + SYS_ID_MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 4),
> + SYS_ID_MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 5),
> + SYS_ID_MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 6),
> + SYS_ID_MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 7),
> + SYS_ID_ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 0),
> + SYS_ID_ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 1),
> + SYS_ID_ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 2),
> + SYS_ID_ISAR3_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 3),
> + SYS_ID_ISAR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 4),
> + SYS_ID_ISAR5_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 5),
> + SYS_ID_MMFR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 6),
> + SYS_ID_ISAR6_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 7),
> + SYS_MVFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 0),
> + SYS_MVFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 1),
> + SYS_MVFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 2),
> + SYS_ID_PFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 4),
> + SYS_ID_DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 5),
> + SYS_ID_MMFR5_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 6),
> + SYS_ID_AA64ZFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 4),
> + SYS_CTR_EL0 = ENCODE_ID_REG(3, 3, 0, 0, 1),
> +} ARMSysRegs;
> +
> +static const uint32_t id_register_sysreg[NUM_ID_IDX] = {
> + [ID_AA64PFR0_EL1_IDX] = SYS_ID_AA64PFR0_EL1,
> + [ID_AA64PFR1_EL1_IDX] = SYS_ID_AA64PFR1_EL1,
> + [ID_AA64SMFR0_EL1_IDX] = SYS_ID_AA64SMFR0_EL1,
> + [ID_AA64DFR0_EL1_IDX] = SYS_ID_AA64DFR0_EL1,
> + [ID_AA64DFR1_EL1_IDX] = SYS_ID_AA64DFR1_EL1,
> + [ID_AA64ISAR0_EL1_IDX] = SYS_ID_AA64ISAR0_EL1,
> + [ID_AA64ISAR1_EL1_IDX] = SYS_ID_AA64ISAR1_EL1,
> + [ID_AA64ISAR2_EL1_IDX] = SYS_ID_AA64ISAR2_EL1,
> + [ID_AA64MMFR0_EL1_IDX] = SYS_ID_AA64MMFR0_EL1,
> + [ID_AA64MMFR1_EL1_IDX] = SYS_ID_AA64MMFR1_EL1,
> + [ID_AA64MMFR2_EL1_IDX] = SYS_ID_AA64MMFR2_EL1,
> + [ID_AA64MMFR3_EL1_IDX] = SYS_ID_AA64MMFR3_EL1,
> + [ID_PFR0_EL1_IDX] = SYS_ID_PFR0_EL1,
> + [ID_PFR1_EL1_IDX] = SYS_ID_PFR1_EL1,
> + [ID_DFR0_EL1_IDX] = SYS_ID_DFR0_EL1,
> + [ID_MMFR0_EL1_IDX] = SYS_ID_MMFR0_EL1,
> + [ID_MMFR1_EL1_IDX] = SYS_ID_MMFR1_EL1,
> + [ID_MMFR2_EL1_IDX] = SYS_ID_MMFR2_EL1,
> + [ID_MMFR3_EL1_IDX] = SYS_ID_MMFR3_EL1,
> + [ID_ISAR0_EL1_IDX] = SYS_ID_ISAR0_EL1,
> + [ID_ISAR1_EL1_IDX] = SYS_ID_ISAR1_EL1,
> + [ID_ISAR2_EL1_IDX] = SYS_ID_ISAR2_EL1,
> + [ID_ISAR3_EL1_IDX] = SYS_ID_ISAR3_EL1,
> + [ID_ISAR4_EL1_IDX] = SYS_ID_ISAR4_EL1,
> + [ID_ISAR5_EL1_IDX] = SYS_ID_ISAR5_EL1,
> + [ID_MMFR4_EL1_IDX] = SYS_ID_MMFR4_EL1,
> + [ID_ISAR6_EL1_IDX] = SYS_ID_ISAR6_EL1,
> + [MVFR0_EL1_IDX] = SYS_MVFR0_EL1,
> + [MVFR1_EL1_IDX] = SYS_MVFR1_EL1,
> + [MVFR2_EL1_IDX] = SYS_MVFR2_EL1,
> + [ID_PFR2_EL1_IDX] = SYS_ID_PFR2_EL1,
> + [ID_DFR1_EL1_IDX] = SYS_ID_DFR1_EL1,
> + [ID_MMFR5_EL1_IDX] = SYS_ID_MMFR5_EL1,
> + [ID_AA64ZFR0_EL1_IDX] = SYS_ID_AA64ZFR0_EL1,
> + [CTR_EL0_IDX] = SYS_CTR_EL0,
> +};
> +
> +#endif /* ARM_CPU_SYSREGS_H */
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 2213c277348d..4bbce34e268d 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -30,6 +30,7 @@
> #include "qapi/qapi-types-common.h"
> #include "target/arm/multiprocessing.h"
> #include "target/arm/gtimer.h"
> +#include "target/arm/cpu-sysregs.h"
>
> #ifdef TARGET_AARCH64
> #define KVM_HAVE_MCE_INJECTION 1
> @@ -832,6 +833,46 @@ typedef struct {
> uint32_t map, init, supported;
> } ARMVQMap;
>
> +static inline uint64_t _get_idreg(uint64_t *idregs, uint32_t index)
> +{
> + return idregs[index];
> +}
> +
> +static inline void _set_idreg(uint64_t *idregs, uint32_t index, uint64_t value)
> +{
> + idregs[index] = value;
> +}
> +
> +/* REG is ID_XXX */
nit: we have MVFRx too so maybe we shall rather say that REG is the
ARMIDRegisterIdx litteral without _EL1_IDX suffix or just remove the comment
> +#define FIELD_DP64_IDREG(ARRAY, REG, FIELD, VALUE) \
> +{ \
> + uint64_t regval = _get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX); \
> + regval = FIELD_DP64(regval, REG, FIELD, VALUE); \
> + _set_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX, regval); \
> +}
> +
> +#define FIELD_DP32_IDREG(ARRAY, REG, FIELD, VALUE) \
> +{ \
> +uint64_t regval = _get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX); \
> +regval = FIELD_DP32(regval, REG, FIELD, VALUE); \
> +_set_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX, regval); \
> +}
> +
> +#define FIELD_EX64_IDREG(ARRAY, REG, FIELD) \
> +FIELD_EX64(_get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX), REG, FIELD) \
> +
> +#define FIELD_EX32_IDREG(ARRAY, REG, FIELD) \
> +FIELD_EX32(_get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX), REG, FIELD) \
> +
> +#define FIELD_SEX64_IDREG(ARRAY, REG, FIELD) \
> +FIELD_SEX64(_get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX), REG, FIELD) \
> +
> +#define SET_IDREG(ARRAY, REG, VALUE) \
> +_set_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX, VALUE)
> +
> +#define GET_IDREG(ARRAY, REG) \
> +_get_idreg((uint64_t *)ARRAY, REG ## _EL1_IDX)
> +
> /**
> * ARMCPU:
> * @env: #CPUARMState
> @@ -1040,6 +1081,7 @@ struct ArchCPU {
> uint64_t id_aa64zfr0;
> uint64_t id_aa64smfr0;
> uint64_t reset_pmcr_el0;
> + uint64_t idregs[NUM_ID_IDX];
> } isar;
> uint64_t midr;
> uint32_t revidr;
Thanks
Eric
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 02/15] arm/kvm: add accessors for storing host features into idregs
2025-02-07 11:02 [PATCH 00/15] arm: rework id register storage Cornelia Huck
2025-02-07 11:02 ` [PATCH 01/15] arm/cpu: Add sysreg definitions in cpu-sysregs.h Cornelia Huck
@ 2025-02-07 11:02 ` Cornelia Huck
2025-02-07 18:43 ` Richard Henderson
` (2 more replies)
2025-02-07 11:02 ` [PATCH 03/15] arm/cpu: Store aa64isar0 into the idregs arrays Cornelia Huck
` (12 subsequent siblings)
14 siblings, 3 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-02-07 11:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-sysregs.h | 3 +++
target/arm/cpu64.c | 25 +++++++++++++++++++++++++
target/arm/kvm.c | 30 ++++++++++++++++++++++++++++++
3 files changed, 58 insertions(+)
diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
index de09ebae91a5..54a4fadbf0c1 100644
--- a/target/arm/cpu-sysregs.h
+++ b/target/arm/cpu-sysregs.h
@@ -128,4 +128,7 @@ static const uint32_t id_register_sysreg[NUM_ID_IDX] = {
[CTR_EL0_IDX] = SYS_CTR_EL0,
};
+int get_sysreg_idx(ARMSysRegs sysreg);
+uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg);
+
#endif /* ARM_CPU_SYSREGS_H */
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 8188ede5cc8a..9ae78253cb34 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -736,6 +736,31 @@ static void aarch64_a53_initfn(Object *obj)
define_cortex_a72_a57_a53_cp_reginfo(cpu);
}
+#ifdef CONFIG_KVM
+
+int get_sysreg_idx(ARMSysRegs sysreg)
+{
+ int i;
+
+ for (i = 0; i < NUM_ID_IDX; i++) {
+ if (id_register_sysreg[i] == sysreg) {
+ return i;
+ }
+ }
+ return -1;
+}
+
+uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg)
+{
+ return ARM64_SYS_REG((sysreg & CP_REG_ARM64_SYSREG_OP0_MASK) >> CP_REG_ARM64_SYSREG_OP0_SHIFT,
+ (sysreg & CP_REG_ARM64_SYSREG_OP1_MASK) >> CP_REG_ARM64_SYSREG_OP1_SHIFT,
+ (sysreg & CP_REG_ARM64_SYSREG_CRN_MASK) >> CP_REG_ARM64_SYSREG_CRN_SHIFT,
+ (sysreg & CP_REG_ARM64_SYSREG_CRM_MASK) >> CP_REG_ARM64_SYSREG_CRM_SHIFT,
+ (sysreg & CP_REG_ARM64_SYSREG_OP2_MASK) >> CP_REG_ARM64_SYSREG_OP2_SHIFT);
+}
+
+#endif
+
static void aarch64_host_initfn(Object *obj)
{
#if defined(CONFIG_KVM)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index da30bdbb2349..3b8bb5661f2b 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -246,6 +246,36 @@ static bool kvm_arm_pauth_supported(void)
kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC));
}
+/* read a 32b sysreg value and store it in the idregs */
+static int get_host_cpu_reg32(int fd, ARMHostCPUFeatures *ahcf, ARMSysRegs sysreg)
+{
+ int index = get_sysreg_idx(sysreg);
+ uint64_t *reg;
+ int ret;
+
+ if (index < 0) {
+ return -ERANGE;
+ }
+ reg = &ahcf->isar.idregs[index];
+ ret = read_sys_reg32(fd, (uint32_t *)reg, idregs_sysreg_to_kvm_reg(sysreg));
+ return ret;
+}
+
+/* read a 64b sysreg value and store it in the idregs */
+static int get_host_cpu_reg64(int fd, ARMHostCPUFeatures *ahcf, ARMSysRegs sysreg)
+{
+ int index = get_sysreg_idx(sysreg);
+ uint64_t *reg;
+ int ret;
+
+ if (index < 0) {
+ return -ERANGE;
+ }
+ reg = &ahcf->isar.idregs[index];
+ ret = read_sys_reg64(fd, reg, idregs_sysreg_to_kvm_reg(sysreg));
+ return ret;
+}
+
static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
{
/* Identify the feature bits corresponding to the host CPU, and
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 02/15] arm/kvm: add accessors for storing host features into idregs
2025-02-07 11:02 ` [PATCH 02/15] arm/kvm: add accessors for storing host features into idregs Cornelia Huck
@ 2025-02-07 18:43 ` Richard Henderson
2025-02-07 18:50 ` Richard Henderson
2025-02-18 15:33 ` Eric Auger
2 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2025-02-07 18:43 UTC (permalink / raw)
To: Cornelia Huck, qemu-devel, qemu-arm, kvmarm
On 2/7/25 03:02, Cornelia Huck wrote:
> +/* read a 32b sysreg value and store it in the idregs */
> +static int get_host_cpu_reg32(int fd, ARMHostCPUFeatures *ahcf, ARMSysRegs sysreg)
> +{
> + int index = get_sysreg_idx(sysreg);
> + uint64_t *reg;
> + int ret;
> +
> + if (index < 0) {
> + return -ERANGE;
> + }
> + reg = &ahcf->isar.idregs[index];
> + ret = read_sys_reg32(fd, (uint32_t *)reg, idregs_sysreg_to_kvm_reg(sysreg));
> + return ret;
> +}
I'm not keen on the casting.
If we want to retain read_sys_reg32 at all, then
uint32_t tmp;
ret = read_sys_reg32(fd, &tmp, idregs_sysreg_to_kvm_reg(sysreg));
if (ret == 0) {
ahcf->isar.idregs[index] = tmp;
}
return ret;
That said, read_sys_reg32 does exactly the opposite, using a uint64_t temporary.
Therefore I would say that we should simply use read_sys_reg64.
r~
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 02/15] arm/kvm: add accessors for storing host features into idregs
2025-02-07 11:02 ` [PATCH 02/15] arm/kvm: add accessors for storing host features into idregs Cornelia Huck
2025-02-07 18:43 ` Richard Henderson
@ 2025-02-07 18:50 ` Richard Henderson
2025-02-18 15:33 ` Eric Auger
2 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2025-02-07 18:50 UTC (permalink / raw)
To: Cornelia Huck, qemu-devel, qemu-arm, kvmarm
On 2/7/25 03:02, Cornelia Huck wrote:
> +/* read a 32b sysreg value and store it in the idregs */
> +static int get_host_cpu_reg32(int fd, ARMHostCPUFeatures *ahcf, ARMSysRegs sysreg)
> +{
> + int index = get_sysreg_idx(sysreg);
> + uint64_t *reg;
> + int ret;
> +
> + if (index < 0) {
> + return -ERANGE;
> + }
> + reg = &ahcf->isar.idregs[index];
> + ret = read_sys_reg32(fd, (uint32_t *)reg, idregs_sysreg_to_kvm_reg(sysreg));
> + return ret;
> +}
> +
> +/* read a 64b sysreg value and store it in the idregs */
> +static int get_host_cpu_reg64(int fd, ARMHostCPUFeatures *ahcf, ARMSysRegs sysreg)
> +{
> + int index = get_sysreg_idx(sysreg);
Why pass the ARMSysRegs value instead of the ARMIDRegisterIdx value?
You save yourself a linear search over the id_register_sysreg array, and you can't use
this interface with a sysreg that doesn't have an index anyway -- ERANGE is a new failure
mode.
r~
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 02/15] arm/kvm: add accessors for storing host features into idregs
2025-02-07 11:02 ` [PATCH 02/15] arm/kvm: add accessors for storing host features into idregs Cornelia Huck
2025-02-07 18:43 ` Richard Henderson
2025-02-07 18:50 ` Richard Henderson
@ 2025-02-18 15:33 ` Eric Auger
2025-02-18 15:54 ` Cornelia Huck
2 siblings, 1 reply; 29+ messages in thread
From: Eric Auger @ 2025-02-18 15:33 UTC (permalink / raw)
To: Cornelia Huck, eric.auger.pro, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini
Hi Connie
On 2/7/25 12:02 PM, Cornelia Huck wrote:
> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
> ---
> target/arm/cpu-sysregs.h | 3 +++
> target/arm/cpu64.c | 25 +++++++++++++++++++++++++
> target/arm/kvm.c | 30 ++++++++++++++++++++++++++++++
> 3 files changed, 58 insertions(+)
>
> diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
> index de09ebae91a5..54a4fadbf0c1 100644
> --- a/target/arm/cpu-sysregs.h
> +++ b/target/arm/cpu-sysregs.h
> @@ -128,4 +128,7 @@ static const uint32_t id_register_sysreg[NUM_ID_IDX] = {
> [CTR_EL0_IDX] = SYS_CTR_EL0,
> };
>
> +int get_sysreg_idx(ARMSysRegs sysreg);
> +uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg);
> +
> #endif /* ARM_CPU_SYSREGS_H */
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index 8188ede5cc8a..9ae78253cb34 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -736,6 +736,31 @@ static void aarch64_a53_initfn(Object *obj)
> define_cortex_a72_a57_a53_cp_reginfo(cpu);
> }
>
> +#ifdef CONFIG_KVM
> +
> +int get_sysreg_idx(ARMSysRegs sysreg)
> +{
> + int i;
> +
> + for (i = 0; i < NUM_ID_IDX; i++) {
> + if (id_register_sysreg[i] == sysreg) {
I agree with Richard that if we could get rid of this linear search it
would be nicer.
> + return i;
> + }
> + }
> + return -1;
> +}
> +
> +uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg)
> +{
> + return ARM64_SYS_REG((sysreg & CP_REG_ARM64_SYSREG_OP0_MASK) >> CP_REG_ARM64_SYSREG_OP0_SHIFT,
> + (sysreg & CP_REG_ARM64_SYSREG_OP1_MASK) >> CP_REG_ARM64_SYSREG_OP1_SHIFT,
> + (sysreg & CP_REG_ARM64_SYSREG_CRN_MASK) >> CP_REG_ARM64_SYSREG_CRN_SHIFT,
> + (sysreg & CP_REG_ARM64_SYSREG_CRM_MASK) >> CP_REG_ARM64_SYSREG_CRM_SHIFT,
> + (sysreg & CP_REG_ARM64_SYSREG_OP2_MASK) >> CP_REG_ARM64_SYSREG_OP2_SHIFT);
> +}
> +
> +#endif
> +
> static void aarch64_host_initfn(Object *obj)
> {
> #if defined(CONFIG_KVM)
> diff --git a/target/arm/kvm.c b/target/arm/kvm.c
> index da30bdbb2349..3b8bb5661f2b 100644
> --- a/target/arm/kvm.c
> +++ b/target/arm/kvm.c
> @@ -246,6 +246,36 @@ static bool kvm_arm_pauth_supported(void)
> kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC));
> }
>
> +/* read a 32b sysreg value and store it in the idregs */
> +static int get_host_cpu_reg32(int fd, ARMHostCPUFeatures *ahcf, ARMSysRegs sysreg)
those are defined as static but there is no user so this will break
compilation locally
Eric
> +{
> + int index = get_sysreg_idx(sysreg);
> + uint64_t *reg;
> + int ret;
> +
> + if (index < 0) {
> + return -ERANGE;
> + }
> + reg = &ahcf->isar.idregs[index];
> + ret = read_sys_reg32(fd, (uint32_t *)reg, idregs_sysreg_to_kvm_reg(sysreg));
> + return ret;
> +}
> +
> +/* read a 64b sysreg value and store it in the idregs */
> +static int get_host_cpu_reg64(int fd, ARMHostCPUFeatures *ahcf, ARMSysRegs sysreg)
> +{
> + int index = get_sysreg_idx(sysreg);
> + uint64_t *reg;
> + int ret;
> +
> + if (index < 0) {
> + return -ERANGE;
> + }
> + reg = &ahcf->isar.idregs[index];
> + ret = read_sys_reg64(fd, reg, idregs_sysreg_to_kvm_reg(sysreg));
> + return ret;
> +}
> +
> static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> {
> /* Identify the feature bits corresponding to the host CPU, and
^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH 02/15] arm/kvm: add accessors for storing host features into idregs
2025-02-18 15:33 ` Eric Auger
@ 2025-02-18 15:54 ` Cornelia Huck
0 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-02-18 15:54 UTC (permalink / raw)
To: eric.auger, eric.auger.pro, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini
On Tue, Feb 18 2025, Eric Auger <eric.auger@redhat.com> wrote:
> Hi Connie
>
> On 2/7/25 12:02 PM, Cornelia Huck wrote:
>> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
>> ---
>> target/arm/cpu-sysregs.h | 3 +++
>> target/arm/cpu64.c | 25 +++++++++++++++++++++++++
>> target/arm/kvm.c | 30 ++++++++++++++++++++++++++++++
>> 3 files changed, 58 insertions(+)
>>
>> diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
>> index de09ebae91a5..54a4fadbf0c1 100644
>> --- a/target/arm/cpu-sysregs.h
>> +++ b/target/arm/cpu-sysregs.h
>> @@ -128,4 +128,7 @@ static const uint32_t id_register_sysreg[NUM_ID_IDX] = {
>> [CTR_EL0_IDX] = SYS_CTR_EL0,
>> };
>>
>> +int get_sysreg_idx(ARMSysRegs sysreg);
>> +uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg);
>> +
>> #endif /* ARM_CPU_SYSREGS_H */
>> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
>> index 8188ede5cc8a..9ae78253cb34 100644
>> --- a/target/arm/cpu64.c
>> +++ b/target/arm/cpu64.c
>> @@ -736,6 +736,31 @@ static void aarch64_a53_initfn(Object *obj)
>> define_cortex_a72_a57_a53_cp_reginfo(cpu);
>> }
>>
>> +#ifdef CONFIG_KVM
>> +
>> +int get_sysreg_idx(ARMSysRegs sysreg)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < NUM_ID_IDX; i++) {
>> + if (id_register_sysreg[i] == sysreg) {
> I agree with Richard that if we could get rid of this linear search it
> would be nicer.
FWIW, I have a local branch which reworks the lookup and the macros that
is currently in the "it compiles" stage. Hopefully progressing to the
"it works" stage (provided I'm not preempted by other things again.)
>> + return i;
>> + }
>> + }
>> + return -1;
>> +}
>> +
>> +uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg)
>> +{
>> + return ARM64_SYS_REG((sysreg & CP_REG_ARM64_SYSREG_OP0_MASK) >> CP_REG_ARM64_SYSREG_OP0_SHIFT,
>> + (sysreg & CP_REG_ARM64_SYSREG_OP1_MASK) >> CP_REG_ARM64_SYSREG_OP1_SHIFT,
>> + (sysreg & CP_REG_ARM64_SYSREG_CRN_MASK) >> CP_REG_ARM64_SYSREG_CRN_SHIFT,
>> + (sysreg & CP_REG_ARM64_SYSREG_CRM_MASK) >> CP_REG_ARM64_SYSREG_CRM_SHIFT,
>> + (sysreg & CP_REG_ARM64_SYSREG_OP2_MASK) >> CP_REG_ARM64_SYSREG_OP2_SHIFT);
>> +}
>> +
>> +#endif
>> +
>> static void aarch64_host_initfn(Object *obj)
>> {
>> #if defined(CONFIG_KVM)
>> diff --git a/target/arm/kvm.c b/target/arm/kvm.c
>> index da30bdbb2349..3b8bb5661f2b 100644
>> --- a/target/arm/kvm.c
>> +++ b/target/arm/kvm.c
>> @@ -246,6 +246,36 @@ static bool kvm_arm_pauth_supported(void)
>> kvm_check_extension(kvm_state, KVM_CAP_ARM_PTRAUTH_GENERIC));
>> }
>>
>> +/* read a 32b sysreg value and store it in the idregs */
>> +static int get_host_cpu_reg32(int fd, ARMHostCPUFeatures *ahcf, ARMSysRegs sysreg)
> those are defined as static but there is no user so this will break
> compilation locally
Hm, didn't see that, but noticed a few other places that are b0rken. I
think I need to fiddle with my config to broaden compilation coverage.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 03/15] arm/cpu: Store aa64isar0 into the idregs arrays
2025-02-07 11:02 [PATCH 00/15] arm: rework id register storage Cornelia Huck
2025-02-07 11:02 ` [PATCH 01/15] arm/cpu: Add sysreg definitions in cpu-sysregs.h Cornelia Huck
2025-02-07 11:02 ` [PATCH 02/15] arm/kvm: add accessors for storing host features into idregs Cornelia Huck
@ 2025-02-07 11:02 ` Cornelia Huck
2025-02-07 18:46 ` Richard Henderson
2025-02-07 11:02 ` [PATCH 04/15] arm/cpu: Store aa64isar1/2 into the idregs array Cornelia Huck
` (11 subsequent siblings)
14 siblings, 1 reply; 29+ messages in thread
From: Cornelia Huck @ 2025-02-07 11:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-features.h | 57 ++++++++++++++++++++-------------------
target/arm/cpu.c | 14 ++++------
target/arm/cpu.h | 2 --
target/arm/cpu64.c | 8 +++---
target/arm/helper.c | 6 +++--
target/arm/kvm.c | 8 +++---
target/arm/tcg/cpu64.c | 44 ++++++++++++++++++------------
7 files changed, 74 insertions(+), 65 deletions(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 30302d6c5b41..9638c9428db3 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -22,6 +22,7 @@
#include "hw/registerfields.h"
#include "qemu/host-utils.h"
+#include "cpu-sysregs.h"
/*
* Naming convention for isar_feature functions:
@@ -376,92 +377,92 @@ static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id)
*/
static inline bool isar_feature_aa64_aes(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, AES) != 0;
}
static inline bool isar_feature_aa64_pmull(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, AES) > 1;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, AES) > 1;
}
static inline bool isar_feature_aa64_sha1(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA1) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, SHA1) != 0;
}
static inline bool isar_feature_aa64_sha256(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, SHA2) != 0;
}
static inline bool isar_feature_aa64_sha512(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA2) > 1;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, SHA2) > 1;
}
static inline bool isar_feature_aa64_crc32(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, CRC32) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, CRC32) != 0;
}
static inline bool isar_feature_aa64_atomics(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, ATOMIC) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, ATOMIC) != 0;
}
static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RDM) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, RDM) != 0;
}
static inline bool isar_feature_aa64_sha3(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SHA3) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, SHA3) != 0;
}
static inline bool isar_feature_aa64_sm3(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM3) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, SM3) != 0;
}
static inline bool isar_feature_aa64_sm4(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, SM4) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, SM4) != 0;
}
static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, DP) != 0;
}
static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, FHM) != 0;
}
static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, TS) != 0;
}
static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, TS) >= 2;
}
static inline bool isar_feature_aa64_rndr(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, RNDR) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, RNDR) != 0;
}
static inline bool isar_feature_aa64_tlbirange(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, TLB) == 2;
}
static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR0, TLB) != 0;
}
static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
@@ -917,52 +918,52 @@ static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, SVEVER) != 0;
}
static inline bool isar_feature_aa64_sve2_aes(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, AES) != 0;
}
static inline bool isar_feature_aa64_sve2_pmull128(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, AES) >= 2;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, AES) >= 2;
}
static inline bool isar_feature_aa64_sve2_bitperm(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, BITPERM) != 0;
}
static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BFLOAT16) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, BFLOAT16) != 0;
}
static inline bool isar_feature_aa64_sve2_sha3(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SHA3) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, SHA3) != 0;
}
static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, SM4) != 0;
}
static inline bool isar_feature_aa64_sve_i8mm(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, I8MM) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, I8MM) != 0;
}
static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, F32MM) != 0;
}
static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ZFR0, F64MM) != 0;
}
static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 7a83b9ee34f7..861b7f893c0c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1989,6 +1989,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
ARMCPU *cpu = ARM_CPU(dev);
+ uint64_t *idregs = cpu->isar.idregs;
ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
CPUARMState *env = &cpu->env;
Error *local_err = NULL;
@@ -2190,7 +2191,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
unset_feature(env, ARM_FEATURE_NEON);
- t = cpu->isar.id_aa64isar0;
+ t = GET_IDREG(idregs, ID_AA64ISAR0);
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0);
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0);
t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0);
@@ -2198,7 +2199,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 0);
t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 0);
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
- cpu->isar.id_aa64isar0 = t;
+ SET_IDREG(idregs, ID_AA64ISAR0, t);
t = cpu->isar.id_aa64isar1;
t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
@@ -2240,16 +2241,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
}
if (!cpu->has_neon && !cpu->has_vfp) {
- uint64_t t;
uint32_t u;
- t = cpu->isar.id_aa64isar0;
- t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 0);
- cpu->isar.id_aa64isar0 = t;
+ FIELD_DP64_IDREG(idregs, ID_AA64ISAR0, FHM, 0);
- t = cpu->isar.id_aa64isar1;
- t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 0);
- cpu->isar.id_aa64isar1 = t;
+ FIELD_DP64_IDREG(idregs, ID_AA64ISAR1, FRINTTS, 0);
u = cpu->isar.mvfr0;
u = FIELD_DP32(u, MVFR0, SIMDREG, 0);
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 4bbce34e268d..cbc1804dbd32 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1067,7 +1067,6 @@ struct ArchCPU {
uint32_t dbgdidr;
uint32_t dbgdevid;
uint32_t dbgdevid1;
- uint64_t id_aa64isar0;
uint64_t id_aa64isar1;
uint64_t id_aa64isar2;
uint64_t id_aa64pfr0;
@@ -1078,7 +1077,6 @@ struct ArchCPU {
uint64_t id_aa64mmfr3;
uint64_t id_aa64dfr0;
uint64_t id_aa64dfr1;
- uint64_t id_aa64zfr0;
uint64_t id_aa64smfr0;
uint64_t reset_pmcr_el0;
uint64_t idregs[NUM_ID_IDX];
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 9ae78253cb34..f582a8ae6cd1 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -114,7 +114,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
* SVE is disabled and so are all vector lengths. Good.
* Disable all SVE extensions as well.
*/
- cpu->isar.id_aa64zfr0 = 0;
+ SET_IDREG(&cpu->isar.idregs, ID_AA64ZFR0, 0);
return;
}
@@ -617,6 +617,7 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
static void aarch64_a57_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,cortex-a57";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -654,7 +655,7 @@ static void aarch64_a57_initfn(Object *obj)
cpu->isar.id_isar6 = 0;
cpu->isar.id_aa64pfr0 = 0x00002222;
cpu->isar.id_aa64dfr0 = 0x10305106;
- cpu->isar.id_aa64isar0 = 0x00011120;
+ SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
cpu->isar.id_aa64mmfr0 = 0x00001124;
cpu->isar.dbgdidr = 0x3516d000;
cpu->isar.dbgdevid = 0x01110f13;
@@ -678,6 +679,7 @@ static void aarch64_a57_initfn(Object *obj)
static void aarch64_a53_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,cortex-a53";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -715,7 +717,7 @@ static void aarch64_a53_initfn(Object *obj)
cpu->isar.id_isar6 = 0;
cpu->isar.id_aa64pfr0 = 0x00002222;
cpu->isar.id_aa64dfr0 = 0x10305106;
- cpu->isar.id_aa64isar0 = 0x00011120;
+ SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
cpu->isar.dbgdidr = 0x3516d000;
cpu->isar.dbgdevid = 0x00110f13;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 40bdfc851a58..42800b62ceb4 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7529,6 +7529,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
{
/* Register all the coprocessor registers based on feature bits */
CPUARMState *env = &cpu->env;
+ uint64_t *idregs = cpu->isar.idregs;
+
if (arm_feature(env, ARM_FEATURE_M)) {
/* M profile has no coprocessor registers */
return;
@@ -7718,7 +7720,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64zfr0 },
+ .resetvalue = GET_IDREG(idregs, ID_AA64ZFR0)},
{ .name = "ID_AA64SMFR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
@@ -7778,7 +7780,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64isar0 },
+ .resetvalue = GET_IDREG(idregs, ID_AA64ISAR0)},
{ .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 3b8bb5661f2b..c0cb81ea953c 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -26,6 +26,7 @@
#include "system/kvm_int.h"
#include "kvm_arm.h"
#include "cpu.h"
+#include "cpu-sysregs.h"
#include "trace.h"
#include "internals.h"
#include "hw/pci/pci.h"
@@ -336,6 +337,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ahcf->target = init.target;
ahcf->dtb_compatible = "arm,arm-v8";
+ int fd = fdarray[2];
err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
ARM64_SYS_REG(3, 0, 0, 4, 0));
@@ -367,8 +369,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ARM64_SYS_REG(3, 0, 0, 5, 0));
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1,
ARM64_SYS_REG(3, 0, 0, 5, 1));
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0,
- ARM64_SYS_REG(3, 0, 0, 6, 0));
+ err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR0_EL1);
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
ARM64_SYS_REG(3, 0, 0, 6, 1));
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2,
@@ -477,8 +478,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* enabled SVE support, which resulted in an error rather than RAZ.
* So only read the register if we set KVM_ARM_VCPU_SVE above.
*/
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
- ARM64_SYS_REG(3, 0, 0, 4, 4));
+ err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ZFR0_EL1);
}
}
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 93573ceeb1a8..6eea7ca2fff6 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -32,6 +32,7 @@
static void aarch64_a35_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,cortex-a35";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -66,7 +67,7 @@ static void aarch64_a35_initfn(Object *obj)
cpu->isar.id_aa64pfr1 = 0;
cpu->isar.id_aa64dfr0 = 0x10305106;
cpu->isar.id_aa64dfr1 = 0;
- cpu->isar.id_aa64isar0 = 0x00011120;
+ SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
cpu->isar.id_aa64isar1 = 0;
cpu->isar.id_aa64mmfr0 = 0x00101122;
cpu->isar.id_aa64mmfr1 = 0;
@@ -204,6 +205,7 @@ static const Property arm_cpu_lpa2_property =
static void aarch64_a55_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,cortex-a55";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -221,7 +223,7 @@ static void aarch64_a55_initfn(Object *obj)
cpu->ctr = 0x84448004; /* L1Ip = VIPT */
cpu->dcz_blocksize = 4; /* 64 bytes */
cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+ SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull);
cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
@@ -276,6 +278,7 @@ static void aarch64_a55_initfn(Object *obj)
static void aarch64_a72_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,cortex-a72";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -311,7 +314,7 @@ static void aarch64_a72_initfn(Object *obj)
cpu->isar.id_isar5 = 0x00011121;
cpu->isar.id_aa64pfr0 = 0x00002222;
cpu->isar.id_aa64dfr0 = 0x10305106;
- cpu->isar.id_aa64isar0 = 0x00011120;
+ SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
cpu->isar.id_aa64mmfr0 = 0x00001124;
cpu->isar.dbgdidr = 0x3516d000;
cpu->isar.dbgdevid = 0x01110f13;
@@ -335,6 +338,7 @@ static void aarch64_a72_initfn(Object *obj)
static void aarch64_a76_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,cortex-a76";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -352,7 +356,7 @@ static void aarch64_a76_initfn(Object *obj)
cpu->ctr = 0x8444C004;
cpu->dcz_blocksize = 4;
cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+ SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull);
cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
@@ -408,6 +412,7 @@ static void aarch64_a76_initfn(Object *obj)
static void aarch64_a64fx_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,a64fx";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -431,9 +436,9 @@ static void aarch64_a64fx_initfn(Object *obj)
cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
- cpu->isar.id_aa64isar0 = 0x0000000010211120;
+ SET_IDREG(idregs, ID_AA64ISAR0, 0x0000000010211120);
cpu->isar.id_aa64isar1 = 0x0000000000010001;
- cpu->isar.id_aa64zfr0 = 0x0000000000000000;
+ SET_IDREG(idregs, ID_AA64ZFR0, 0x0000000000000000);
cpu->clidr = 0x0000000080000023;
/* 64KB L1 dcache */
cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 256, 64 * KiB, 7);
@@ -581,6 +586,7 @@ static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu)
static void aarch64_neoverse_n1_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,neoverse-n1";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -598,7 +604,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
cpu->ctr = 0x8444c004;
cpu->dcz_blocksize = 4;
cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
+ SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull);
cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
@@ -656,6 +662,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
static void aarch64_neoverse_v1_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,neoverse-v1";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -676,7 +683,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->id_aa64afr1 = 0x00000000;
cpu->isar.id_aa64dfr0 = 0x000001f210305519ull;
cpu->isar.id_aa64dfr1 = 0x00000000;
- cpu->isar.id_aa64isar0 = 0x1011111110212120ull; /* with FEAT_RNG */
+ SET_IDREG(idregs, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG */
cpu->isar.id_aa64isar1 = 0x0011100001211032ull;
cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
@@ -735,7 +742,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043;
/* From 3.7.5 ID_AA64ZFR0_EL1 */
- cpu->isar.id_aa64zfr0 = 0x0000100000100000;
+ SET_IDREG(idregs, ID_AA64ZFR0, 0x0000100000100000);
cpu->sve_vq.supported = (1 << 0) /* 128bit */
| (1 << 1); /* 256bit */
@@ -882,6 +889,7 @@ static const ARMCPRegInfo cortex_a710_cp_reginfo[] = {
static void aarch64_a710_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,cortex-a710";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -919,12 +927,12 @@ static void aarch64_a710_initfn(Object *obj)
cpu->isar.id_pfr2 = 0x00000011;
cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
- cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */
+ SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
cpu->isar.id_aa64dfr0 = 0x000011f010305619ull;
cpu->isar.id_aa64dfr1 = 0;
cpu->id_aa64afr0 = 0;
cpu->id_aa64afr1 = 0;
- cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */
+ SET_IDREG(idregs, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */
cpu->isar.id_aa64isar1 = 0x0010111101211052ull;
cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
@@ -983,6 +991,7 @@ static const ARMCPRegInfo neoverse_n2_cp_reginfo[] = {
static void aarch64_neoverse_n2_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,neoverse-n2";
set_feature(&cpu->env, ARM_FEATURE_V8);
@@ -1020,12 +1029,12 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->isar.id_pfr2 = 0x00000011;
cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
- cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */
+ SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
cpu->isar.id_aa64dfr0 = 0x000011f210305619ull;
cpu->isar.id_aa64dfr1 = 0;
cpu->id_aa64afr0 = 0;
cpu->id_aa64afr1 = 0;
- cpu->isar.id_aa64isar0 = 0x1221111110212120ull; /* with Crypto and FEAT_RNG */
+ SET_IDREG(idregs, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto and FEAT_RNG */
cpu->isar.id_aa64isar1 = 0x0011111101211052ull;
cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
@@ -1083,6 +1092,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
void aarch64_max_tcg_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
uint64_t t;
uint32_t u;
@@ -1133,7 +1143,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, CTR_EL0, DIC, 1);
cpu->ctr = t;
- t = cpu->isar.id_aa64isar0;
+ t = GET_IDREG(idregs, ID_AA64ISAR0);
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */
t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */
@@ -1148,7 +1158,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */
t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
- cpu->isar.id_aa64isar0 = t;
+ SET_IDREG(idregs, ID_AA64ISAR0, t);
t = cpu->isar.id_aa64isar1;
t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
@@ -1242,7 +1252,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */
cpu->isar.id_aa64mmfr3 = t;
- t = cpu->isar.id_aa64zfr0;
+ t = GET_IDREG(idregs, ID_AA64ZFR0);
t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
@@ -1252,7 +1262,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
- cpu->isar.id_aa64zfr0 = t;
+ SET_IDREG(idregs, ID_AA64ZFR0, t);
t = cpu->isar.id_aa64dfr0;
t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 03/15] arm/cpu: Store aa64isar0 into the idregs arrays
2025-02-07 11:02 ` [PATCH 03/15] arm/cpu: Store aa64isar0 into the idregs arrays Cornelia Huck
@ 2025-02-07 18:46 ` Richard Henderson
2025-02-18 15:53 ` Eric Auger
0 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2025-02-07 18:46 UTC (permalink / raw)
To: Cornelia Huck, qemu-devel, qemu-arm, kvmarm
On 2/7/25 03:02, Cornelia Huck wrote:
> - t = cpu->isar.id_aa64zfr0;
> + t = GET_IDREG(idregs, ID_AA64ZFR0);
> t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
> t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */
> t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */
> @@ -1252,7 +1262,7 @@ void aarch64_max_tcg_initfn(Object *obj)
> t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
> t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
> t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
> - cpu->isar.id_aa64zfr0 = t;
> + SET_IDREG(idregs, ID_AA64ZFR0, t);
This doesn't belong to this patch.
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 03/15] arm/cpu: Store aa64isar0 into the idregs arrays
2025-02-07 18:46 ` Richard Henderson
@ 2025-02-18 15:53 ` Eric Auger
0 siblings, 0 replies; 29+ messages in thread
From: Eric Auger @ 2025-02-18 15:53 UTC (permalink / raw)
To: Richard Henderson, Cornelia Huck, qemu-devel, qemu-arm, kvmarm
On 2/7/25 7:46 PM, Richard Henderson wrote:
> On 2/7/25 03:02, Cornelia Huck wrote:
>> - t = cpu->isar.id_aa64zfr0;
>> + t = GET_IDREG(idregs, ID_AA64ZFR0);
>> t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
>> t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /*
>> FEAT_SVE_PMULL128 */
>> t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /*
>> FEAT_SVE_BitPerm */
>> @@ -1252,7 +1262,7 @@ void aarch64_max_tcg_initfn(Object *obj)
>> t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */
>> t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */
>> t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
>> - cpu->isar.id_aa64zfr0 = t;
>> + SET_IDREG(idregs, ID_AA64ZFR0, t);
>
> This doesn't belong to this patch.
Yes my fault, ID_AA64ZFR0 handling can easily be put in a separate patch
Eric
>
>
> r~
>
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 04/15] arm/cpu: Store aa64isar1/2 into the idregs array
2025-02-07 11:02 [PATCH 00/15] arm: rework id register storage Cornelia Huck
` (2 preceding siblings ...)
2025-02-07 11:02 ` [PATCH 03/15] arm/cpu: Store aa64isar0 into the idregs arrays Cornelia Huck
@ 2025-02-07 11:02 ` Cornelia Huck
2025-02-07 11:02 ` [PATCH 05/15] arm/cpu: Store aa64pfr0/1 " Cornelia Huck
` (10 subsequent siblings)
14 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-02-07 11:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-features.h | 42 +++++++++++++++++++--------------------
target/arm/cpu.c | 8 +++-----
target/arm/cpu.h | 2 --
target/arm/cpu64.c | 9 +++++----
target/arm/helper.c | 4 ++--
target/arm/kvm.c | 6 ++----
target/arm/tcg/cpu64.c | 24 +++++++++++-----------
7 files changed, 45 insertions(+), 50 deletions(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 9638c9428db3..2837c3e8c1c7 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -467,17 +467,17 @@ static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, JSCVT) != 0;
}
static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, FCMA) != 0;
}
static inline bool isar_feature_aa64_xs(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, XS) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, XS) != 0;
}
/*
@@ -501,9 +501,9 @@ isar_feature_pauth_feature(const ARMISARegisters *id)
* Architecturally, only one of {APA,API,APA3} may be active (non-zero)
* and the other two must be zero. Thus we may avoid conditionals.
*/
- return (FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) |
- FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, API) |
- FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3));
+ return (FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, APA) |
+ FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, API) |
+ FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR2, APA3));
}
static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
@@ -521,7 +521,7 @@ static inline bool isar_feature_aa64_pauth_qarma5(const ARMISARegisters *id)
* Return true if pauth is enabled with the architected QARMA5 algorithm.
* QEMU will always enable or disable both APA and GPA.
*/
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, APA) != 0;
}
static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id)
@@ -530,72 +530,72 @@ static inline bool isar_feature_aa64_pauth_qarma3(const ARMISARegisters *id)
* Return true if pauth is enabled with the architected QARMA3 algorithm.
* QEMU will always enable or disable both APA3 and GPA3.
*/
- return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, APA3) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR2, APA3) != 0;
}
static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, SB) != 0;
}
static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, SPECRES) != 0;
}
static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, FRINTTS) != 0;
}
static inline bool isar_feature_aa64_dcpop(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, DPB) != 0;
}
static inline bool isar_feature_aa64_dcpodp(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >= 2;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, DPB) >= 2;
}
static inline bool isar_feature_aa64_bf16(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, BF16) != 0;
}
static inline bool isar_feature_aa64_ebf16(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, BF16) > 1;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, BF16) > 1;
}
static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, LRCPC) != 0;
}
static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >= 2;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, LRCPC) >= 2;
}
static inline bool isar_feature_aa64_i8mm(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, I8MM) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR1, I8MM) != 0;
}
static inline bool isar_feature_aa64_wfxt(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, WFXT) >= 2;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR2, WFXT) >= 2;
}
static inline bool isar_feature_aa64_hbc(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, BC) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR2, BC) != 0;
}
static inline bool isar_feature_aa64_mops(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64isar2, ID_AA64ISAR2, MOPS);
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64ISAR2, MOPS);
}
static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 861b7f893c0c..d2f0eb1f78e4 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2146,9 +2146,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
uint64_t t;
uint32_t u;
- t = cpu->isar.id_aa64isar1;
- t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0);
- cpu->isar.id_aa64isar1 = t;
+ FIELD_DP64_IDREG(idregs, ID_AA64ISAR1, JSCVT, 0);
t = cpu->isar.id_aa64pfr0;
t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
@@ -2201,11 +2199,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0);
SET_IDREG(idregs, ID_AA64ISAR0, t);
- t = cpu->isar.id_aa64isar1;
+ t = GET_IDREG(idregs, ID_AA64ISAR1);
t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 0);
t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 0);
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0);
- cpu->isar.id_aa64isar1 = t;
+ SET_IDREG(idregs, ID_AA64ISAR1, t);
t = cpu->isar.id_aa64pfr0;
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index cbc1804dbd32..fb1c88b9ae91 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1067,8 +1067,6 @@ struct ArchCPU {
uint32_t dbgdidr;
uint32_t dbgdevid;
uint32_t dbgdevid1;
- uint64_t id_aa64isar1;
- uint64_t id_aa64isar2;
uint64_t id_aa64pfr0;
uint64_t id_aa64pfr1;
uint64_t id_aa64mmfr0;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f582a8ae6cd1..1780b2f8dbce 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -480,6 +480,7 @@ void aarch64_add_sme_properties(Object *obj)
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
{
ARMPauthFeature features = cpu_isar_feature(pauth_feature, cpu);
+ uint64_t *idregs = cpu->isar.idregs;
uint64_t isar1, isar2;
/*
@@ -490,13 +491,13 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
*
* Begin by disabling all fields.
*/
- isar1 = cpu->isar.id_aa64isar1;
+ isar1 = GET_IDREG(idregs, ID_AA64ISAR1);
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, 0);
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 0);
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, 0);
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 0);
- isar2 = cpu->isar.id_aa64isar2;
+ isar2 = GET_IDREG(idregs, ID_AA64ISAR2);
isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0);
isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0);
@@ -558,8 +559,8 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
}
}
- cpu->isar.id_aa64isar1 = isar1;
- cpu->isar.id_aa64isar2 = isar2;
+ SET_IDREG(idregs, ID_AA64ISAR1, isar1);
+ SET_IDREG(idregs, ID_AA64ISAR2, isar2);
}
static const Property arm_cpu_pauth_property =
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 42800b62ceb4..f4dd603cfb23 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7785,12 +7785,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64isar1 },
+ .resetvalue = GET_IDREG(idregs, ID_AA64ISAR1)},
{ .name = "ID_AA64ISAR2_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64isar2 },
+ .resetvalue = GET_IDREG(idregs, ID_AA64ISAR2)},
{ .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index c0cb81ea953c..34565de60690 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -370,10 +370,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1,
ARM64_SYS_REG(3, 0, 0, 5, 1));
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR0_EL1);
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
- ARM64_SYS_REG(3, 0, 0, 6, 1));
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2,
- ARM64_SYS_REG(3, 0, 0, 6, 2));
+ err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR1_EL1);
+ err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR2_EL1);
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0,
ARM64_SYS_REG(3, 0, 0, 7, 0));
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1,
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 6eea7ca2fff6..a287984b7ad0 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -68,7 +68,7 @@ static void aarch64_a35_initfn(Object *obj)
cpu->isar.id_aa64dfr0 = 0x10305106;
cpu->isar.id_aa64dfr1 = 0;
SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
- cpu->isar.id_aa64isar1 = 0;
+ SET_IDREG(idregs, ID_AA64ISAR1, 0);
cpu->isar.id_aa64mmfr0 = 0x00101122;
cpu->isar.id_aa64mmfr1 = 0;
cpu->clidr = 0x0a200023;
@@ -224,7 +224,7 @@ static void aarch64_a55_initfn(Object *obj)
cpu->dcz_blocksize = 4; /* 64 bytes */
cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull);
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+ SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull);
cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
@@ -357,7 +357,7 @@ static void aarch64_a76_initfn(Object *obj)
cpu->dcz_blocksize = 4;
cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull);
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+ SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull);
cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
@@ -437,7 +437,7 @@ static void aarch64_a64fx_initfn(Object *obj)
cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
SET_IDREG(idregs, ID_AA64ISAR0, 0x0000000010211120);
- cpu->isar.id_aa64isar1 = 0x0000000000010001;
+ SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000010001);
SET_IDREG(idregs, ID_AA64ZFR0, 0x0000000000000000);
cpu->clidr = 0x0000000080000023;
/* 64KB L1 dcache */
@@ -605,7 +605,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
cpu->dcz_blocksize = 4;
cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull);
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
+ SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull);
cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
@@ -684,7 +684,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->isar.id_aa64dfr0 = 0x000001f210305519ull;
cpu->isar.id_aa64dfr1 = 0x00000000;
SET_IDREG(idregs, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG */
- cpu->isar.id_aa64isar1 = 0x0011100001211032ull;
+ SET_IDREG(idregs, ID_AA64ISAR1, 0x0011000001211032ull);
cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull;
@@ -933,7 +933,7 @@ static void aarch64_a710_initfn(Object *obj)
cpu->id_aa64afr0 = 0;
cpu->id_aa64afr1 = 0;
SET_IDREG(idregs, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */
- cpu->isar.id_aa64isar1 = 0x0010111101211052ull;
+ SET_IDREG(idregs, ID_AA64ISAR1, 0x0010111101211052ull);
cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x1221011110101011ull;
@@ -1035,7 +1035,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->id_aa64afr0 = 0;
cpu->id_aa64afr1 = 0;
SET_IDREG(idregs, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto and FEAT_RNG */
- cpu->isar.id_aa64isar1 = 0x0011111101211052ull;
+ SET_IDREG(idregs, ID_AA64ISAR1, 0x0011111101211052ull);
cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x1221011112101011ull;
@@ -1160,7 +1160,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */
SET_IDREG(idregs, ID_AA64ISAR0, t);
- t = cpu->isar.id_aa64isar1;
+ t = GET_IDREG(idregs, ID_AA64ISAR1);
t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */
t = FIELD_DP64(t, ID_AA64ISAR1, APA, PauthFeat_FPACCOMBINED);
t = FIELD_DP64(t, ID_AA64ISAR1, API, 1);
@@ -1174,13 +1174,13 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
t = FIELD_DP64(t, ID_AA64ISAR1, XS, 1); /* FEAT_XS */
- cpu->isar.id_aa64isar1 = t;
+ SET_IDREG(idregs, ID_AA64ISAR1, t);
- t = cpu->isar.id_aa64isar2;
+ t = GET_IDREG(idregs, ID_AA64ISAR2);
t = FIELD_DP64(t, ID_AA64ISAR2, MOPS, 1); /* FEAT_MOPS */
t = FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */
t = FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */
- cpu->isar.id_aa64isar2 = t;
+ SET_IDREG(idregs, ID_AA64ISAR2, t);
t = cpu->isar.id_aa64pfr0;
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 05/15] arm/cpu: Store aa64pfr0/1 into the idregs array
2025-02-07 11:02 [PATCH 00/15] arm: rework id register storage Cornelia Huck
` (3 preceding siblings ...)
2025-02-07 11:02 ` [PATCH 04/15] arm/cpu: Store aa64isar1/2 into the idregs array Cornelia Huck
@ 2025-02-07 11:02 ` Cornelia Huck
2025-02-07 11:02 ` [PATCH 06/15] arm/cpu: Store aa64mmfr0-3 " Cornelia Huck
` (9 subsequent siblings)
14 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-02-07 11:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-features.h | 40 ++++++++++++++++-----------------
target/arm/cpu.c | 29 ++++++++----------------
target/arm/cpu.h | 2 --
target/arm/cpu64.c | 14 ++++--------
target/arm/helper.c | 6 ++---
target/arm/kvm.c | 24 +++++++++-----------
target/arm/tcg/cpu64.c | 47 ++++++++++++++++++---------------------
7 files changed, 68 insertions(+), 94 deletions(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 2837c3e8c1c7..fa5a524b5513 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -601,68 +601,68 @@ static inline bool isar_feature_aa64_mops(const ARMISARegisters *id)
static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)
{
/* We always set the AdvSIMD and FP fields identically. */
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) != 0xf;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, FP) != 0xf;
}
static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
{
/* We always set the AdvSIMD and FP fields identically wrt FP16. */
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, FP) == 1;
}
static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, EL0) >= 2;
}
static inline bool isar_feature_aa64_aa32_el1(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >= 2;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, EL1) >= 2;
}
static inline bool isar_feature_aa64_aa32_el2(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL2) >= 2;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, EL2) >= 2;
}
static inline bool isar_feature_aa64_ras(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, RAS) != 0;
}
static inline bool isar_feature_aa64_doublefault(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) >= 2;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, RAS) >= 2;
}
static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, SVE) != 0;
}
static inline bool isar_feature_aa64_sel2(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SEL2) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, SEL2) != 0;
}
static inline bool isar_feature_aa64_rme(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RME) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, RME) != 0;
}
static inline bool isar_feature_aa64_dit(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, DIT) != 0;
}
static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
{
- int key = FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2);
+ int key = FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR0, CSV2);
if (key >= 2) {
return true; /* FEAT_CSV2_2 */
}
if (key == 1) {
- key = FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC);
+ key = FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR1, CSV2_FRAC);
return key >= 2; /* FEAT_CSV2_1p2 */
}
return false;
@@ -670,37 +670,37 @@ static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id)
static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR1, SSBS) != 0;
}
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR1, BT) != 0;
}
static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR1, MTE) != 0;
}
static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR1, MTE) >= 2;
}
static inline bool isar_feature_aa64_mte3(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 3;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR1, MTE) >= 3;
}
static inline bool isar_feature_aa64_sme(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR1, SME) != 0;
}
static inline bool isar_feature_aa64_nmi(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, NMI) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64PFR1, NMI) != 0;
}
static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index d2f0eb1f78e4..3e7f2e495e68 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2143,14 +2143,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
}
if (!cpu->has_vfp) {
- uint64_t t;
uint32_t u;
FIELD_DP64_IDREG(idregs, ID_AA64ISAR1, JSCVT, 0);
- t = cpu->isar.id_aa64pfr0;
- t = FIELD_DP64(t, ID_AA64PFR0, FP, 0xf);
- cpu->isar.id_aa64pfr0 = t;
+ FIELD_DP64_IDREG(idregs, ID_AA64PFR0, FP, 0xf);
u = cpu->isar.id_isar6;
u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
@@ -2205,9 +2202,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 0);
SET_IDREG(idregs, ID_AA64ISAR1, t);
- t = cpu->isar.id_aa64pfr0;
- t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 0xf);
- cpu->isar.id_aa64pfr0 = t;
+ FIELD_DP64_IDREG(idregs, ID_AA64PFR0, ADVSIMD, 0xf);
u = cpu->isar.id_isar5;
u = FIELD_DP32(u, ID_ISAR5, AES, 0);
@@ -2349,12 +2344,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
*/
cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
- cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
- ID_AA64PFR0, EL3, 0);
+ FIELD_DP64_IDREG(idregs, ID_AA64PFR0, EL3, 0);
/* Disable the realm management extension, which requires EL3. */
- cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
- ID_AA64PFR0, RME, 0);
+ FIELD_DP64_IDREG(idregs, ID_AA64PFR0, RME, 0);
}
if (!cpu->has_el2) {
@@ -2389,8 +2382,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* Disable the hypervisor feature bits in the processor feature
* registers if we don't have EL2.
*/
- cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
- ID_AA64PFR0, EL2, 0);
+ FIELD_DP64_IDREG(idregs, ID_AA64PFR0, EL2, 0);
cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
ID_PFR1, VIRTUALIZATION, 0);
}
@@ -2411,8 +2403,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* This matches Cortex-A710 BROADCASTMTE input being LOW.
*/
if (tcg_enabled() && cpu->tag_memory == NULL) {
- cpu->isar.id_aa64pfr1 =
- FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
+ FIELD_DP64_IDREG(idregs, ID_AA64PFR1, MTE, 1);
}
/*
@@ -2420,7 +2411,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* enabled on the guest (i.e mte=off), clear guest's MTE bits."
*/
if (kvm_enabled() && !cpu->kvm_mte) {
- FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
+ FIELD_DP64_IDREG(idregs, ID_AA64PFR1, MTE, 0);
}
#endif
}
@@ -2459,13 +2450,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
cpu->isar.id_dfr0 =
FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0);
/* FEAT_AMU (Activity Monitors Extension) */
- cpu->isar.id_aa64pfr0 =
- FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0);
+ FIELD_DP64_IDREG(idregs, ID_AA64PFR0, AMU, 0);
cpu->isar.id_pfr0 =
FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0);
/* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */
- cpu->isar.id_aa64pfr0 =
- FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0);
+ FIELD_DP64_IDREG(idregs, ID_AA64PFR0, MPAM, 0);
}
/* MPU can be configured out of a PMSA CPU either by setting has-mpu
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index fb1c88b9ae91..36378b29a8d1 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1067,8 +1067,6 @@ struct ArchCPU {
uint32_t dbgdidr;
uint32_t dbgdevid;
uint32_t dbgdevid1;
- uint64_t id_aa64pfr0;
- uint64_t id_aa64pfr1;
uint64_t id_aa64mmfr0;
uint64_t id_aa64mmfr1;
uint64_t id_aa64mmfr2;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 1780b2f8dbce..1cb57d2e7b1e 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -288,16 +288,13 @@ static bool cpu_arm_get_sve(Object *obj, Error **errp)
static void cpu_arm_set_sve(Object *obj, bool value, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
- uint64_t t;
if (value && kvm_enabled() && !kvm_arm_sve_supported()) {
error_setg(errp, "'sve' feature not supported by KVM on this host");
return;
}
- t = cpu->isar.id_aa64pfr0;
- t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
- cpu->isar.id_aa64pfr0 = t;
+ FIELD_DP64_IDREG(&cpu->isar.idregs, ID_AA64PFR0, SVE, value);
}
void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
@@ -348,11 +345,8 @@ static bool cpu_arm_get_sme(Object *obj, Error **errp)
static void cpu_arm_set_sme(Object *obj, bool value, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
- uint64_t t;
- t = cpu->isar.id_aa64pfr1;
- t = FIELD_DP64(t, ID_AA64PFR1, SME, value);
- cpu->isar.id_aa64pfr1 = t;
+ FIELD_DP64_IDREG(&cpu->isar.idregs, ID_AA64PFR1, SME, value);
}
static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp)
@@ -654,7 +648,7 @@ static void aarch64_a57_initfn(Object *obj)
cpu->isar.id_isar4 = 0x00011142;
cpu->isar.id_isar5 = 0x00011121;
cpu->isar.id_isar6 = 0;
- cpu->isar.id_aa64pfr0 = 0x00002222;
+ SET_IDREG(idregs, ID_AA64PFR0, 0x00002222);
cpu->isar.id_aa64dfr0 = 0x10305106;
SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
cpu->isar.id_aa64mmfr0 = 0x00001124;
@@ -716,7 +710,7 @@ static void aarch64_a53_initfn(Object *obj)
cpu->isar.id_isar4 = 0x00011142;
cpu->isar.id_isar5 = 0x00011121;
cpu->isar.id_isar6 = 0;
- cpu->isar.id_aa64pfr0 = 0x00002222;
+ SET_IDREG(idregs, ID_AA64PFR0, 0x00002222);
cpu->isar.id_aa64dfr0 = 0x10305106;
SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f4dd603cfb23..ee5a683a1772 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6719,7 +6719,7 @@ static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = env_archcpu(env);
- uint64_t pfr0 = cpu->isar.id_aa64pfr0;
+ uint64_t pfr0 = GET_IDREG(&cpu->isar.idregs, ID_AA64PFR0);
if (env->gicv3state) {
pfr0 |= 1 << 24;
@@ -7693,7 +7693,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL1_R,
#ifdef CONFIG_USER_ONLY
.type = ARM_CP_CONST,
- .resetvalue = cpu->isar.id_aa64pfr0
+ .resetvalue = GET_IDREG(idregs, ID_AA64PFR0)
#else
.type = ARM_CP_NO_RAW,
.accessfn = access_aa64_tid3,
@@ -7705,7 +7705,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64pfr1},
+ .resetvalue = GET_IDREG(idregs, ID_AA64PFR1)},
{ .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 34565de60690..604ed8854dc8 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -339,8 +339,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ahcf->dtb_compatible = "arm,arm-v8";
int fd = fdarray[2];
- err = read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr0,
- ARM64_SYS_REG(3, 0, 0, 4, 0));
+ err = get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR0_EL1);
if (unlikely(err < 0)) {
/*
* Before v4.15, the kernel only exposed a limited number of system
@@ -358,11 +357,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* ??? Either of these sounds like too much effort just
* to work around running a modern host kernel.
*/
- ahcf->isar.id_aa64pfr0 = 0x00000011; /* EL1&0, AArch64 only */
+ SET_IDREG(&ahcf->isar.idregs, ID_AA64PFR0, 0x00000011); /* EL1&0, AArch64 only */
err = 0;
} else {
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1,
- ARM64_SYS_REG(3, 0, 0, 4, 1));
+ err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR1_EL1);
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0,
ARM64_SYS_REG(3, 0, 0, 4, 5));
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0,
@@ -388,10 +386,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* than skipping the reads and leaving 0, as we must avoid
* considering the values in every case.
*/
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0,
- ARM64_SYS_REG(3, 0, 0, 1, 0));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
- ARM64_SYS_REG(3, 0, 0, 1, 1));
+ err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR0_EL1);
+ err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR1_EL1);
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
ARM64_SYS_REG(3, 0, 0, 1, 2));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
@@ -442,14 +438,14 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
* arch/arm64/kvm/sys_regs.c:trap_dbgidr() does.
* We only do this if the CPU supports AArch32 at EL1.
*/
- if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >= 2) {
- int wrps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, WRPS);
- int brps = FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, BRPS);
+ if (FIELD_EX32_IDREG(&ahcf->isar.idregs, ID_AA64PFR0, EL1) >= 2) {
+ int wrps = FIELD_EX64_IDREG(&ahcf->isar.idregs, ID_AA64DFR0, WRPS);
+ int brps = FIELD_EX64_IDREG(&ahcf->isar.idregs, ID_AA64DFR0, BRPS);
int ctx_cmps =
- FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS);
+ FIELD_EX64_IDREG(&ahcf->isar.idregs, ID_AA64DFR0, CTX_CMPS);
int version = 6; /* ARMv8 debug architecture */
bool has_el3 =
- !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3);
+ !!FIELD_EX32_IDREG(&ahcf->isar.idregs, ID_AA64PFR0, EL3);
uint32_t dbgdidr = 0;
dbgdidr = FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps);
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index a287984b7ad0..ab5a57b7590f 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -63,8 +63,8 @@ static void aarch64_a35_initfn(Object *obj)
cpu->isar.id_isar3 = 0x01112131;
cpu->isar.id_isar4 = 0x00011142;
cpu->isar.id_isar5 = 0x00011121;
- cpu->isar.id_aa64pfr0 = 0x00002222;
- cpu->isar.id_aa64pfr1 = 0;
+ SET_IDREG(idregs, ID_AA64PFR0, 0x00002222);
+ SET_IDREG(idregs, ID_AA64PFR1, 0);
cpu->isar.id_aa64dfr0 = 0x10305106;
cpu->isar.id_aa64dfr1 = 0;
SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
@@ -158,11 +158,8 @@ static bool cpu_arm_get_rme(Object *obj, Error **errp)
static void cpu_arm_set_rme(Object *obj, bool value, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
- uint64_t t;
- t = cpu->isar.id_aa64pfr0;
- t = FIELD_DP64(t, ID_AA64PFR0, RME, value);
- cpu->isar.id_aa64pfr0 = t;
+ FIELD_DP64_IDREG(&cpu->isar.idregs, ID_AA64PFR0, RME, value);
}
static void cpu_max_set_l0gptsz(Object *obj, Visitor *v, const char *name,
@@ -228,8 +225,8 @@ static void aarch64_a55_initfn(Object *obj)
cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
- cpu->isar.id_aa64pfr0 = 0x0000000010112222ull;
- cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
+ SET_IDREG(idregs, ID_AA64PFR0, 0x0000000010112222ull);
+ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_dfr0 = 0x04010088;
cpu->isar.id_isar0 = 0x02101110;
@@ -312,7 +309,7 @@ static void aarch64_a72_initfn(Object *obj)
cpu->isar.id_isar3 = 0x01112131;
cpu->isar.id_isar4 = 0x00011142;
cpu->isar.id_isar5 = 0x00011121;
- cpu->isar.id_aa64pfr0 = 0x00002222;
+ SET_IDREG(idregs, ID_AA64PFR0, 0x00002222);
cpu->isar.id_aa64dfr0 = 0x10305106;
SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
cpu->isar.id_aa64mmfr0 = 0x00001124;
@@ -361,8 +358,8 @@ static void aarch64_a76_initfn(Object *obj)
cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
- cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
+ SET_IDREG(idregs, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
+ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_dfr0 = 0x04010088;
cpu->isar.id_isar0 = 0x02101110;
@@ -427,8 +424,8 @@ static void aarch64_a64fx_initfn(Object *obj)
cpu->revidr = 0x00000000;
cpu->ctr = 0x86668006;
cpu->reset_sctlr = 0x30000180;
- cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
- cpu->isar.id_aa64pfr1 = 0x0000000000000000;
+ SET_IDREG(idregs, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions */
+ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000000);
cpu->isar.id_aa64dfr0 = 0x0000000010305408;
cpu->isar.id_aa64dfr1 = 0x0000000000000000;
cpu->id_aa64afr0 = 0x0000000000000000;
@@ -609,8 +606,8 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
- cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
+ SET_IDREG(idregs, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
+ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_dfr0 = 0x04010088;
cpu->isar.id_isar0 = 0x02101110;
@@ -688,8 +685,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull;
- cpu->isar.id_aa64pfr0 = 0x1101110120111112ull; /* GIC filled in later */
- cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
+ SET_IDREG(idregs, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in later */
+ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_dfr0 = 0x15011099;
cpu->isar.id_isar0 = 0x02101110;
@@ -925,8 +922,8 @@ static void aarch64_a710_initfn(Object *obj)
cpu->isar.mvfr1 = 0x13211111;
cpu->isar.mvfr2 = 0x00000043;
cpu->isar.id_pfr2 = 0x00000011;
- cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
- cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
+ SET_IDREG(idregs, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
+ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000221ull);
SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
cpu->isar.id_aa64dfr0 = 0x000011f010305619ull;
cpu->isar.id_aa64dfr1 = 0;
@@ -1027,8 +1024,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->isar.mvfr1 = 0x13211111;
cpu->isar.mvfr2 = 0x00000043;
cpu->isar.id_pfr2 = 0x00000011;
- cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */
- cpu->isar.id_aa64pfr1 = 0x0000000000000221ull;
+ SET_IDREG(idregs, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
+ SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000221ull);
SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
cpu->isar.id_aa64dfr0 = 0x000011f210305619ull;
cpu->isar.id_aa64dfr1 = 0;
@@ -1182,7 +1179,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */
SET_IDREG(idregs, ID_AA64ISAR2, t);
- t = cpu->isar.id_aa64pfr0;
+ t = GET_IDREG(idregs, ID_AA64PFR0);
t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */
t = FIELD_DP64(t, ID_AA64PFR0, RAS, 2); /* FEAT_RASv1p1 + FEAT_DoubleFault */
@@ -1191,9 +1188,9 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 3); /* FEAT_CSV2_3 */
t = FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */
- cpu->isar.id_aa64pfr0 = t;
+ SET_IDREG(idregs, ID_AA64PFR0, t);
- t = cpu->isar.id_aa64pfr1;
+ t = GET_IDREG(idregs, ID_AA64PFR1);
t = FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */
t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */
/*
@@ -1206,7 +1203,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64PFR1, SME, 1); /* FEAT_SME */
t = FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */
t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */
- cpu->isar.id_aa64pfr1 = t;
+ SET_IDREG(idregs, ID_AA64PFR1, t);
t = cpu->isar.id_aa64mmfr0;
t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 06/15] arm/cpu: Store aa64mmfr0-3 into the idregs array
2025-02-07 11:02 [PATCH 00/15] arm: rework id register storage Cornelia Huck
` (4 preceding siblings ...)
2025-02-07 11:02 ` [PATCH 05/15] arm/cpu: Store aa64pfr0/1 " Cornelia Huck
@ 2025-02-07 11:02 ` Cornelia Huck
2025-02-07 11:02 ` [PATCH 07/15] arm/cpu: Store aa64dfr0/1 " Cornelia Huck
` (8 subsequent siblings)
14 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-02-07 11:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-features.h | 72 +++++++++++++++++++--------------------
target/arm/cpu.h | 4 ---
target/arm/cpu64.c | 8 ++---
target/arm/helper.c | 8 ++---
target/arm/kvm.c | 12 +++----
target/arm/ptw.c | 6 ++--
target/arm/tcg/cpu64.c | 64 +++++++++++++++++-----------------
7 files changed, 82 insertions(+), 92 deletions(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index fa5a524b5513..a26b05cb9804 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -705,187 +705,187 @@ static inline bool isar_feature_aa64_nmi(const ARMISARegisters *id)
static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)
{
- return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 1;
+ return FIELD_SEX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN4) >= 1;
}
static inline bool isar_feature_aa64_tgran4_2_lpa2(const ARMISARegisters *id)
{
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
+ unsigned t = FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN4_2);
return t >= 3 || (t == 0 && isar_feature_aa64_tgran4_lpa2(id));
}
static inline bool isar_feature_aa64_tgran16_lpa2(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 2;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN16) >= 2;
}
static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
{
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
+ unsigned t = FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN16_2);
return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
}
static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id)
{
- return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0;
+ return FIELD_SEX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN4) >= 0;
}
static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN16) >= 1;
}
static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id)
{
- return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0;
+ return FIELD_SEX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN64) >= 0;
}
static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id)
{
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
+ unsigned t = FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN4_2);
return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id));
}
static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id)
{
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
+ unsigned t = FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN16_2);
return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id));
}
static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
{
- unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2);
+ unsigned t = FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, TGRAN64_2);
return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
}
static inline bool isar_feature_aa64_fgt(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, FGT) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, FGT) != 0;
}
static inline bool isar_feature_aa64_ecv_traps(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, ECV) > 0;
}
static inline bool isar_feature_aa64_ecv(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, ECV) > 1;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR0, ECV) > 1;
}
static inline bool isar_feature_aa64_vh(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, VH) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, VH) != 0;
}
static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, LO) != 0;
}
static inline bool isar_feature_aa64_pan(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, PAN) != 0;
}
static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, PAN) >= 2;
}
static inline bool isar_feature_aa64_pan3(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 3;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, PAN) >= 3;
}
static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, HCX) != 0;
}
static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, TIDCP1) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, TIDCP1) != 0;
}
static inline bool isar_feature_aa64_cmow(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, CMOW) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, CMOW) != 0;
}
static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, HAFDBS) != 0;
}
static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, HAFDBS) >= 2;
}
static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR1, XNX) != 0;
}
static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, UAO) != 0;
}
static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, ST) != 0;
}
static inline bool isar_feature_aa64_lse2(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, AT) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, AT) != 0;
}
static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, FWB) != 0;
}
static inline bool isar_feature_aa64_ids(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, IDS) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, IDS) != 0;
}
static inline bool isar_feature_aa64_half_evt(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 1;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, EVT) >= 1;
}
static inline bool isar_feature_aa64_evt(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, EVT) >= 2;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, EVT) >= 2;
}
static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, CCIDX) != 0;
}
static inline bool isar_feature_aa64_lva(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, VARANGE) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, VARANGE) != 0;
}
static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, E0PD) != 0;
}
static inline bool isar_feature_aa64_nv(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) != 0;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, NV) != 0;
}
static inline bool isar_feature_aa64_nv2(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, NV) >= 2;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64MMFR2, NV) >= 2;
}
static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 36378b29a8d1..fbbec43dbdac 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1067,10 +1067,6 @@ struct ArchCPU {
uint32_t dbgdidr;
uint32_t dbgdevid;
uint32_t dbgdevid1;
- uint64_t id_aa64mmfr0;
- uint64_t id_aa64mmfr1;
- uint64_t id_aa64mmfr2;
- uint64_t id_aa64mmfr3;
uint64_t id_aa64dfr0;
uint64_t id_aa64dfr1;
uint64_t id_aa64smfr0;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 1cb57d2e7b1e..ba39b8cc1ee0 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -601,12 +601,12 @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
return;
}
- t = cpu->isar.id_aa64mmfr0;
+ t = GET_IDREG(&cpu->isar.idregs, ID_AA64MMFR0);
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 */
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 */
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2 */
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2 */
- cpu->isar.id_aa64mmfr0 = t;
+ SET_IDREG(&cpu->isar.idregs, ID_AA64MMFR0, t);
}
static void aarch64_a57_initfn(Object *obj)
@@ -651,7 +651,7 @@ static void aarch64_a57_initfn(Object *obj)
SET_IDREG(idregs, ID_AA64PFR0, 0x00002222);
cpu->isar.id_aa64dfr0 = 0x10305106;
SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
- cpu->isar.id_aa64mmfr0 = 0x00001124;
+ SET_IDREG(idregs, ID_AA64MMFR0, 0x00001124);
cpu->isar.dbgdidr = 0x3516d000;
cpu->isar.dbgdevid = 0x01110f13;
cpu->isar.dbgdevid1 = 0x2;
@@ -713,7 +713,7 @@ static void aarch64_a53_initfn(Object *obj)
SET_IDREG(idregs, ID_AA64PFR0, 0x00002222);
cpu->isar.id_aa64dfr0 = 0x10305106;
SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
- cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
+ SET_IDREG(idregs, ID_AA64MMFR0, 0x00001122); /* 40 bit physical addr */
cpu->isar.dbgdidr = 0x3516d000;
cpu->isar.dbgdevid = 0x00110f13;
cpu->isar.dbgdevid1 = 0x1;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ee5a683a1772..d1d9a0d53f08 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7820,22 +7820,22 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64mmfr0 },
+ .resetvalue = GET_IDREG(idregs, ID_AA64MMFR0)},
{ .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64mmfr1 },
+ .resetvalue = GET_IDREG(idregs, ID_AA64MMFR1) },
{ .name = "ID_AA64MMFR2_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64mmfr2 },
+ .resetvalue = GET_IDREG(idregs, ID_AA64MMFR2) },
{ .name = "ID_AA64MMFR3_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64mmfr3 },
+ .resetvalue = GET_IDREG(idregs, ID_AA64MMFR3) },
{ .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 604ed8854dc8..87b5e7cec118 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -370,14 +370,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR0_EL1);
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR1_EL1);
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR2_EL1);
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0,
- ARM64_SYS_REG(3, 0, 0, 7, 0));
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1,
- ARM64_SYS_REG(3, 0, 0, 7, 1));
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr2,
- ARM64_SYS_REG(3, 0, 0, 7, 2));
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr3,
- ARM64_SYS_REG(3, 0, 0, 7, 3));
+ err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64MMFR0_EL1);
+ err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64MMFR1_EL1);
+ err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64MMFR2_EL1);
+ err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64MMFR3_EL1);
/*
* Note that if AArch32 support is not present in the host,
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 64bb6878a48a..f5d294cfb75c 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -123,7 +123,7 @@ unsigned int arm_pamax(ARMCPU *cpu)
{
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
unsigned int parange =
- FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
+ FIELD_EX64_IDREG(&cpu->isar.idregs, ID_AA64MMFR0, PARANGE);
/*
* id_aa64mmfr0 is a read-only register so values outside of the
@@ -333,7 +333,7 @@ static bool granule_protection_check(CPUARMState *env, uint64_t paddress,
* physical address size is invalid.
*/
pps = FIELD_EX64(gpccr, GPCCR, PPS);
- if (pps > FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE)) {
+ if (pps > FIELD_EX64_IDREG(&cpu->isar.idregs, ID_AA64MMFR0, PARANGE)) {
goto fault_walk;
}
pps = pamax_map[pps];
@@ -1735,7 +1735,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw,
* ID_AA64MMFR0 is a read-only register so values outside of the
* supported mappings can be considered an implementation error.
*/
- ps = FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
+ ps = FIELD_EX64_IDREG(&cpu->isar.idregs, ID_AA64MMFR0, PARANGE);
ps = MIN(ps, param.ps);
assert(ps < ARRAY_SIZE(pamax_map));
outputsize = pamax_map[ps];
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index ab5a57b7590f..0f98c6981380 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -69,8 +69,8 @@ static void aarch64_a35_initfn(Object *obj)
cpu->isar.id_aa64dfr1 = 0;
SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
SET_IDREG(idregs, ID_AA64ISAR1, 0);
- cpu->isar.id_aa64mmfr0 = 0x00101122;
- cpu->isar.id_aa64mmfr1 = 0;
+ SET_IDREG(idregs, ID_AA64MMFR0, 0x00101122);
+ SET_IDREG(idregs, ID_AA64MMFR1, 0);
cpu->clidr = 0x0a200023;
cpu->dcz_blocksize = 4;
@@ -222,9 +222,9 @@ static void aarch64_a55_initfn(Object *obj)
cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull);
SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull);
- cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+ SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101122ull);
+ SET_IDREG(idregs, ID_AA64MMFR1, 0x0000000010212122ull);
+ SET_IDREG(idregs, ID_AA64MMFR2, 0x0000000000001011ull);
SET_IDREG(idregs, ID_AA64PFR0, 0x0000000010112222ull);
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
@@ -312,7 +312,7 @@ static void aarch64_a72_initfn(Object *obj)
SET_IDREG(idregs, ID_AA64PFR0, 0x00002222);
cpu->isar.id_aa64dfr0 = 0x10305106;
SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
- cpu->isar.id_aa64mmfr0 = 0x00001124;
+ SET_IDREG(idregs, ID_AA64MMFR0, 0x00001124);
cpu->isar.dbgdidr = 0x3516d000;
cpu->isar.dbgdevid = 0x01110f13;
cpu->isar.dbgdevid1 = 0x2;
@@ -355,9 +355,9 @@ static void aarch64_a76_initfn(Object *obj)
cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull);
SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull);
- cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+ SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101122ull);
+ SET_IDREG(idregs, ID_AA64MMFR1, 0x0000000010212122ull);
+ SET_IDREG(idregs, ID_AA64MMFR2, 0x0000000000001011ull);
SET_IDREG(idregs, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
@@ -430,9 +430,9 @@ static void aarch64_a64fx_initfn(Object *obj)
cpu->isar.id_aa64dfr1 = 0x0000000000000000;
cpu->id_aa64afr0 = 0x0000000000000000;
cpu->id_aa64afr1 = 0x0000000000000000;
- cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
- cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
+ SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000001122);
+ SET_IDREG(idregs, ID_AA64MMFR1, 0x0000000011212100);
+ SET_IDREG(idregs, ID_AA64MMFR2, 0x0000000000001011);
SET_IDREG(idregs, ID_AA64ISAR0, 0x0000000010211120);
SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000010001);
SET_IDREG(idregs, ID_AA64ZFR0, 0x0000000000000000);
@@ -603,9 +603,9 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull);
SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull);
- cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
+ SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101125ull);
+ SET_IDREG(idregs, ID_AA64MMFR1, 0x0000000010212122ull);
+ SET_IDREG(idregs, ID_AA64MMFR2, 0x0000000000001011ull);
SET_IDREG(idregs, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
@@ -682,9 +682,9 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->isar.id_aa64dfr1 = 0x00000000;
SET_IDREG(idregs, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG */
SET_IDREG(idregs, ID_AA64ISAR1, 0x0011000001211032ull);
- cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull;
+ SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101125ull);
+ SET_IDREG(idregs, ID_AA64MMFR1, 0x0000000010212122ull),
+ SET_IDREG(idregs, ID_AA64MMFR2, 0x0220011102101011ull),
SET_IDREG(idregs, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in later */
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
@@ -931,9 +931,9 @@ static void aarch64_a710_initfn(Object *obj)
cpu->id_aa64afr1 = 0;
SET_IDREG(idregs, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */
SET_IDREG(idregs, ID_AA64ISAR1, 0x0010111101211052ull);
- cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x1221011110101011ull;
+ SET_IDREG(idregs, ID_AA64MMFR0, 0x0000022200101122ull);
+ SET_IDREG(idregs, ID_AA64MMFR1, 0x0000000010212122ull);
+ SET_IDREG(idregs, ID_AA64MMFR2, 0x1221011110101011ull);
cpu->clidr = 0x0000001482000023ull;
cpu->gm_blocksize = 4;
cpu->ctr = 0x000000049444c004ull;
@@ -1033,9 +1033,9 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->id_aa64afr1 = 0;
SET_IDREG(idregs, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto and FEAT_RNG */
SET_IDREG(idregs, ID_AA64ISAR1, 0x0011111101211052ull);
- cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull;
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
- cpu->isar.id_aa64mmfr2 = 0x1221011112101011ull;
+ SET_IDREG(idregs, ID_AA64MMFR0, 0x0000022200101125ull);
+ SET_IDREG(idregs, ID_AA64MMFR1, 0x0000000010212122ull);
+ SET_IDREG(idregs, ID_AA64MMFR2, 0x1221011112101011ull);
cpu->clidr = 0x0000001482000023ull;
cpu->gm_blocksize = 4;
cpu->ctr = 0x00000004b444c004ull;
@@ -1205,7 +1205,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */
SET_IDREG(idregs, ID_AA64PFR1, t);
- t = cpu->isar.id_aa64mmfr0;
+ t = GET_IDREG(idregs, ID_AA64MMFR0);
t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 6); /* FEAT_LPA: 52 bits */
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 1); /* 16k pages supported */
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 2); /* 16k stage2 supported */
@@ -1213,9 +1213,9 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 2); /* 4k stage2 supported */
t = FIELD_DP64(t, ID_AA64MMFR0, FGT, 1); /* FEAT_FGT */
t = FIELD_DP64(t, ID_AA64MMFR0, ECV, 2); /* FEAT_ECV */
- cpu->isar.id_aa64mmfr0 = t;
+ SET_IDREG(idregs, ID_AA64MMFR0, t);
- t = cpu->isar.id_aa64mmfr1;
+ t = GET_IDREG(idregs, ID_AA64MMFR1);
t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */
t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */
t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */
@@ -1227,9 +1227,9 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */
t = FIELD_DP64(t, ID_AA64MMFR1, TIDCP1, 1); /* FEAT_TIDCP1 */
t = FIELD_DP64(t, ID_AA64MMFR1, CMOW, 1); /* FEAT_CMOW */
- cpu->isar.id_aa64mmfr1 = t;
+ SET_IDREG(idregs, ID_AA64MMFR1, t);
- t = cpu->isar.id_aa64mmfr2;
+ t = GET_IDREG(idregs, ID_AA64MMFR2);
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */
t = FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */
@@ -1243,11 +1243,9 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */
t = FIELD_DP64(t, ID_AA64MMFR2, EVT, 2); /* FEAT_EVT */
t = FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */
- cpu->isar.id_aa64mmfr2 = t;
+ SET_IDREG(idregs, ID_AA64MMFR2, t);
- t = cpu->isar.id_aa64mmfr3;
- t = FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */
- cpu->isar.id_aa64mmfr3 = t;
+ FIELD_DP64_IDREG(idregs, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */
t = GET_IDREG(idregs, ID_AA64ZFR0);
t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 07/15] arm/cpu: Store aa64dfr0/1 into the idregs array
2025-02-07 11:02 [PATCH 00/15] arm: rework id register storage Cornelia Huck
` (5 preceding siblings ...)
2025-02-07 11:02 ` [PATCH 06/15] arm/cpu: Store aa64mmfr0-3 " Cornelia Huck
@ 2025-02-07 11:02 ` Cornelia Huck
2025-02-07 11:02 ` [PATCH 08/15] arm/cpu: Store aa64smfr0 " Cornelia Huck
` (7 subsequent siblings)
14 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-02-07 11:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-features.h | 16 ++++++++--------
target/arm/cpu.c | 15 +++++----------
target/arm/cpu.h | 2 --
target/arm/cpu64.c | 4 ++--
target/arm/helper.c | 4 ++--
target/arm/internals.h | 6 +++---
target/arm/kvm.c | 6 ++----
target/arm/tcg/cpu64.c | 33 +++++++++++++++++----------------
8 files changed, 39 insertions(+), 47 deletions(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index a26b05cb9804..05de9e0d9932 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -890,30 +890,30 @@ static inline bool isar_feature_aa64_nv2(const ARMISARegisters *id)
static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
- FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) >= 4 &&
+ FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) != 0xf;
}
static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 &&
- FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) >= 5 &&
+ FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) != 0xf;
}
static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 &&
- FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) >= 6 &&
+ FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, PMUVER) != 0xf;
}
static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >= 8;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64DFR0, DEBUGVER) >= 8;
}
static inline bool isar_feature_aa64_doublelock(const ARMISARegisters *id)
{
- return FIELD_SEX64(id->id_aa64dfr0, ID_AA64DFR0, DOUBLELOCK) >= 0;
+ return FIELD_SEX64_IDREG(&id->idregs, ID_AA64DFR0, DOUBLELOCK) >= 0;
}
static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 3e7f2e495e68..8f2d58cffbfd 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2370,8 +2370,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
cpu);
#endif
} else {
- cpu->isar.id_aa64dfr0 =
- FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0);
+ FIELD_DP64_IDREG(idregs, ID_AA64DFR0, PMUVER, 0);
cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
cpu->pmceid0 = 0;
cpu->pmceid1 = 0;
@@ -2431,19 +2430,15 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* try to access the non-existent system registers for them.
*/
/* FEAT_SPE (Statistical Profiling Extension) */
- cpu->isar.id_aa64dfr0 =
- FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0);
+ FIELD_DP64_IDREG(idregs, ID_AA64DFR0, PMSVER, 0);
/* FEAT_TRBE (Trace Buffer Extension) */
- cpu->isar.id_aa64dfr0 =
- FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEBUFFER, 0);
+ FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEBUFFER, 0);
/* FEAT_TRF (Self-hosted Trace Extension) */
- cpu->isar.id_aa64dfr0 =
- FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0);
+ FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEFILT, 0);
cpu->isar.id_dfr0 =
FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0);
/* Trace Macrocell system register access */
- cpu->isar.id_aa64dfr0 =
- FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0);
+ FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEVER, 0);
cpu->isar.id_dfr0 =
FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0);
/* Memory mapped trace */
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index fbbec43dbdac..99b0c2a4b39d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1067,8 +1067,6 @@ struct ArchCPU {
uint32_t dbgdidr;
uint32_t dbgdevid;
uint32_t dbgdevid1;
- uint64_t id_aa64dfr0;
- uint64_t id_aa64dfr1;
uint64_t id_aa64smfr0;
uint64_t reset_pmcr_el0;
uint64_t idregs[NUM_ID_IDX];
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index ba39b8cc1ee0..22286a1844a4 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -649,7 +649,7 @@ static void aarch64_a57_initfn(Object *obj)
cpu->isar.id_isar5 = 0x00011121;
cpu->isar.id_isar6 = 0;
SET_IDREG(idregs, ID_AA64PFR0, 0x00002222);
- cpu->isar.id_aa64dfr0 = 0x10305106;
+ SET_IDREG(idregs, ID_AA64DFR0, 0x10305106);
SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
SET_IDREG(idregs, ID_AA64MMFR0, 0x00001124);
cpu->isar.dbgdidr = 0x3516d000;
@@ -711,7 +711,7 @@ static void aarch64_a53_initfn(Object *obj)
cpu->isar.id_isar5 = 0x00011121;
cpu->isar.id_isar6 = 0;
SET_IDREG(idregs, ID_AA64PFR0, 0x00002222);
- cpu->isar.id_aa64dfr0 = 0x10305106;
+ SET_IDREG(idregs, ID_AA64DFR0, 0x10305106);
SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
SET_IDREG(idregs, ID_AA64MMFR0, 0x00001122); /* 40 bit physical addr */
cpu->isar.dbgdidr = 0x3516d000;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d1d9a0d53f08..437ba8a53934 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7740,12 +7740,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64dfr0 },
+ .resetvalue = GET_IDREG(idregs, ID_AA64DFR0) },
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64dfr1 },
+ .resetvalue = GET_IDREG(idregs, ID_AA64DFR1) },
{ .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 863a84edf81c..af2590964754 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1035,7 +1035,7 @@ static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
static inline int arm_num_brps(ARMCPU *cpu)
{
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
- return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1;
+ return FIELD_EX64_IDREG(&cpu->isar.idregs, ID_AA64DFR0, BRPS) + 1;
} else {
return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1;
}
@@ -1049,7 +1049,7 @@ static inline int arm_num_brps(ARMCPU *cpu)
static inline int arm_num_wrps(ARMCPU *cpu)
{
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
- return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1;
+ return FIELD_EX64_IDREG(&cpu->isar.idregs, ID_AA64DFR0, WRPS) + 1;
} else {
return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1;
}
@@ -1063,7 +1063,7 @@ static inline int arm_num_wrps(ARMCPU *cpu)
static inline int arm_num_ctx_cmps(ARMCPU *cpu)
{
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
- return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + 1;
+ return FIELD_EX64_IDREG(&cpu->isar.idregs, ID_AA64DFR0, CTX_CMPS) + 1;
} else {
return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1;
}
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 87b5e7cec118..7597c84ff2ce 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -363,10 +363,8 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR1_EL1);
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0,
ARM64_SYS_REG(3, 0, 0, 4, 5));
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0,
- ARM64_SYS_REG(3, 0, 0, 5, 0));
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1,
- ARM64_SYS_REG(3, 0, 0, 5, 1));
+ err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64DFR0_EL1);
+ err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64DFR1_EL1);
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR0_EL1);
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR1_EL1);
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR2_EL1);
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 0f98c6981380..ce4cb449a381 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -65,8 +65,8 @@ static void aarch64_a35_initfn(Object *obj)
cpu->isar.id_isar5 = 0x00011121;
SET_IDREG(idregs, ID_AA64PFR0, 0x00002222);
SET_IDREG(idregs, ID_AA64PFR1, 0);
- cpu->isar.id_aa64dfr0 = 0x10305106;
- cpu->isar.id_aa64dfr1 = 0;
+ SET_IDREG(idregs, ID_AA64DFR0, 0x10305106);
+ SET_IDREG(idregs, ID_AA64DFR1, 0);
SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
SET_IDREG(idregs, ID_AA64ISAR1, 0);
SET_IDREG(idregs, ID_AA64MMFR0, 0x00101122);
@@ -219,7 +219,7 @@ static void aarch64_a55_initfn(Object *obj)
cpu->clidr = 0x82000023;
cpu->ctr = 0x84448004; /* L1Ip = VIPT */
cpu->dcz_blocksize = 4; /* 64 bytes */
- cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
+ SET_IDREG(idregs, ID_AA64DFR0, 0x0000000010305408ull);
SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull);
SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull);
SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101122ull);
@@ -310,7 +310,7 @@ static void aarch64_a72_initfn(Object *obj)
cpu->isar.id_isar4 = 0x00011142;
cpu->isar.id_isar5 = 0x00011121;
SET_IDREG(idregs, ID_AA64PFR0, 0x00002222);
- cpu->isar.id_aa64dfr0 = 0x10305106;
+ SET_IDREG(idregs, ID_AA64DFR0, 0x10305106);
SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
SET_IDREG(idregs, ID_AA64MMFR0, 0x00001124);
cpu->isar.dbgdidr = 0x3516d000;
@@ -352,7 +352,7 @@ static void aarch64_a76_initfn(Object *obj)
cpu->clidr = 0x82000023;
cpu->ctr = 0x8444C004;
cpu->dcz_blocksize = 4;
- cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
+ SET_IDREG(idregs, ID_AA64DFR0, 0x0000000010305408ull),
SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull);
SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull);
SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101122ull);
@@ -426,8 +426,8 @@ static void aarch64_a64fx_initfn(Object *obj)
cpu->reset_sctlr = 0x30000180;
SET_IDREG(idregs, ID_AA64PFR0, 0x0000000101111111); /* No RAS Extensions */
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000000);
- cpu->isar.id_aa64dfr0 = 0x0000000010305408;
- cpu->isar.id_aa64dfr1 = 0x0000000000000000;
+ SET_IDREG(idregs, ID_AA64DFR0, 0x0000000010305408),
+ SET_IDREG(idregs, ID_AA64DFR1, 0x0000000000000000),
cpu->id_aa64afr0 = 0x0000000000000000;
cpu->id_aa64afr1 = 0x0000000000000000;
SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000001122);
@@ -600,7 +600,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
cpu->clidr = 0x82000023;
cpu->ctr = 0x8444c004;
cpu->dcz_blocksize = 4;
- cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
+ SET_IDREG(idregs, ID_AA64DFR0, 0x0000000110305408ull);
SET_IDREG(idregs, ID_AA64ISAR0, 0x0000100010211120ull);
SET_IDREG(idregs, ID_AA64ISAR1, 0x0000000000100001ull);
SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101125ull);
@@ -678,8 +678,8 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->dcz_blocksize = 4;
cpu->id_aa64afr0 = 0x00000000;
cpu->id_aa64afr1 = 0x00000000;
- cpu->isar.id_aa64dfr0 = 0x000001f210305519ull;
- cpu->isar.id_aa64dfr1 = 0x00000000;
+ SET_IDREG(idregs, ID_AA64DFR0, 0x000001f210305519ull),
+ SET_IDREG(idregs, ID_AA64DFR1, 0x00000000),
SET_IDREG(idregs, ID_AA64ISAR0, 0x1011111110212120ull); /* with FEAT_RNG */
SET_IDREG(idregs, ID_AA64ISAR1, 0x0011000001211032ull);
SET_IDREG(idregs, ID_AA64MMFR0, 0x0000000000101125ull);
@@ -925,8 +925,9 @@ static void aarch64_a710_initfn(Object *obj)
SET_IDREG(idregs, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000221ull);
SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
- cpu->isar.id_aa64dfr0 = 0x000011f010305619ull;
- cpu->isar.id_aa64dfr1 = 0;
+ SET_IDREG(idregs, ID_AA64DFR0, 0x000011f010305619ull);
+ SET_IDREG(idregs, ID_AA64DFR0, 0x000011f010305619ull);
+ SET_IDREG(idregs, ID_AA64DFR1, 0);
cpu->id_aa64afr0 = 0;
cpu->id_aa64afr1 = 0;
SET_IDREG(idregs, ID_AA64ISAR0, 0x0221111110212120ull); /* with Crypto */
@@ -1027,8 +1028,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
SET_IDREG(idregs, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000221ull);
SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
- cpu->isar.id_aa64dfr0 = 0x000011f210305619ull;
- cpu->isar.id_aa64dfr1 = 0;
+ SET_IDREG(idregs, ID_AA64DFR0, 0x000011f210305619ull);
+ SET_IDREG(idregs, ID_AA64DFR1, 0);
cpu->id_aa64afr0 = 0;
cpu->id_aa64afr1 = 0;
SET_IDREG(idregs, ID_AA64ISAR0, 0x1221111110212120ull); /* with Crypto and FEAT_RNG */
@@ -1259,11 +1260,11 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */
SET_IDREG(idregs, ID_AA64ZFR0, t);
- t = cpu->isar.id_aa64dfr0;
+ t = GET_IDREG(idregs, ID_AA64DFR0);
t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */
t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */
- cpu->isar.id_aa64dfr0 = t;
+ SET_IDREG(idregs, ID_AA64DFR0, t);
t = cpu->isar.id_aa64smfr0;
t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 08/15] arm/cpu: Store aa64smfr0 into the idregs array
2025-02-07 11:02 [PATCH 00/15] arm: rework id register storage Cornelia Huck
` (6 preceding siblings ...)
2025-02-07 11:02 ` [PATCH 07/15] arm/cpu: Store aa64dfr0/1 " Cornelia Huck
@ 2025-02-07 11:02 ` Cornelia Huck
2025-02-07 11:02 ` [PATCH 09/15] arm/cpu: Store id_isar0-7 " Cornelia Huck
` (6 subsequent siblings)
14 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-02-07 11:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-features.h | 6 +++---
target/arm/cpu.h | 1 -
target/arm/cpu64.c | 7 ++-----
target/arm/helper.c | 2 +-
target/arm/kvm.c | 3 +--
target/arm/tcg/cpu64.c | 4 ++--
6 files changed, 9 insertions(+), 14 deletions(-)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 05de9e0d9932..6224c7ec6356 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -968,17 +968,17 @@ static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id)
static inline bool isar_feature_aa64_sme_f64f64(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, F64F64);
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64SMFR0, F64F64);
}
static inline bool isar_feature_aa64_sme_i16i64(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, I16I64) == 0xf;
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64SMFR0, I16I64) == 0xf;
}
static inline bool isar_feature_aa64_sme_fa64(const ARMISARegisters *id)
{
- return FIELD_EX64(id->id_aa64smfr0, ID_AA64SMFR0, FA64);
+ return FIELD_EX64_IDREG(&id->idregs, ID_AA64SMFR0, FA64);
}
/*
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 99b0c2a4b39d..82db0d429c91 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1067,7 +1067,6 @@ struct ArchCPU {
uint32_t dbgdidr;
uint32_t dbgdevid;
uint32_t dbgdevid1;
- uint64_t id_aa64smfr0;
uint64_t reset_pmcr_el0;
uint64_t idregs[NUM_ID_IDX];
} isar;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 22286a1844a4..5c3ca3ba7af1 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -306,7 +306,7 @@ void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
if (vq_map == 0) {
if (!cpu_isar_feature(aa64_sme, cpu)) {
- cpu->isar.id_aa64smfr0 = 0;
+ SET_IDREG(&cpu->isar.idregs, ID_AA64SMFR0, 0);
return;
}
@@ -359,11 +359,8 @@ static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp)
static void cpu_arm_set_sme_fa64(Object *obj, bool value, Error **errp)
{
ARMCPU *cpu = ARM_CPU(obj);
- uint64_t t;
- t = cpu->isar.id_aa64smfr0;
- t = FIELD_DP64(t, ID_AA64SMFR0, FA64, value);
- cpu->isar.id_aa64smfr0 = t;
+ FIELD_DP64_IDREG(&cpu->isar.idregs, ID_AA64SMFR0, FA64, value);
}
#ifdef CONFIG_USER_ONLY
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 437ba8a53934..7c2953a971b6 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7725,7 +7725,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_aa64smfr0 },
+ .resetvalue = GET_IDREG(idregs, ID_AA64SMFR0)},
{ .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 7597c84ff2ce..b3092335a118 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -361,8 +361,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
err = 0;
} else {
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR1_EL1);
- err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64smfr0,
- ARM64_SYS_REG(3, 0, 0, 4, 5));
+ err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64SMFR0_EL1);
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64DFR0_EL1);
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64DFR1_EL1);
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64ISAR0_EL1);
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index ce4cb449a381..38d189361e3e 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1266,7 +1266,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */
SET_IDREG(idregs, ID_AA64DFR0, t);
- t = cpu->isar.id_aa64smfr0;
+ t = GET_IDREG(idregs, ID_AA64SMFR0);
t = FIELD_DP64(t, ID_AA64SMFR0, F32F32, 1); /* FEAT_SME */
t = FIELD_DP64(t, ID_AA64SMFR0, B16F32, 1); /* FEAT_SME */
t = FIELD_DP64(t, ID_AA64SMFR0, F16F32, 1); /* FEAT_SME */
@@ -1274,7 +1274,7 @@ void aarch64_max_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64SMFR0, F64F64, 1); /* FEAT_SME_F64F64 */
t = FIELD_DP64(t, ID_AA64SMFR0, I16I64, 0xf); /* FEAT_SME_I16I64 */
t = FIELD_DP64(t, ID_AA64SMFR0, FA64, 1); /* FEAT_SME_FA64 */
- cpu->isar.id_aa64smfr0 = t;
+ SET_IDREG(idregs, ID_AA64SMFR0, t);
/* Replicate the same data to the 32-bit id registers. */
aa32_max_features(cpu);
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 09/15] arm/cpu: Store id_isar0-7 into the idregs array
2025-02-07 11:02 [PATCH 00/15] arm: rework id register storage Cornelia Huck
` (7 preceding siblings ...)
2025-02-07 11:02 ` [PATCH 08/15] arm/cpu: Store aa64smfr0 " Cornelia Huck
@ 2025-02-07 11:02 ` Cornelia Huck
2025-02-07 11:02 ` [PATCH 10/15] arm/cpu: Store id_mfr0/1 " Cornelia Huck
` (5 subsequent siblings)
14 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-02-07 11:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
hw/intc/armv7m_nvic.c | 12 ++--
target/arm/cpu-features.h | 36 +++++-----
target/arm/cpu.c | 24 +++----
target/arm/cpu.h | 7 --
target/arm/cpu64.c | 28 ++++----
target/arm/helper.c | 14 ++--
target/arm/kvm.c | 22 +++---
target/arm/tcg/cpu-v7m.c | 90 +++++++++++++-----------
target/arm/tcg/cpu32.c | 143 ++++++++++++++++++++------------------
target/arm/tcg/cpu64.c | 108 ++++++++++++++--------------
10 files changed, 243 insertions(+), 241 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 5fd076098243..0e3174dc30db 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1303,32 +1303,32 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_isar0;
+ return GET_IDREG(&cpu->isar.idregs, ID_ISAR0);
case 0xd64: /* ISAR1. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_isar1;
+ return GET_IDREG(&cpu->isar.idregs, ID_ISAR1);
case 0xd68: /* ISAR2. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_isar2;
+ return GET_IDREG(&cpu->isar.idregs, ID_ISAR2);
case 0xd6c: /* ISAR3. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_isar3;
+ return GET_IDREG(&cpu->isar.idregs, ID_ISAR3);
case 0xd70: /* ISAR4. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_isar4;
+ return GET_IDREG(&cpu->isar.idregs, ID_ISAR4);
case 0xd74: /* ISAR5. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_isar5;
+ return GET_IDREG(&cpu->isar.idregs, ID_ISAR5);
case 0xd78: /* CLIDR */
return cpu->clidr;
case 0xd7c: /* CTR */
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 6224c7ec6356..b0d181996865 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -45,93 +45,93 @@
*/
static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR0, DIVIDE) != 0;
}
static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR0, DIVIDE) > 1;
}
static inline bool isar_feature_aa32_lob(const ARMISARegisters *id)
{
/* (M-profile) low-overhead loops and branch future */
- return FIELD_EX32(id->id_isar0, ID_ISAR0, CMPBRANCH) >= 3;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR0, CMPBRANCH) >= 3;
}
static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR1, JAZELLE) != 0;
}
static inline bool isar_feature_aa32_aes(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR5, AES) != 0;
}
static inline bool isar_feature_aa32_pmull(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar5, ID_ISAR5, AES) > 1;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR5, AES) > 1;
}
static inline bool isar_feature_aa32_sha1(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA1) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR5, SHA1) != 0;
}
static inline bool isar_feature_aa32_sha2(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar5, ID_ISAR5, SHA2) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR5, SHA2) != 0;
}
static inline bool isar_feature_aa32_crc32(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar5, ID_ISAR5, CRC32) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR5, CRC32) != 0;
}
static inline bool isar_feature_aa32_rdm(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar5, ID_ISAR5, RDM) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR5, RDM) != 0;
}
static inline bool isar_feature_aa32_vcma(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar5, ID_ISAR5, VCMA) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR5, VCMA) != 0;
}
static inline bool isar_feature_aa32_jscvt(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar6, ID_ISAR6, JSCVT) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR6, JSCVT) != 0;
}
static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR6, DP) != 0;
}
static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR6, FHM) != 0;
}
static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR6, SB) != 0;
}
static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR6, SPECRES) != 0;
}
static inline bool isar_feature_aa32_bf16(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar6, ID_ISAR6, BF16) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR6, BF16) != 0;
}
static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_isar6, ID_ISAR6, I8MM) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_ISAR6, I8MM) != 0;
}
static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 8f2d58cffbfd..a269544d3e09 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2149,10 +2149,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
FIELD_DP64_IDREG(idregs, ID_AA64PFR0, FP, 0xf);
- u = cpu->isar.id_isar6;
+ u = GET_IDREG(idregs, ID_ISAR6);
u = FIELD_DP32(u, ID_ISAR6, JSCVT, 0);
u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
- cpu->isar.id_isar6 = u;
+ SET_IDREG(idregs, ID_ISAR6, u);
u = cpu->isar.mvfr0;
u = FIELD_DP32(u, MVFR0, FPSP, 0);
@@ -2204,20 +2204,20 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
FIELD_DP64_IDREG(idregs, ID_AA64PFR0, ADVSIMD, 0xf);
- u = cpu->isar.id_isar5;
+ u = GET_IDREG(idregs, ID_ISAR5);
u = FIELD_DP32(u, ID_ISAR5, AES, 0);
u = FIELD_DP32(u, ID_ISAR5, SHA1, 0);
u = FIELD_DP32(u, ID_ISAR5, SHA2, 0);
u = FIELD_DP32(u, ID_ISAR5, RDM, 0);
u = FIELD_DP32(u, ID_ISAR5, VCMA, 0);
- cpu->isar.id_isar5 = u;
+ SET_IDREG(idregs, ID_ISAR5, u);
- u = cpu->isar.id_isar6;
+ u = GET_IDREG(idregs, ID_ISAR6);
u = FIELD_DP32(u, ID_ISAR6, DP, 0);
u = FIELD_DP32(u, ID_ISAR6, FHM, 0);
u = FIELD_DP32(u, ID_ISAR6, BF16, 0);
u = FIELD_DP32(u, ID_ISAR6, I8MM, 0);
- cpu->isar.id_isar6 = u;
+ SET_IDREG(idregs, ID_ISAR6, u);
if (!arm_feature(env, ARM_FEATURE_M)) {
u = cpu->isar.mvfr1;
@@ -2255,19 +2255,17 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
unset_feature(env, ARM_FEATURE_THUMB_DSP);
- u = cpu->isar.id_isar1;
- u = FIELD_DP32(u, ID_ISAR1, EXTEND, 1);
- cpu->isar.id_isar1 = u;
+ FIELD_DP32_IDREG(idregs, ID_ISAR1, EXTEND, 1);
- u = cpu->isar.id_isar2;
+ u = GET_IDREG(idregs, ID_ISAR2);
u = FIELD_DP32(u, ID_ISAR2, MULTU, 1);
u = FIELD_DP32(u, ID_ISAR2, MULTS, 1);
- cpu->isar.id_isar2 = u;
+ SET_IDREG(idregs, ID_ISAR2, u);
- u = cpu->isar.id_isar3;
+ u = GET_IDREG(idregs, ID_ISAR3);
u = FIELD_DP32(u, ID_ISAR3, SIMD, 1);
u = FIELD_DP32(u, ID_ISAR3, SATURATE, 0);
- cpu->isar.id_isar3 = u;
+ SET_IDREG(idregs, ID_ISAR3, u);
}
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 82db0d429c91..738a4b540efd 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1043,13 +1043,6 @@ struct ArchCPU {
* field by reading the value from the KVM vCPU.
*/
struct ARMISARegisters {
- uint32_t id_isar0;
- uint32_t id_isar1;
- uint32_t id_isar2;
- uint32_t id_isar3;
- uint32_t id_isar4;
- uint32_t id_isar5;
- uint32_t id_isar6;
uint32_t id_mmfr0;
uint32_t id_mmfr1;
uint32_t id_mmfr2;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 5c3ca3ba7af1..fb312805fca7 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -638,13 +638,13 @@ static void aarch64_a57_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x00011121;
- cpu->isar.id_isar6 = 0;
+ SET_IDREG(idregs, ID_ISAR0, 0x02101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x13112111);
+ SET_IDREG(idregs, ID_ISAR2, 0x21232042);
+ SET_IDREG(idregs, ID_ISAR3, 0x01112131);
+ SET_IDREG(idregs, ID_ISAR4, 0x00011142);
+ SET_IDREG(idregs, ID_ISAR5, 0x00011121);
+ SET_IDREG(idregs, ID_ISAR6, 0);
SET_IDREG(idregs, ID_AA64PFR0, 0x00002222);
SET_IDREG(idregs, ID_AA64DFR0, 0x10305106);
SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
@@ -700,13 +700,13 @@ static void aarch64_a53_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x00011121;
- cpu->isar.id_isar6 = 0;
+ SET_IDREG(idregs, ID_ISAR0, 0x02101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x13112111);
+ SET_IDREG(idregs, ID_ISAR2, 0x21232042);
+ SET_IDREG(idregs, ID_ISAR3, 0x01112131);
+ SET_IDREG(idregs, ID_ISAR4, 0x00011142);
+ SET_IDREG(idregs, ID_ISAR5, 0x00011121);
+ SET_IDREG(idregs, ID_ISAR6, 0);
SET_IDREG(idregs, ID_AA64PFR0, 0x00002222);
SET_IDREG(idregs, ID_AA64DFR0, 0x10305106);
SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7c2953a971b6..8200ee4a4d03 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7607,32 +7607,32 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_isar0 },
+ .resetvalue = GET_IDREG(idregs, ID_ISAR0)},
{ .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_isar1 },
+ .resetvalue = GET_IDREG(idregs, ID_ISAR1)},
{ .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_isar2 },
+ .resetvalue = GET_IDREG(idregs, ID_ISAR2)},
{ .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_isar3 },
+ .resetvalue = GET_IDREG(idregs, ID_ISAR3) },
{ .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_isar4 },
+ .resetvalue = GET_IDREG(idregs, ID_ISAR4) },
{ .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_isar5 },
+ .resetvalue = GET_IDREG(idregs, ID_ISAR5) },
{ .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
@@ -7642,7 +7642,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_isar6 },
+ .resetvalue = GET_IDREG(idregs, ID_ISAR6) },
};
define_arm_cp_regs(cpu, v6_idregs);
define_arm_cp_regs(cpu, v6_cp_reginfo);
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index b3092335a118..c9b535503a4e 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -277,6 +277,7 @@ static int get_host_cpu_reg64(int fd, ARMHostCPUFeatures *ahcf, ARMSysRegs sysre
return ret;
}
+
static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
{
/* Identify the feature bits corresponding to the host CPU, and
@@ -391,22 +392,15 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ARM64_SYS_REG(3, 0, 0, 1, 6));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
ARM64_SYS_REG(3, 0, 0, 1, 7));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0,
- ARM64_SYS_REG(3, 0, 0, 2, 0));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1,
- ARM64_SYS_REG(3, 0, 0, 2, 1));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar2,
- ARM64_SYS_REG(3, 0, 0, 2, 2));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar3,
- ARM64_SYS_REG(3, 0, 0, 2, 3));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar4,
- ARM64_SYS_REG(3, 0, 0, 2, 4));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5,
- ARM64_SYS_REG(3, 0, 0, 2, 5));
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR0_EL1);
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR1_EL1);
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR2_EL1);
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR3_EL1);
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR4_EL1);
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR5_EL1);
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR6_EL1);
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
ARM64_SYS_REG(3, 0, 0, 2, 6));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6,
- ARM64_SYS_REG(3, 0, 0, 2, 7));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
ARM64_SYS_REG(3, 0, 0, 3, 0));
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index 03acdf83e006..31f9bcc49a13 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -46,6 +46,7 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
static void cortex_m0_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
set_feature(&cpu->env, ARM_FEATURE_V6);
set_feature(&cpu->env, ARM_FEATURE_M);
@@ -67,18 +68,19 @@ static void cortex_m0_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x00000000;
cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01141110;
- cpu->isar.id_isar1 = 0x02111000;
- cpu->isar.id_isar2 = 0x21112231;
- cpu->isar.id_isar3 = 0x01111110;
- cpu->isar.id_isar4 = 0x01310102;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
+ SET_IDREG(idregs, ID_ISAR0, 0x01141110);
+ SET_IDREG(idregs, ID_ISAR1, 0x02111000);
+ SET_IDREG(idregs, ID_ISAR2, 0x21112231);
+ SET_IDREG(idregs, ID_ISAR3, 0x01111110);
+ SET_IDREG(idregs, ID_ISAR4, 0x01310102);
+ SET_IDREG(idregs, ID_ISAR5, 0x00000000);
+ SET_IDREG(idregs, ID_ISAR6, 0x00000000);
}
static void cortex_m3_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_M);
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
@@ -92,18 +94,19 @@ static void cortex_m3_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x00000000;
cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01141110;
- cpu->isar.id_isar1 = 0x02111000;
- cpu->isar.id_isar2 = 0x21112231;
- cpu->isar.id_isar3 = 0x01111110;
- cpu->isar.id_isar4 = 0x01310102;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
+ SET_IDREG(idregs, ID_ISAR0, 0x01141110);
+ SET_IDREG(idregs, ID_ISAR1, 0x02111000);
+ SET_IDREG(idregs, ID_ISAR2, 0x21112231);
+ SET_IDREG(idregs, ID_ISAR3, 0x01111110);
+ SET_IDREG(idregs, ID_ISAR4, 0x01310102);
+ SET_IDREG(idregs, ID_ISAR5, 0x00000000);
+ SET_IDREG(idregs, ID_ISAR6, 0x00000000);
}
static void cortex_m4_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_M);
@@ -122,18 +125,19 @@ static void cortex_m4_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x00000000;
cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01141110;
- cpu->isar.id_isar1 = 0x02111000;
- cpu->isar.id_isar2 = 0x21112231;
- cpu->isar.id_isar3 = 0x01111110;
- cpu->isar.id_isar4 = 0x01310102;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
+ SET_IDREG(idregs, ID_ISAR0, 0x01141110);
+ SET_IDREG(idregs, ID_ISAR1, 0x02111000);
+ SET_IDREG(idregs, ID_ISAR2, 0x21112231);
+ SET_IDREG(idregs, ID_ISAR3, 0x01111110);
+ SET_IDREG(idregs, ID_ISAR4, 0x01310102);
+ SET_IDREG(idregs, ID_ISAR5, 0x00000000);
+ SET_IDREG(idregs, ID_ISAR6, 0x00000000);
}
static void cortex_m7_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_M);
@@ -152,18 +156,19 @@ static void cortex_m7_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x01000000;
cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01101110;
- cpu->isar.id_isar1 = 0x02112000;
- cpu->isar.id_isar2 = 0x20232231;
- cpu->isar.id_isar3 = 0x01111131;
- cpu->isar.id_isar4 = 0x01310132;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
+ SET_IDREG(idregs, ID_ISAR0, 0x01101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x02112000);
+ SET_IDREG(idregs, ID_ISAR2, 0x20232231);
+ SET_IDREG(idregs, ID_ISAR3, 0x01111131);
+ SET_IDREG(idregs, ID_ISAR4, 0x01310132);
+ SET_IDREG(idregs, ID_ISAR5, 0x00000000);
+ SET_IDREG(idregs, ID_ISAR6, 0x00000000);
}
static void cortex_m33_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
set_feature(&cpu->env, ARM_FEATURE_V8);
set_feature(&cpu->env, ARM_FEATURE_M);
@@ -184,13 +189,13 @@ static void cortex_m33_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x01000000;
cpu->isar.id_mmfr3 = 0x00000000;
- cpu->isar.id_isar0 = 0x01101110;
- cpu->isar.id_isar1 = 0x02212000;
- cpu->isar.id_isar2 = 0x20232232;
- cpu->isar.id_isar3 = 0x01111131;
- cpu->isar.id_isar4 = 0x01310132;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
+ SET_IDREG(idregs, ID_ISAR0, 0x01101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x02212000);
+ SET_IDREG(idregs, ID_ISAR2, 0x20232232);
+ SET_IDREG(idregs, ID_ISAR3, 0x01111131);
+ SET_IDREG(idregs, ID_ISAR4, 0x01310132);
+ SET_IDREG(idregs, ID_ISAR5, 0x00000000);
+ SET_IDREG(idregs, ID_ISAR6, 0x00000000);
cpu->clidr = 0x00000000;
cpu->ctr = 0x8000c000;
}
@@ -198,6 +203,7 @@ static void cortex_m33_initfn(Object *obj)
static void cortex_m55_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
set_feature(&cpu->env, ARM_FEATURE_V8);
set_feature(&cpu->env, ARM_FEATURE_V8_1M);
@@ -221,13 +227,13 @@ static void cortex_m55_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x01000000;
cpu->isar.id_mmfr3 = 0x00000011;
- cpu->isar.id_isar0 = 0x01103110;
- cpu->isar.id_isar1 = 0x02212000;
- cpu->isar.id_isar2 = 0x20232232;
- cpu->isar.id_isar3 = 0x01111131;
- cpu->isar.id_isar4 = 0x01310132;
- cpu->isar.id_isar5 = 0x00000000;
- cpu->isar.id_isar6 = 0x00000000;
+ SET_IDREG(idregs, ID_ISAR0, 0x01103110);
+ SET_IDREG(idregs, ID_ISAR1, 0x02212000);
+ SET_IDREG(idregs, ID_ISAR2, 0x20232232);
+ SET_IDREG(idregs, ID_ISAR3, 0x01111131);
+ SET_IDREG(idregs, ID_ISAR4, 0x01310132);
+ SET_IDREG(idregs, ID_ISAR5, 0x00000000);
+ SET_IDREG(idregs, ID_ISAR6, 0x00000000);
cpu->clidr = 0x00000000; /* caches not implemented */
cpu->ctr = 0x8303c003;
}
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 2ad218252553..5ff0e8b0a65c 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -25,16 +25,16 @@ void aa32_max_features(ARMCPU *cpu)
uint32_t t;
/* Add additional features supported by QEMU */
- t = cpu->isar.id_isar5;
+ t = GET_IDREG(&cpu->isar.idregs, ID_ISAR5);
t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
- cpu->isar.id_isar5 = t;
+ SET_IDREG(&cpu->isar.idregs, ID_ISAR5, t);
- t = cpu->isar.id_isar6;
+ t = GET_IDREG(&cpu->isar.idregs, ID_ISAR6);
t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
@@ -42,7 +42,7 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
- cpu->isar.id_isar6 = t;
+ SET_IDREG(&cpu->isar.idregs, ID_ISAR6, t);
t = cpu->isar.mvfr1;
t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
@@ -140,7 +140,7 @@ static void arm926_initfn(Object *obj)
* ARMv5 does not have the ID_ISAR registers, but we can still
* set the field to indicate Jazelle support within QEMU.
*/
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
+ FIELD_DP32_IDREG(&cpu->isar.idregs, ID_ISAR1, JAZELLE, 1);
/*
* Similarly, we need to set MVFR0 fields to enable vfp and short vector
* support even though ARMv5 doesn't have this register.
@@ -182,7 +182,7 @@ static void arm1026_initfn(Object *obj)
* ARMv5 does not have the ID_ISAR registers, but we can still
* set the field to indicate Jazelle support within QEMU.
*/
- cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
+ FIELD_DP32_IDREG(&cpu->isar.idregs, ID_ISAR1, JAZELLE, 1);
/*
* Similarly, we need to set MVFR0 fields to enable vfp and short vector
* support even though ARMv5 doesn't have this register.
@@ -206,6 +206,7 @@ static void arm1026_initfn(Object *obj)
static void arm1136_r2_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
/*
* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
* older core than plain "arm1136". In particular this does not
@@ -233,17 +234,18 @@ static void arm1136_r2_initfn(Object *obj)
cpu->isar.id_mmfr0 = 0x01130003;
cpu->isar.id_mmfr1 = 0x10030302;
cpu->isar.id_mmfr2 = 0x01222110;
- cpu->isar.id_isar0 = 0x00140011;
- cpu->isar.id_isar1 = 0x12002111;
- cpu->isar.id_isar2 = 0x11231111;
- cpu->isar.id_isar3 = 0x01102131;
- cpu->isar.id_isar4 = 0x141;
+ SET_IDREG(idregs, ID_ISAR0, 0x00140011);
+ SET_IDREG(idregs, ID_ISAR1, 0x12002111);
+ SET_IDREG(idregs, ID_ISAR2, 0x11231111);
+ SET_IDREG(idregs, ID_ISAR3, 0x01102131);
+ SET_IDREG(idregs, ID_ISAR4, 0x141);
cpu->reset_auxcr = 7;
}
static void arm1136_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,arm1136";
set_feature(&cpu->env, ARM_FEATURE_V6K);
@@ -264,17 +266,18 @@ static void arm1136_initfn(Object *obj)
cpu->isar.id_mmfr0 = 0x01130003;
cpu->isar.id_mmfr1 = 0x10030302;
cpu->isar.id_mmfr2 = 0x01222110;
- cpu->isar.id_isar0 = 0x00140011;
- cpu->isar.id_isar1 = 0x12002111;
- cpu->isar.id_isar2 = 0x11231111;
- cpu->isar.id_isar3 = 0x01102131;
- cpu->isar.id_isar4 = 0x141;
+ SET_IDREG(idregs, ID_ISAR0, 0x00140011);
+ SET_IDREG(idregs, ID_ISAR1, 0x12002111);
+ SET_IDREG(idregs, ID_ISAR2, 0x11231111);
+ SET_IDREG(idregs, ID_ISAR3, 0x01102131);
+ SET_IDREG(idregs, ID_ISAR4, 0x141);
cpu->reset_auxcr = 7;
}
static void arm1176_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,arm1176";
set_feature(&cpu->env, ARM_FEATURE_V6K);
@@ -296,17 +299,18 @@ static void arm1176_initfn(Object *obj)
cpu->isar.id_mmfr0 = 0x01130003;
cpu->isar.id_mmfr1 = 0x10030302;
cpu->isar.id_mmfr2 = 0x01222100;
- cpu->isar.id_isar0 = 0x0140011;
- cpu->isar.id_isar1 = 0x12002111;
- cpu->isar.id_isar2 = 0x11231121;
- cpu->isar.id_isar3 = 0x01102131;
- cpu->isar.id_isar4 = 0x01141;
+ SET_IDREG(idregs, ID_ISAR0, 0x0140011);
+ SET_IDREG(idregs, ID_ISAR1, 0x12002111);
+ SET_IDREG(idregs, ID_ISAR2, 0x11231121);
+ SET_IDREG(idregs, ID_ISAR3, 0x01102131);
+ SET_IDREG(idregs, ID_ISAR4, 0x01141);
cpu->reset_auxcr = 7;
}
static void arm11mpcore_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,arm11mpcore";
set_feature(&cpu->env, ARM_FEATURE_V6K);
@@ -325,11 +329,11 @@ static void arm11mpcore_initfn(Object *obj)
cpu->isar.id_mmfr0 = 0x01100103;
cpu->isar.id_mmfr1 = 0x10020302;
cpu->isar.id_mmfr2 = 0x01222000;
- cpu->isar.id_isar0 = 0x00100011;
- cpu->isar.id_isar1 = 0x12002111;
- cpu->isar.id_isar2 = 0x11221011;
- cpu->isar.id_isar3 = 0x01102131;
- cpu->isar.id_isar4 = 0x141;
+ SET_IDREG(idregs, ID_ISAR0, 0x00100011);
+ SET_IDREG(idregs, ID_ISAR1, 0x12002111);
+ SET_IDREG(idregs, ID_ISAR2, 0x11221011);
+ SET_IDREG(idregs, ID_ISAR3, 0x01102131);
+ SET_IDREG(idregs, ID_ISAR4, 0x141);
cpu->reset_auxcr = 1;
}
@@ -343,6 +347,7 @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
static void cortex_a8_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,cortex-a8";
set_feature(&cpu->env, ARM_FEATURE_V7);
@@ -365,11 +370,11 @@ static void cortex_a8_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x20000000;
cpu->isar.id_mmfr2 = 0x01202000;
cpu->isar.id_mmfr3 = 0x11;
- cpu->isar.id_isar0 = 0x00101111;
- cpu->isar.id_isar1 = 0x12112111;
- cpu->isar.id_isar2 = 0x21232031;
- cpu->isar.id_isar3 = 0x11112131;
- cpu->isar.id_isar4 = 0x00111142;
+ SET_IDREG(idregs, ID_ISAR0, 0x00101111);
+ SET_IDREG(idregs, ID_ISAR1, 0x12112111);
+ SET_IDREG(idregs, ID_ISAR2, 0x21232031);
+ SET_IDREG(idregs, ID_ISAR3, 0x11112131);
+ SET_IDREG(idregs, ID_ISAR4, 0x00111142);
cpu->isar.dbgdidr = 0x15141000;
cpu->clidr = (1 << 27) | (2 << 24) | 3;
cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
@@ -412,6 +417,7 @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
static void cortex_a9_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,cortex-a9";
set_feature(&cpu->env, ARM_FEATURE_V7);
@@ -440,11 +446,11 @@ static void cortex_a9_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x20000000;
cpu->isar.id_mmfr2 = 0x01230000;
cpu->isar.id_mmfr3 = 0x00002111;
- cpu->isar.id_isar0 = 0x00101111;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232041;
- cpu->isar.id_isar3 = 0x11112131;
- cpu->isar.id_isar4 = 0x00111142;
+ SET_IDREG(idregs, ID_ISAR0, 0x00101111);
+ SET_IDREG(idregs, ID_ISAR1, 0x13112111);
+ SET_IDREG(idregs, ID_ISAR2, 0x21232041);
+ SET_IDREG(idregs, ID_ISAR3, 0x11112131);
+ SET_IDREG(idregs, ID_ISAR4, 0x00111142);
cpu->isar.dbgdidr = 0x35141000;
cpu->clidr = (1 << 27) | (1 << 24) | 3;
cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
@@ -479,6 +485,7 @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
static void cortex_a7_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,cortex-a7";
set_feature(&cpu->env, ARM_FEATURE_V7VE);
@@ -509,11 +516,11 @@ static void cortex_a7_initfn(Object *obj)
* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
* table 4-41 gives 0x02101110, which includes the arm div insns.
*/
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232041;
- cpu->isar.id_isar3 = 0x11112131;
- cpu->isar.id_isar4 = 0x10011142;
+ SET_IDREG(idregs, ID_ISAR0, 0x02101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x13112111);
+ SET_IDREG(idregs, ID_ISAR2, 0x21232041);
+ SET_IDREG(idregs, ID_ISAR3, 0x11112131);
+ SET_IDREG(idregs, ID_ISAR4, 0x10011142);
cpu->isar.dbgdidr = 0x3515f005;
cpu->isar.dbgdevid = 0x01110f13;
cpu->isar.dbgdevid1 = 0x1;
@@ -528,6 +535,7 @@ static void cortex_a7_initfn(Object *obj)
static void cortex_a15_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
cpu->dtb_compatible = "arm,cortex-a15";
set_feature(&cpu->env, ARM_FEATURE_V7VE);
@@ -556,11 +564,11 @@ static void cortex_a15_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x20000000;
cpu->isar.id_mmfr2 = 0x01240000;
cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232041;
- cpu->isar.id_isar3 = 0x11112131;
- cpu->isar.id_isar4 = 0x10011142;
+ SET_IDREG(idregs, ID_ISAR0, 0x02101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x13112111);
+ SET_IDREG(idregs, ID_ISAR2, 0x21232041);
+ SET_IDREG(idregs, ID_ISAR3, 0x11112131);
+ SET_IDREG(idregs, ID_ISAR4, 0x10011142);
cpu->isar.dbgdidr = 0x3515f021;
cpu->isar.dbgdevid = 0x01110f13;
cpu->isar.dbgdevid1 = 0x0;
@@ -585,6 +593,7 @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
static void cortex_r5_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_V7MP);
@@ -599,13 +608,13 @@ static void cortex_r5_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x00000000;
cpu->isar.id_mmfr2 = 0x01200000;
cpu->isar.id_mmfr3 = 0x0211;
- cpu->isar.id_isar0 = 0x02101111;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232141;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x0010142;
- cpu->isar.id_isar5 = 0x0;
- cpu->isar.id_isar6 = 0x0;
+ SET_IDREG(idregs, ID_ISAR0, 0x02101111);
+ SET_IDREG(idregs, ID_ISAR1, 0x13112111);
+ SET_IDREG(idregs, ID_ISAR2, 0x21232141);
+ SET_IDREG(idregs, ID_ISAR3, 0x01112131);
+ SET_IDREG(idregs, ID_ISAR4, 0x0010142);
+ SET_IDREG(idregs, ID_ISAR5, 0x21232141);
+ SET_IDREG(idregs, ID_ISAR6, 0x0);
cpu->mp_is_up = true;
cpu->pmsav7_dregion = 16;
cpu->isar.reset_pmcr_el0 = 0x41151800;
@@ -720,6 +729,7 @@ static const ARMCPRegInfo cortex_r52_cp_reginfo[] = {
static void cortex_r52_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
set_feature(&cpu->env, ARM_FEATURE_V8);
set_feature(&cpu->env, ARM_FEATURE_EL2);
@@ -746,12 +756,12 @@ static void cortex_r52_initfn(Object *obj)
cpu->isar.id_mmfr2 = 0x01200000;
cpu->isar.id_mmfr3 = 0xf0102211;
cpu->isar.id_mmfr4 = 0x00000010;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232142;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x00010001;
+ SET_IDREG(idregs, ID_ISAR0, 0x02101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x13112111);
+ SET_IDREG(idregs, ID_ISAR2, 0x21232142);
+ SET_IDREG(idregs, ID_ISAR3, 0x01112131);
+ SET_IDREG(idregs, ID_ISAR4, 0x00010142);
+ SET_IDREG(idregs, ID_ISAR5, 0x00010001);
cpu->isar.dbgdidr = 0x77168000;
cpu->clidr = (1 << 27) | (1 << 24) | 0x3;
cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
@@ -949,6 +959,7 @@ static void pxa270c5_initfn(Object *obj)
static void arm_max_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t *idregs = cpu->isar.idregs;
/* aarch64_a57_initfn, advertising none of the aarch64 features */
cpu->dtb_compatible = "arm,cortex-a57";
@@ -976,13 +987,13 @@ static void arm_max_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x00011121;
- cpu->isar.id_isar6 = 0;
+ SET_IDREG(idregs, ID_ISAR0, 0x02101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x13112111);
+ SET_IDREG(idregs, ID_ISAR2, 0x21232042);
+ SET_IDREG(idregs, ID_ISAR3, 0x01112131);
+ SET_IDREG(idregs, ID_ISAR4, 0x00011142);
+ SET_IDREG(idregs, ID_ISAR5, 0x00011121);
+ SET_IDREG(idregs, ID_ISAR6, 0);
cpu->isar.reset_pmcr_el0 = 0x41013000;
cpu->clidr = 0x0a200023;
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 38d189361e3e..355e3e437304 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -57,12 +57,12 @@ static void aarch64_a35_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x00011121;
+ SET_IDREG(idregs, ID_ISAR0, 0x02101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x13112111);
+ SET_IDREG(idregs, ID_ISAR2, 0x21232042);
+ SET_IDREG(idregs, ID_ISAR3, 0x01112131);
+ SET_IDREG(idregs, ID_ISAR4, 0x00011142);
+ SET_IDREG(idregs, ID_ISAR5, 0x00011121);
SET_IDREG(idregs, ID_AA64PFR0, 0x00002222);
SET_IDREG(idregs, ID_AA64PFR1, 0);
SET_IDREG(idregs, ID_AA64DFR0, 0x10305106);
@@ -229,13 +229,13 @@ static void aarch64_a55_initfn(Object *obj)
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_dfr0 = 0x04010088;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x01011121;
- cpu->isar.id_isar6 = 0x00000010;
+ SET_IDREG(idregs, ID_ISAR0, 0x02101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x13112111);
+ SET_IDREG(idregs, ID_ISAR2, 0x21232042);
+ SET_IDREG(idregs, ID_ISAR3, 0x01112131);
+ SET_IDREG(idregs, ID_ISAR4, 0x00011142);
+ SET_IDREG(idregs, ID_ISAR5, 0x01011121);
+ SET_IDREG(idregs, ID_ISAR6, 0x00000010);
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
@@ -303,12 +303,12 @@ static void aarch64_a72_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02102211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00011142;
- cpu->isar.id_isar5 = 0x00011121;
+ SET_IDREG(idregs, ID_ISAR0, 0x02101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x13112111);
+ SET_IDREG(idregs, ID_ISAR2, 0x21232042);
+ SET_IDREG(idregs, ID_ISAR3, 0x01112131);
+ SET_IDREG(idregs, ID_ISAR4, 0x00011142);
+ SET_IDREG(idregs, ID_ISAR5, 0x00011121);
SET_IDREG(idregs, ID_AA64PFR0, 0x00002222);
SET_IDREG(idregs, ID_AA64DFR0, 0x10305106);
SET_IDREG(idregs, ID_AA64ISAR0, 0x00011120);
@@ -362,13 +362,13 @@ static void aarch64_a76_initfn(Object *obj)
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_dfr0 = 0x04010088;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x01011121;
- cpu->isar.id_isar6 = 0x00000010;
+ SET_IDREG(idregs, ID_ISAR0, 0x02101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x13112111);
+ SET_IDREG(idregs, ID_ISAR2, 0x21232042);
+ SET_IDREG(idregs, ID_ISAR3, 0x01112131);
+ SET_IDREG(idregs, ID_ISAR4, 0x00010142);
+ SET_IDREG(idregs, ID_ISAR5, 0x01011121);
+ SET_IDREG(idregs, ID_ISAR6, 0x00000010);
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
@@ -610,13 +610,13 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_dfr0 = 0x04010088;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x01011121;
- cpu->isar.id_isar6 = 0x00000010;
+ SET_IDREG(idregs, ID_ISAR0, 0x02101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x13112111);
+ SET_IDREG(idregs, ID_ISAR2, 0x21232042);
+ SET_IDREG(idregs, ID_ISAR3, 0x01112131);
+ SET_IDREG(idregs, ID_ISAR4, 0x00010142);
+ SET_IDREG(idregs, ID_ISAR5, 0x01011121);
+ SET_IDREG(idregs, ID_ISAR6, 0x00000010);
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
@@ -689,13 +689,13 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_dfr0 = 0x15011099;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x11011121;
- cpu->isar.id_isar6 = 0x01100111;
+ SET_IDREG(idregs, ID_ISAR0, 0x02101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x13112111);
+ SET_IDREG(idregs, ID_ISAR2, 0x21232042);
+ SET_IDREG(idregs, ID_ISAR3, 0x01112131);
+ SET_IDREG(idregs, ID_ISAR4, 0x00010142);
+ SET_IDREG(idregs, ID_ISAR5, 0x11011121);
+ SET_IDREG(idregs, ID_ISAR6, 0x01100111);
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
@@ -910,14 +910,14 @@ static void aarch64_a710_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x11011121; /* with Crypto */
+ SET_IDREG(idregs, ID_ISAR0, 0x02101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x13112111);
+ SET_IDREG(idregs, ID_ISAR2, 0x21232042);
+ SET_IDREG(idregs, ID_ISAR3, 0x01112131);
+ SET_IDREG(idregs, ID_ISAR4, 0x00010142);
+ SET_IDREG(idregs, ID_ISAR5, 0x11011121); /* with Crypto */
cpu->isar.id_mmfr4 = 0x21021110;
- cpu->isar.id_isar6 = 0x01111111;
+ SET_IDREG(idregs, ID_ISAR6, 0x01111111);
cpu->isar.mvfr0 = 0x10110222;
cpu->isar.mvfr1 = 0x13211111;
cpu->isar.mvfr2 = 0x00000043;
@@ -1013,14 +1013,14 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->isar.id_mmfr1 = 0x40000000;
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_isar0 = 0x02101110;
- cpu->isar.id_isar1 = 0x13112111;
- cpu->isar.id_isar2 = 0x21232042;
- cpu->isar.id_isar3 = 0x01112131;
- cpu->isar.id_isar4 = 0x00010142;
- cpu->isar.id_isar5 = 0x11011121; /* with Crypto */
+ SET_IDREG(idregs, ID_ISAR0, 0x02101110);
+ SET_IDREG(idregs, ID_ISAR1, 0x13112111);
+ SET_IDREG(idregs, ID_ISAR2, 0x21232042);
+ SET_IDREG(idregs, ID_ISAR3, 0x01112131);
+ SET_IDREG(idregs, ID_ISAR4, 0x00010142);
+ SET_IDREG(idregs, ID_ISAR5, 0x11011121); /* with Crypto */
cpu->isar.id_mmfr4 = 0x01021110;
- cpu->isar.id_isar6 = 0x01111111;
+ SET_IDREG(idregs, ID_ISAR6, 0x01111111);
cpu->isar.mvfr0 = 0x10110222;
cpu->isar.mvfr1 = 0x13211111;
cpu->isar.mvfr2 = 0x00000043;
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 10/15] arm/cpu: Store id_mfr0/1 into the idregs array
2025-02-07 11:02 [PATCH 00/15] arm: rework id register storage Cornelia Huck
` (8 preceding siblings ...)
2025-02-07 11:02 ` [PATCH 09/15] arm/cpu: Store id_isar0-7 " Cornelia Huck
@ 2025-02-07 11:02 ` Cornelia Huck
2025-02-07 11:02 ` [PATCH 11/15] arm/cpu: Store id_dfr0/1 " Cornelia Huck
` (4 subsequent siblings)
14 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-02-07 11:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
hw/intc/armv7m_nvic.c | 5 ++--
target/arm/cpu-features.h | 10 +++----
target/arm/cpu.c | 8 ++---
target/arm/cpu.h | 3 --
target/arm/cpu64.c | 8 ++---
target/arm/helper.c | 8 ++---
target/arm/kvm.c | 3 +-
target/arm/tcg/cpu-v7m.c | 24 +++++++--------
target/arm/tcg/cpu32.c | 61 ++++++++++++++++++++-------------------
target/arm/tcg/cpu64.c | 44 ++++++++++++++--------------
10 files changed, 85 insertions(+), 89 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 0e3174dc30db..08529b89a6e0 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -988,6 +988,7 @@ static void nvic_nmi_trigger(void *opaque, int n, int level)
static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
{
ARMCPU *cpu = s->cpu;
+ uint64_t *idregs = cpu->isar.idregs;
uint32_t val;
switch (offset) {
@@ -1263,12 +1264,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_pfr0;
+ return GET_IDREG(idregs, ID_PFR0);
case 0xd44: /* PFR1. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_pfr1;
+ return GET_IDREG(idregs, ID_PFR1);
case 0xd48: /* DFR0. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index b0d181996865..a6eda2a1c554 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -136,12 +136,12 @@ static inline bool isar_feature_aa32_i8mm(const ARMISARegisters *id)
static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_PFR0, RAS) != 0;
}
static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_PFR1, MPROGMOD) != 0;
}
static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
@@ -150,7 +150,7 @@ static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
* Return true if M-profile state handling insns
* (VSCCLRM, CLRM, FPCTX access insns) are implemented
*/
- return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
+ return FIELD_EX32_IDREG(&id->idregs, ID_PFR1, SECURITY) >= 3;
}
static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
@@ -349,12 +349,12 @@ static inline bool isar_feature_aa32_evt(const ARMISARegisters *id)
static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_pfr0, ID_PFR0, DIT) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_PFR0, DIT) != 0;
}
static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_PFR2, SSBS) != 0;
}
static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index a269544d3e09..da11b59ba843 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2340,7 +2340,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* Disable the security extension feature bits in the processor
* feature registers as well.
*/
- cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
+ FIELD_DP32_IDREG(idregs, ID_PFR1, SECURITY, 0);
cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
FIELD_DP64_IDREG(idregs, ID_AA64PFR0, EL3, 0);
@@ -2380,8 +2380,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* registers if we don't have EL2.
*/
FIELD_DP64_IDREG(idregs, ID_AA64PFR0, EL2, 0);
- cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
- ID_PFR1, VIRTUALIZATION, 0);
+ FIELD_DP32_IDREG(idregs, ID_PFR1, VIRTUALIZATION, 0);
}
if (cpu_isar_feature(aa64_mte, cpu)) {
@@ -2444,8 +2443,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0);
/* FEAT_AMU (Activity Monitors Extension) */
FIELD_DP64_IDREG(idregs, ID_AA64PFR0, AMU, 0);
- cpu->isar.id_pfr0 =
- FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0);
+ FIELD_DP32_IDREG(idregs, ID_PFR0, AMU, 0);
/* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */
FIELD_DP64_IDREG(idregs, ID_AA64PFR0, MPAM, 0);
}
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 738a4b540efd..6c3dbf0e607c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1049,9 +1049,6 @@ struct ArchCPU {
uint32_t id_mmfr3;
uint32_t id_mmfr4;
uint32_t id_mmfr5;
- uint32_t id_pfr0;
- uint32_t id_pfr1;
- uint32_t id_pfr2;
uint32_t mvfr0;
uint32_t mvfr1;
uint32_t mvfr2;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index fb312805fca7..4efb20069b2b 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -630,8 +630,8 @@ static void aarch64_a57_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x8444c004;
cpu->reset_sctlr = 0x00c50838;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x00011011;
+ SET_IDREG(idregs, ID_PFR0, 0x00000131);
+ SET_IDREG(idregs, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
@@ -692,8 +692,8 @@ static void aarch64_a53_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x84448004; /* L1Ip = VIPT */
cpu->reset_sctlr = 0x00c50838;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x00011011;
+ SET_IDREG(idregs, ID_PFR0, 0x00000131);
+ SET_IDREG(idregs, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8200ee4a4d03..a3edd171ddf8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6708,7 +6708,7 @@ static void define_pmu_regs(ARMCPU *cpu)
static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
ARMCPU *cpu = env_archcpu(env);
- uint64_t pfr1 = cpu->isar.id_pfr1;
+ uint64_t pfr1 = GET_IDREG(&cpu->isar.idregs, ID_PFR1);
if (env->gicv3state) {
pfr1 |= 1 << 28;
@@ -7554,7 +7554,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_pfr0 },
+ .resetvalue = GET_IDREG(idregs, ID_PFR0)},
/*
* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
* the value of the GIC field until after we define these regs.
@@ -7565,7 +7565,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.accessfn = access_aa32_tid3,
#ifdef CONFIG_USER_ONLY
.type = ARM_CP_CONST,
- .resetvalue = cpu->isar.id_pfr1,
+ .resetvalue = GET_IDREG(idregs, ID_PFR0),
#else
.type = ARM_CP_NO_RAW,
.accessfn = access_aa32_tid3,
@@ -7907,7 +7907,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_pfr2 },
+ .resetvalue = GET_IDREG(idregs, ID_PFR2)},
{ .name = "ID_DFR1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index c9b535503a4e..d7666047bba4 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -408,8 +408,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ARM64_SYS_REG(3, 0, 0, 3, 1));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2,
ARM64_SYS_REG(3, 0, 0, 3, 2));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr2,
- ARM64_SYS_REG(3, 0, 0, 3, 4));
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_PFR2_EL1);
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1,
ARM64_SYS_REG(3, 0, 0, 3, 5));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5,
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index 31f9bcc49a13..2fe45e0cbd83 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -60,8 +60,8 @@ static void cortex_m0_initfn(Object *obj)
* by looking at ID register fields. We use the same values as
* for the M3.
*/
- cpu->isar.id_pfr0 = 0x00000030;
- cpu->isar.id_pfr1 = 0x00000200;
+ SET_IDREG(idregs, ID_PFR0, 0x00000030);
+ SET_IDREG(idregs, ID_PFR1, 0x00000200);
cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030;
@@ -86,8 +86,8 @@ static void cortex_m3_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
cpu->midr = 0x410fc231;
cpu->pmsav7_dregion = 8;
- cpu->isar.id_pfr0 = 0x00000030;
- cpu->isar.id_pfr1 = 0x00000200;
+ SET_IDREG(idregs, ID_PFR0, 0x00000030);
+ SET_IDREG(idregs, ID_PFR1, 0x00000200);
cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030;
@@ -117,8 +117,8 @@ static void cortex_m4_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110021;
cpu->isar.mvfr1 = 0x11000011;
cpu->isar.mvfr2 = 0x00000000;
- cpu->isar.id_pfr0 = 0x00000030;
- cpu->isar.id_pfr1 = 0x00000200;
+ SET_IDREG(idregs, ID_PFR0, 0x00000030);
+ SET_IDREG(idregs, ID_PFR1, 0x00000200);
cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030;
@@ -148,8 +148,8 @@ static void cortex_m7_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110221;
cpu->isar.mvfr1 = 0x12000011;
cpu->isar.mvfr2 = 0x00000040;
- cpu->isar.id_pfr0 = 0x00000030;
- cpu->isar.id_pfr1 = 0x00000200;
+ SET_IDREG(idregs, ID_PFR0, 0x00000030);
+ SET_IDREG(idregs, ID_PFR1, 0x00000200);
cpu->isar.id_dfr0 = 0x00100000;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00100030;
@@ -181,8 +181,8 @@ static void cortex_m33_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110021;
cpu->isar.mvfr1 = 0x11000011;
cpu->isar.mvfr2 = 0x00000040;
- cpu->isar.id_pfr0 = 0x00000030;
- cpu->isar.id_pfr1 = 0x00000210;
+ SET_IDREG(idregs, ID_PFR0, 0x00000030);
+ SET_IDREG(idregs, ID_PFR1, 0x00000210);
cpu->isar.id_dfr0 = 0x00200000;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00101F40;
@@ -219,8 +219,8 @@ static void cortex_m55_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110221;
cpu->isar.mvfr1 = 0x12100211;
cpu->isar.mvfr2 = 0x00000040;
- cpu->isar.id_pfr0 = 0x20000030;
- cpu->isar.id_pfr1 = 0x00000230;
+ SET_IDREG(idregs, ID_PFR0, 0x20000030);
+ SET_IDREG(idregs, ID_PFR1, 0x00000230);
cpu->isar.id_dfr0 = 0x10200000;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00111040;
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 5ff0e8b0a65c..fc29aa51891c 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -23,18 +23,19 @@
void aa32_max_features(ARMCPU *cpu)
{
uint32_t t;
+ uint64_t *idregs = cpu->isar.idregs;
/* Add additional features supported by QEMU */
- t = GET_IDREG(&cpu->isar.idregs, ID_ISAR5);
+ t = GET_IDREG(idregs, ID_ISAR5);
t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
- SET_IDREG(&cpu->isar.idregs, ID_ISAR5, t);
+ SET_IDREG(idregs, ID_ISAR5, t);
- t = GET_IDREG(&cpu->isar.idregs, ID_ISAR6);
+ t = GET_IDREG(idregs, ID_ISAR6);
t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
@@ -42,7 +43,7 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
- SET_IDREG(&cpu->isar.idregs, ID_ISAR6, t);
+ SET_IDREG(idregs, ID_ISAR6, t);
t = cpu->isar.mvfr1;
t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
@@ -70,16 +71,16 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
cpu->isar.id_mmfr5 = t;
- t = cpu->isar.id_pfr0;
+ t = GET_IDREG(idregs, ID_PFR0);
t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
- cpu->isar.id_pfr0 = t;
+ SET_IDREG(idregs, ID_PFR0, t);
- t = cpu->isar.id_pfr2;
+ t = GET_IDREG(idregs, ID_PFR2);
t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
- cpu->isar.id_pfr2 = t;
+ SET_IDREG(idregs, ID_PFR2, t);
t = cpu->isar.id_dfr0;
t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */
@@ -227,8 +228,8 @@ static void arm1136_r2_initfn(Object *obj)
cpu->isar.mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00050078;
- cpu->isar.id_pfr0 = 0x111;
- cpu->isar.id_pfr1 = 0x1;
+ SET_IDREG(idregs, ID_PFR0, 0x111);
+ SET_IDREG(idregs, ID_PFR1, 0x1);
cpu->isar.id_dfr0 = 0x2;
cpu->id_afr0 = 0x3;
cpu->isar.id_mmfr0 = 0x01130003;
@@ -259,8 +260,8 @@ static void arm1136_initfn(Object *obj)
cpu->isar.mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00050078;
- cpu->isar.id_pfr0 = 0x111;
- cpu->isar.id_pfr1 = 0x1;
+ SET_IDREG(idregs, ID_PFR0, 0x111);
+ SET_IDREG(idregs, ID_PFR1, 0x1);
cpu->isar.id_dfr0 = 0x2;
cpu->id_afr0 = 0x3;
cpu->isar.id_mmfr0 = 0x01130003;
@@ -292,8 +293,8 @@ static void arm1176_initfn(Object *obj)
cpu->isar.mvfr1 = 0x00000000;
cpu->ctr = 0x1dd20d2;
cpu->reset_sctlr = 0x00050078;
- cpu->isar.id_pfr0 = 0x111;
- cpu->isar.id_pfr1 = 0x11;
+ SET_IDREG(idregs, ID_PFR0, 0x111);
+ SET_IDREG(idregs, ID_PFR1, 0x11);
cpu->isar.id_dfr0 = 0x33;
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x01130003;
@@ -322,8 +323,8 @@ static void arm11mpcore_initfn(Object *obj)
cpu->isar.mvfr0 = 0x11111111;
cpu->isar.mvfr1 = 0x00000000;
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
- cpu->isar.id_pfr0 = 0x111;
- cpu->isar.id_pfr1 = 0x1;
+ SET_IDREG(idregs, ID_PFR0, 0x111);
+ SET_IDREG(idregs, ID_PFR1, 0x1);
cpu->isar.id_dfr0 = 0;
cpu->id_afr0 = 0x2;
cpu->isar.id_mmfr0 = 0x01100103;
@@ -362,8 +363,8 @@ static void cortex_a8_initfn(Object *obj)
cpu->isar.mvfr1 = 0x00011111;
cpu->ctr = 0x82048004;
cpu->reset_sctlr = 0x00c50078;
- cpu->isar.id_pfr0 = 0x1031;
- cpu->isar.id_pfr1 = 0x11;
+ SET_IDREG(idregs, ID_PFR0, 0x1031);
+ SET_IDREG(idregs, ID_PFR1, 0x11);
cpu->isar.id_dfr0 = 0x400;
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x31100003;
@@ -438,8 +439,8 @@ static void cortex_a9_initfn(Object *obj)
cpu->isar.mvfr1 = 0x01111111;
cpu->ctr = 0x80038003;
cpu->reset_sctlr = 0x00c50078;
- cpu->isar.id_pfr0 = 0x1031;
- cpu->isar.id_pfr1 = 0x11;
+ SET_IDREG(idregs, ID_PFR0, 0x1031);
+ SET_IDREG(idregs, ID_PFR1, 0x11);
cpu->isar.id_dfr0 = 0x000;
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x00100103;
@@ -504,8 +505,8 @@ static void cortex_a7_initfn(Object *obj)
cpu->isar.mvfr1 = 0x11111111;
cpu->ctr = 0x84448003;
cpu->reset_sctlr = 0x00c50078;
- cpu->isar.id_pfr0 = 0x00001131;
- cpu->isar.id_pfr1 = 0x00011011;
+ SET_IDREG(idregs, ID_PFR0, 0x00001131);
+ SET_IDREG(idregs, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x02010555;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
@@ -556,8 +557,8 @@ static void cortex_a15_initfn(Object *obj)
cpu->isar.mvfr1 = 0x11111111;
cpu->ctr = 0x8444c004;
cpu->reset_sctlr = 0x00c50078;
- cpu->isar.id_pfr0 = 0x00001131;
- cpu->isar.id_pfr1 = 0x00011011;
+ SET_IDREG(idregs, ID_PFR0, 0x00001131);
+ SET_IDREG(idregs, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x02010555;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10201105;
@@ -600,8 +601,8 @@ static void cortex_r5_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_PMSA);
set_feature(&cpu->env, ARM_FEATURE_PMU);
cpu->midr = 0x411fc153; /* r1p3 */
- cpu->isar.id_pfr0 = 0x0131;
- cpu->isar.id_pfr1 = 0x001;
+ SET_IDREG(idregs, ID_PFR0, 0x0131);
+ SET_IDREG(idregs, ID_PFR1, 0x001);
cpu->isar.id_dfr0 = 0x010400;
cpu->id_afr0 = 0x0;
cpu->isar.id_mmfr0 = 0x0210030;
@@ -747,8 +748,8 @@ static void cortex_r52_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x8144c004;
cpu->reset_sctlr = 0x30c50838;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x10111001;
+ SET_IDREG(idregs, ID_PFR0, 0x00000131);
+ SET_IDREG(idregs, ID_PFR1, 0x10111001);
cpu->isar.id_dfr0 = 0x03010006;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00211040;
@@ -979,8 +980,8 @@ static void arm_max_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x8444c004;
cpu->reset_sctlr = 0x00c50838;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x00011011;
+ SET_IDREG(idregs, ID_PFR0, 0x00000131);
+ SET_IDREG(idregs, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 355e3e437304..91fb8a59af56 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -49,8 +49,8 @@ static void aarch64_a35_initfn(Object *obj)
cpu->midr = 0x411fd040;
cpu->revidr = 0;
cpu->ctr = 0x84448004;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x00011011;
+ SET_IDREG(idregs, ID_PFR0, 0x00000131);
+ SET_IDREG(idregs, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105;
@@ -241,9 +241,9 @@ static void aarch64_a55_initfn(Object *obj)
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02122211;
cpu->isar.id_mmfr4 = 0x00021110;
- cpu->isar.id_pfr0 = 0x10010131;
- cpu->isar.id_pfr1 = 0x00011011;
- cpu->isar.id_pfr2 = 0x00000011;
+ SET_IDREG(idregs, ID_PFR0, 0x10010131);
+ SET_IDREG(idregs, ID_PFR1, 0x00011011);
+ SET_IDREG(idregs, ID_PFR2, 0x00000011);
cpu->midr = 0x412FD050; /* r2p0 */
cpu->revidr = 0;
@@ -295,8 +295,8 @@ static void aarch64_a72_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000043;
cpu->ctr = 0x8444c004;
cpu->reset_sctlr = 0x00c50838;
- cpu->isar.id_pfr0 = 0x00000131;
- cpu->isar.id_pfr1 = 0x00011011;
+ SET_IDREG(idregs, ID_PFR0, 0x00000131);
+ SET_IDREG(idregs, ID_PFR1, 0x00011011);
cpu->isar.id_dfr0 = 0x03010066;
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10201105;
@@ -374,9 +374,9 @@ static void aarch64_a76_initfn(Object *obj)
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02122211;
cpu->isar.id_mmfr4 = 0x00021110;
- cpu->isar.id_pfr0 = 0x10010131;
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
- cpu->isar.id_pfr2 = 0x00000011;
+ SET_IDREG(idregs, ID_PFR0, 0x10010131);
+ SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */
+ SET_IDREG(idregs, ID_PFR2, 0x00000011);
cpu->midr = 0x414fd0b1; /* r4p1 */
cpu->revidr = 0;
@@ -622,9 +622,9 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02122211;
cpu->isar.id_mmfr4 = 0x00021110;
- cpu->isar.id_pfr0 = 0x10010131;
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
- cpu->isar.id_pfr2 = 0x00000011;
+ SET_IDREG(idregs, ID_PFR0, 0x10010131);
+ SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */
+ SET_IDREG(idregs, ID_PFR2, 0x00000011);
cpu->midr = 0x414fd0c1; /* r4p1 */
cpu->revidr = 0;
@@ -701,9 +701,9 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
cpu->isar.id_mmfr2 = 0x01260000;
cpu->isar.id_mmfr3 = 0x02122211;
cpu->isar.id_mmfr4 = 0x01021110;
- cpu->isar.id_pfr0 = 0x21110131;
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
- cpu->isar.id_pfr2 = 0x00000011;
+ SET_IDREG(idregs, ID_PFR0, 0x21110131);
+ SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */
+ SET_IDREG(idregs, ID_PFR2, 0x00000011);
cpu->midr = 0x411FD402; /* r1p2 */
cpu->revidr = 0;
@@ -902,8 +902,8 @@ static void aarch64_a710_initfn(Object *obj)
/* Ordered by Section B.4: AArch64 registers */
cpu->midr = 0x412FD471; /* r2p1 */
cpu->revidr = 0;
- cpu->isar.id_pfr0 = 0x21110131;
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
+ SET_IDREG(idregs, ID_PFR0, 0x21110131);
+ SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */
cpu->isar.id_dfr0 = 0x16011099;
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105;
@@ -921,7 +921,7 @@ static void aarch64_a710_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110222;
cpu->isar.mvfr1 = 0x13211111;
cpu->isar.mvfr2 = 0x00000043;
- cpu->isar.id_pfr2 = 0x00000011;
+ SET_IDREG(idregs, ID_PFR2, 0x00000011);
SET_IDREG(idregs, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000221ull);
SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
@@ -1005,8 +1005,8 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
/* Ordered by Section B.5: AArch64 ID registers */
cpu->midr = 0x410FD493; /* r0p3 */
cpu->revidr = 0;
- cpu->isar.id_pfr0 = 0x21110131;
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
+ SET_IDREG(idregs, ID_PFR0, 0x21110131);
+ SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */
cpu->isar.id_dfr0 = 0x16011099;
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105;
@@ -1024,7 +1024,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->isar.mvfr0 = 0x10110222;
cpu->isar.mvfr1 = 0x13211111;
cpu->isar.mvfr2 = 0x00000043;
- cpu->isar.id_pfr2 = 0x00000011;
+ SET_IDREG(idregs, ID_PFR2, 0x00000011);
SET_IDREG(idregs, ID_AA64PFR0, 0x1201111120111112ull); /* GIC filled in later */
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000221ull);
SET_IDREG(idregs, ID_AA64ZFR0, 0x0000110100110021ull); /* with Crypto */
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 11/15] arm/cpu: Store id_dfr0/1 into the idregs array
2025-02-07 11:02 [PATCH 00/15] arm: rework id register storage Cornelia Huck
` (9 preceding siblings ...)
2025-02-07 11:02 ` [PATCH 10/15] arm/cpu: Store id_mfr0/1 " Cornelia Huck
@ 2025-02-07 11:02 ` Cornelia Huck
2025-02-07 11:02 ` [PATCH 12/15] arm/cpu: Store id_mmfr0-5 " Cornelia Huck
` (3 subsequent siblings)
14 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-02-07 11:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
hw/intc/armv7m_nvic.c | 2 +-
target/arm/cpu-features.h | 16 ++++++++--------
target/arm/cpu.c | 13 +++++--------
target/arm/cpu.h | 2 --
target/arm/cpu64.c | 4 ++--
target/arm/helper.c | 4 ++--
target/arm/kvm.c | 6 ++----
target/arm/tcg/cpu-v7m.c | 12 ++++++------
target/arm/tcg/cpu32.c | 30 ++++++++++++++----------------
target/arm/tcg/cpu64.c | 16 ++++++++--------
10 files changed, 48 insertions(+), 57 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 08529b89a6e0..456a1db62bdd 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1274,7 +1274,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_dfr0;
+ return GET_IDREG(idregs, ID_DFR0);
case 0xd4c: /* AFR0. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index a6eda2a1c554..97c7fee70a7b 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -299,22 +299,22 @@ static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id)
{
/* 0xf means "non-standard IMPDEF PMU" */
- return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
- FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
+ return FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) >= 4 &&
+ FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) != 0xf;
}
static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id)
{
/* 0xf means "non-standard IMPDEF PMU" */
- return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 &&
- FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
+ return FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) >= 5 &&
+ FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) != 0xf;
}
static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id)
{
/* 0xf means "non-standard IMPDEF PMU" */
- return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 &&
- FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
+ return FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) >= 6 &&
+ FIELD_EX32_IDREG(&id->idregs, ID_DFR0, PERFMON) != 0xf;
}
static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
@@ -359,12 +359,12 @@ static inline bool isar_feature_aa32_ssbs(const ARMISARegisters *id)
static inline bool isar_feature_aa32_debugv7p1(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 5;
+ return FIELD_EX32_IDREG(&id->idregs, ID_DFR0, COPDBG) >= 5;
}
static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >= 8;
+ return FIELD_EX32_IDREG(&id->idregs, ID_DFR0, COPDBG) >= 8;
}
static inline bool isar_feature_aa32_doublelock(const ARMISARegisters *id)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index da11b59ba843..bfca468fb342 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2341,7 +2341,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
* feature registers as well.
*/
FIELD_DP32_IDREG(idregs, ID_PFR1, SECURITY, 0);
- cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSDBG, 0);
+ FIELD_DP32_IDREG(idregs, ID_DFR0, COPSDBG, 0);
FIELD_DP64_IDREG(idregs, ID_AA64PFR0, EL3, 0);
/* Disable the realm management extension, which requires EL3. */
@@ -2369,7 +2369,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
#endif
} else {
FIELD_DP64_IDREG(idregs, ID_AA64DFR0, PMUVER, 0);
- cpu->isar.id_dfr0 = FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFMON, 0);
+ FIELD_DP32_IDREG(idregs, ID_DFR0, PERFMON, 0);
cpu->pmceid0 = 0;
cpu->pmceid1 = 0;
}
@@ -2432,15 +2432,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEBUFFER, 0);
/* FEAT_TRF (Self-hosted Trace Extension) */
FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEFILT, 0);
- cpu->isar.id_dfr0 =
- FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0);
+ FIELD_DP32_IDREG(idregs, ID_DFR0, TRACEFILT, 0);
/* Trace Macrocell system register access */
FIELD_DP64_IDREG(idregs, ID_AA64DFR0, TRACEVER, 0);
- cpu->isar.id_dfr0 =
- FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0);
+ FIELD_DP32_IDREG(idregs, ID_DFR0, COPTRC, 0);
/* Memory mapped trace */
- cpu->isar.id_dfr0 =
- FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0);
+ FIELD_DP32_IDREG(idregs, ID_DFR0, MMAPTRC, 0);
/* FEAT_AMU (Activity Monitors Extension) */
FIELD_DP64_IDREG(idregs, ID_AA64PFR0, AMU, 0);
FIELD_DP32_IDREG(idregs, ID_PFR0, AMU, 0);
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 6c3dbf0e607c..215ebf165e6b 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1052,8 +1052,6 @@ struct ArchCPU {
uint32_t mvfr0;
uint32_t mvfr1;
uint32_t mvfr2;
- uint32_t id_dfr0;
- uint32_t id_dfr1;
uint32_t dbgdidr;
uint32_t dbgdevid;
uint32_t dbgdevid1;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 4efb20069b2b..9f83984fa900 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -632,7 +632,7 @@ static void aarch64_a57_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50838;
SET_IDREG(idregs, ID_PFR0, 0x00000131);
SET_IDREG(idregs, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x03010066;
+ SET_IDREG(idregs, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -694,7 +694,7 @@ static void aarch64_a53_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50838;
SET_IDREG(idregs, ID_PFR0, 0x00000131);
SET_IDREG(idregs, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x03010066;
+ SET_IDREG(idregs, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
cpu->isar.id_mmfr1 = 0x40000000;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a3edd171ddf8..e4a7d2493305 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7577,7 +7577,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_dfr0 },
+ .resetvalue = GET_IDREG(idregs, ID_DFR0)},
{ .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
@@ -7912,7 +7912,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_dfr1 },
+ .resetvalue = GET_IDREG(idregs, ID_DFR1)},
{ .name = "ID_MMFR5", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index d7666047bba4..bea844adb07b 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -382,8 +382,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
*/
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR0_EL1);
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR1_EL1);
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
- ARM64_SYS_REG(3, 0, 0, 1, 2));
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_DFR0_EL1);
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
ARM64_SYS_REG(3, 0, 0, 1, 4));
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
@@ -409,8 +408,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2,
ARM64_SYS_REG(3, 0, 0, 3, 2));
err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_PFR2_EL1);
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr1,
- ARM64_SYS_REG(3, 0, 0, 3, 5));
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_DFR1_EL1);
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5,
ARM64_SYS_REG(3, 0, 0, 3, 6));
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index 2fe45e0cbd83..2817d81ae8f5 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -62,7 +62,7 @@ static void cortex_m0_initfn(Object *obj)
*/
SET_IDREG(idregs, ID_PFR0, 0x00000030);
SET_IDREG(idregs, ID_PFR1, 0x00000200);
- cpu->isar.id_dfr0 = 0x00100000;
+ SET_IDREG(idregs, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -88,7 +88,7 @@ static void cortex_m3_initfn(Object *obj)
cpu->pmsav7_dregion = 8;
SET_IDREG(idregs, ID_PFR0, 0x00000030);
SET_IDREG(idregs, ID_PFR1, 0x00000200);
- cpu->isar.id_dfr0 = 0x00100000;
+ SET_IDREG(idregs, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -119,7 +119,7 @@ static void cortex_m4_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000000;
SET_IDREG(idregs, ID_PFR0, 0x00000030);
SET_IDREG(idregs, ID_PFR1, 0x00000200);
- cpu->isar.id_dfr0 = 0x00100000;
+ SET_IDREG(idregs, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00000030;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -150,7 +150,7 @@ static void cortex_m7_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000040;
SET_IDREG(idregs, ID_PFR0, 0x00000030);
SET_IDREG(idregs, ID_PFR1, 0x00000200);
- cpu->isar.id_dfr0 = 0x00100000;
+ SET_IDREG(idregs, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00100030;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -183,7 +183,7 @@ static void cortex_m33_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000040;
SET_IDREG(idregs, ID_PFR0, 0x00000030);
SET_IDREG(idregs, ID_PFR1, 0x00000210);
- cpu->isar.id_dfr0 = 0x00200000;
+ SET_IDREG(idregs, ID_DFR0, 0x00200000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00101F40;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -221,7 +221,7 @@ static void cortex_m55_initfn(Object *obj)
cpu->isar.mvfr2 = 0x00000040;
SET_IDREG(idregs, ID_PFR0, 0x20000030);
SET_IDREG(idregs, ID_PFR1, 0x00000230);
- cpu->isar.id_dfr0 = 0x10200000;
+ SET_IDREG(idregs, ID_DFR0, 0x10200000);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00111040;
cpu->isar.id_mmfr1 = 0x00000000;
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index fc29aa51891c..1d2261865b39 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -82,11 +82,11 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
SET_IDREG(idregs, ID_PFR2, t);
- t = cpu->isar.id_dfr0;
+ t = GET_IDREG(idregs, ID_DFR0);
t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */
t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */
t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
- cpu->isar.id_dfr0 = t;
+ SET_IDREG(idregs, ID_DFR0, t);
/* Debug ID registers. */
@@ -116,9 +116,7 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, DBGDEVID1, PCSROFFSET, 2);
cpu->isar.dbgdevid1 = t;
- t = cpu->isar.id_dfr1;
- t = FIELD_DP32(t, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
- cpu->isar.id_dfr1 = t;
+ FIELD_DP32_IDREG(idregs, ID_DFR1, HPMN0, 1); /* FEAT_HPMN0 */
}
/* CPU models. These are not needed for the AArch64 linux-user build. */
@@ -230,7 +228,7 @@ static void arm1136_r2_initfn(Object *obj)
cpu->reset_sctlr = 0x00050078;
SET_IDREG(idregs, ID_PFR0, 0x111);
SET_IDREG(idregs, ID_PFR1, 0x1);
- cpu->isar.id_dfr0 = 0x2;
+ SET_IDREG(idregs, ID_DFR0, 0x2);
cpu->id_afr0 = 0x3;
cpu->isar.id_mmfr0 = 0x01130003;
cpu->isar.id_mmfr1 = 0x10030302;
@@ -262,7 +260,7 @@ static void arm1136_initfn(Object *obj)
cpu->reset_sctlr = 0x00050078;
SET_IDREG(idregs, ID_PFR0, 0x111);
SET_IDREG(idregs, ID_PFR1, 0x1);
- cpu->isar.id_dfr0 = 0x2;
+ SET_IDREG(idregs, ID_DFR0, 0x2);
cpu->id_afr0 = 0x3;
cpu->isar.id_mmfr0 = 0x01130003;
cpu->isar.id_mmfr1 = 0x10030302;
@@ -295,7 +293,7 @@ static void arm1176_initfn(Object *obj)
cpu->reset_sctlr = 0x00050078;
SET_IDREG(idregs, ID_PFR0, 0x111);
SET_IDREG(idregs, ID_PFR1, 0x11);
- cpu->isar.id_dfr0 = 0x33;
+ SET_IDREG(idregs, ID_DFR0, 0x33);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x01130003;
cpu->isar.id_mmfr1 = 0x10030302;
@@ -325,7 +323,7 @@ static void arm11mpcore_initfn(Object *obj)
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
SET_IDREG(idregs, ID_PFR0, 0x111);
SET_IDREG(idregs, ID_PFR1, 0x1);
- cpu->isar.id_dfr0 = 0;
+ SET_IDREG(idregs, ID_DFR0, 0);
cpu->id_afr0 = 0x2;
cpu->isar.id_mmfr0 = 0x01100103;
cpu->isar.id_mmfr1 = 0x10020302;
@@ -365,7 +363,7 @@ static void cortex_a8_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50078;
SET_IDREG(idregs, ID_PFR0, 0x1031);
SET_IDREG(idregs, ID_PFR1, 0x11);
- cpu->isar.id_dfr0 = 0x400;
+ SET_IDREG(idregs, ID_DFR0, 0x400);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x31100003;
cpu->isar.id_mmfr1 = 0x20000000;
@@ -441,7 +439,7 @@ static void cortex_a9_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50078;
SET_IDREG(idregs, ID_PFR0, 0x1031);
SET_IDREG(idregs, ID_PFR1, 0x11);
- cpu->isar.id_dfr0 = 0x000;
+ SET_IDREG(idregs, ID_DFR0, 0x000);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x00100103;
cpu->isar.id_mmfr1 = 0x20000000;
@@ -507,7 +505,7 @@ static void cortex_a7_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50078;
SET_IDREG(idregs, ID_PFR0, 0x00001131);
SET_IDREG(idregs, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x02010555;
+ SET_IDREG(idregs, ID_DFR0, 0x02010555);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -559,7 +557,7 @@ static void cortex_a15_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50078;
SET_IDREG(idregs, ID_PFR0, 0x00001131);
SET_IDREG(idregs, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x02010555;
+ SET_IDREG(idregs, ID_DFR0, 0x02010555);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x20000000;
@@ -603,7 +601,7 @@ static void cortex_r5_initfn(Object *obj)
cpu->midr = 0x411fc153; /* r1p3 */
SET_IDREG(idregs, ID_PFR0, 0x0131);
SET_IDREG(idregs, ID_PFR1, 0x001);
- cpu->isar.id_dfr0 = 0x010400;
+ SET_IDREG(idregs, ID_DFR0, 0x010400);
cpu->id_afr0 = 0x0;
cpu->isar.id_mmfr0 = 0x0210030;
cpu->isar.id_mmfr1 = 0x00000000;
@@ -750,7 +748,7 @@ static void cortex_r52_initfn(Object *obj)
cpu->reset_sctlr = 0x30c50838;
SET_IDREG(idregs, ID_PFR0, 0x00000131);
SET_IDREG(idregs, ID_PFR1, 0x10111001);
- cpu->isar.id_dfr0 = 0x03010006;
+ SET_IDREG(idregs, ID_DFR0, 0x03010006);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x00211040;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -982,7 +980,7 @@ static void arm_max_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50838;
SET_IDREG(idregs, ID_PFR0, 0x00000131);
SET_IDREG(idregs, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x03010066;
+ SET_IDREG(idregs, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10101105;
cpu->isar.id_mmfr1 = 0x40000000;
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 91fb8a59af56..eb42633f3d80 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -51,7 +51,7 @@ static void aarch64_a35_initfn(Object *obj)
cpu->ctr = 0x84448004;
SET_IDREG(idregs, ID_PFR0, 0x00000131);
SET_IDREG(idregs, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x03010066;
+ SET_IDREG(idregs, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -228,7 +228,7 @@ static void aarch64_a55_initfn(Object *obj)
SET_IDREG(idregs, ID_AA64PFR0, 0x0000000010112222ull);
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
+ SET_IDREG(idregs, ID_DFR0, 0x04010088);
SET_IDREG(idregs, ID_ISAR0, 0x02101110);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232042);
@@ -297,7 +297,7 @@ static void aarch64_a72_initfn(Object *obj)
cpu->reset_sctlr = 0x00c50838;
SET_IDREG(idregs, ID_PFR0, 0x00000131);
SET_IDREG(idregs, ID_PFR1, 0x00011011);
- cpu->isar.id_dfr0 = 0x03010066;
+ SET_IDREG(idregs, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -361,7 +361,7 @@ static void aarch64_a76_initfn(Object *obj)
SET_IDREG(idregs, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000010ull);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
+ SET_IDREG(idregs, ID_DFR0, 0x04010088);
SET_IDREG(idregs, ID_ISAR0, 0x02101110);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232042);
@@ -609,7 +609,7 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
SET_IDREG(idregs, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in later */
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x04010088;
+ SET_IDREG(idregs, ID_DFR0, 0x04010088);
SET_IDREG(idregs, ID_ISAR0, 0x02101110);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232042);
@@ -688,7 +688,7 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
SET_IDREG(idregs, ID_AA64PFR0, 0x1101110120111112ull); /* GIC filled in later */
SET_IDREG(idregs, ID_AA64PFR1, 0x0000000000000020ull);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_dfr0 = 0x15011099;
+ SET_IDREG(idregs, ID_DFR0, 0x15011099);
SET_IDREG(idregs, ID_ISAR0, 0x02101110);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232042);
@@ -904,7 +904,7 @@ static void aarch64_a710_initfn(Object *obj)
cpu->revidr = 0;
SET_IDREG(idregs, ID_PFR0, 0x21110131);
SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */
- cpu->isar.id_dfr0 = 0x16011099;
+ SET_IDREG(idregs, ID_DFR0, 0x16011099);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
@@ -1007,7 +1007,7 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
cpu->revidr = 0;
SET_IDREG(idregs, ID_PFR0, 0x21110131);
SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */
- cpu->isar.id_dfr0 = 0x16011099;
+ SET_IDREG(idregs, ID_DFR0, 0x16011099);
cpu->id_afr0 = 0;
cpu->isar.id_mmfr0 = 0x10201105;
cpu->isar.id_mmfr1 = 0x40000000;
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 12/15] arm/cpu: Store id_mmfr0-5 into the idregs array
2025-02-07 11:02 [PATCH 00/15] arm: rework id register storage Cornelia Huck
` (10 preceding siblings ...)
2025-02-07 11:02 ` [PATCH 11/15] arm/cpu: Store id_dfr0/1 " Cornelia Huck
@ 2025-02-07 11:02 ` Cornelia Huck
2025-02-07 11:02 ` [PATCH 13/15] arm/cpu: Add infra to handle generated ID register definitions Cornelia Huck
` (2 subsequent siblings)
14 siblings, 0 replies; 29+ messages in thread
From: Cornelia Huck @ 2025-02-07 11:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
hw/intc/armv7m_nvic.c | 8 ++--
target/arm/cpu-features.h | 18 ++++----
target/arm/cpu.h | 6 ---
target/arm/cpu64.c | 16 +++----
target/arm/helper.c | 12 ++---
target/arm/kvm.c | 18 +++-----
target/arm/tcg/cpu-v7m.c | 48 ++++++++++----------
target/arm/tcg/cpu32.c | 94 +++++++++++++++++++--------------------
target/arm/tcg/cpu64.c | 76 +++++++++++++++----------------
9 files changed, 140 insertions(+), 156 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 456a1db62bdd..86e18cac116c 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -1284,22 +1284,22 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_mmfr0;
+ return GET_IDREG(idregs, ID_MMFR0);
case 0xd54: /* MMFR1. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_mmfr1;
+ return GET_IDREG(idregs, ID_MMFR1);
case 0xd58: /* MMFR2. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_mmfr2;
+ return GET_IDREG(idregs, ID_MMFR2);
case 0xd5c: /* MMFR3. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
}
- return cpu->isar.id_mmfr3;
+ return GET_IDREG(idregs, ID_MMFR3);
case 0xd60: /* ISAR0. */
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
goto bad_offset;
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 97c7fee70a7b..90ada4c2d227 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -283,17 +283,17 @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
+ return FIELD_EX32_IDREG(&id->idregs, ID_MMFR0, VMSA) >= 4;
}
static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_MMFR3, PAN) != 0;
}
static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
+ return FIELD_EX32_IDREG(&id->idregs, ID_MMFR3, PAN) >= 2;
}
static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id)
@@ -319,32 +319,32 @@ static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id)
static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, HPDS) != 0;
}
static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, AC2) != 0;
}
static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, CCIDX) != 0;
}
static inline bool isar_feature_aa32_tts2uxn(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, XNX) != 0;
+ return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, XNX) != 0;
}
static inline bool isar_feature_aa32_half_evt(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 1;
+ return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, EVT) >= 1;
}
static inline bool isar_feature_aa32_evt(const ARMISARegisters *id)
{
- return FIELD_EX32(id->id_mmfr4, ID_MMFR4, EVT) >= 2;
+ return FIELD_EX32_IDREG(&id->idregs, ID_MMFR4, EVT) >= 2;
}
static inline bool isar_feature_aa32_dit(const ARMISARegisters *id)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 215ebf165e6b..f6e1836d0fdd 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1043,12 +1043,6 @@ struct ArchCPU {
* field by reading the value from the KVM vCPU.
*/
struct ARMISARegisters {
- uint32_t id_mmfr0;
- uint32_t id_mmfr1;
- uint32_t id_mmfr2;
- uint32_t id_mmfr3;
- uint32_t id_mmfr4;
- uint32_t id_mmfr5;
uint32_t mvfr0;
uint32_t mvfr1;
uint32_t mvfr2;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 9f83984fa900..beba1733c99f 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -634,10 +634,10 @@ static void aarch64_a57_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x00011011);
SET_IDREG(idregs, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x10101105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02102211;
+ SET_IDREG(idregs, ID_MMFR0, 0x10101105);
+ SET_IDREG(idregs, ID_MMFR1, 0x40000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01260000);
+ SET_IDREG(idregs, ID_MMFR3, 0x02102211);
SET_IDREG(idregs, ID_ISAR0, 0x02101110);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232042);
@@ -696,10 +696,10 @@ static void aarch64_a53_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x00011011);
SET_IDREG(idregs, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x10101105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02102211;
+ SET_IDREG(idregs, ID_MMFR0, 0x10101105);
+ SET_IDREG(idregs, ID_MMFR1, 0x40000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01260000);
+ SET_IDREG(idregs, ID_MMFR3, 0x02102211);
SET_IDREG(idregs, ID_ISAR0, 0x02101110);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232042);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index e4a7d2493305..65b85cf5cc25 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7587,22 +7587,22 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_mmfr0 },
+ .resetvalue = GET_IDREG(idregs, ID_MMFR0)},
{ .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_mmfr1 },
+ .resetvalue = GET_IDREG(idregs, ID_MMFR1)},
{ .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_mmfr2 },
+ .resetvalue = GET_IDREG(idregs, ID_MMFR2)},
{ .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_mmfr3 },
+ .resetvalue = GET_IDREG(idregs, ID_MMFR3)},
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
.access = PL1_R, .type = ARM_CP_CONST,
@@ -7637,7 +7637,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa32_tid3,
- .resetvalue = cpu->isar.id_mmfr4 },
+ .resetvalue = GET_IDREG(idregs, ID_MMFR4)},
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST,
@@ -7917,7 +7917,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = cpu->isar.id_mmfr5 },
+ .resetvalue = GET_IDREG(idregs, ID_MMFR5)},
{ .name = "RES_0_C0_C3_7", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index bea844adb07b..8881005ad9e6 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -383,14 +383,10 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR0_EL1);
err |= get_host_cpu_reg64(fd, ahcf, SYS_ID_AA64PFR1_EL1);
err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_DFR0_EL1);
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
- ARM64_SYS_REG(3, 0, 0, 1, 4));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1,
- ARM64_SYS_REG(3, 0, 0, 1, 5));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2,
- ARM64_SYS_REG(3, 0, 0, 1, 6));
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3,
- ARM64_SYS_REG(3, 0, 0, 1, 7));
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR0_EL1);
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR1_EL1);
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR2_EL1);
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR3_EL1);
err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR0_EL1);
err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR1_EL1);
err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR2_EL1);
@@ -398,8 +394,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR4_EL1);
err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR5_EL1);
err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_ISAR6_EL1);
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4,
- ARM64_SYS_REG(3, 0, 0, 2, 6));
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR4_EL1);
err |= read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0,
ARM64_SYS_REG(3, 0, 0, 3, 0));
@@ -409,8 +404,7 @@ static bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ARM64_SYS_REG(3, 0, 0, 3, 2));
err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_PFR2_EL1);
err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_DFR1_EL1);
- err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr5,
- ARM64_SYS_REG(3, 0, 0, 3, 6));
+ err |= get_host_cpu_reg32(fd, ahcf, SYS_ID_MMFR5_EL1);
/*
* DBGDIDR is a bit complicated because the kernel doesn't
diff --git a/target/arm/tcg/cpu-v7m.c b/target/arm/tcg/cpu-v7m.c
index 2817d81ae8f5..5bff97beb704 100644
--- a/target/arm/tcg/cpu-v7m.c
+++ b/target/arm/tcg/cpu-v7m.c
@@ -64,10 +64,10 @@ static void cortex_m0_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x00000200);
SET_IDREG(idregs, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00000030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x00000000;
- cpu->isar.id_mmfr3 = 0x00000000;
+ SET_IDREG(idregs, ID_MMFR0, 0x00000030);
+ SET_IDREG(idregs, ID_MMFR1, 0x00000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x00000000);
+ SET_IDREG(idregs, ID_MMFR3, 0x00000000);
SET_IDREG(idregs, ID_ISAR0, 0x01141110);
SET_IDREG(idregs, ID_ISAR1, 0x02111000);
SET_IDREG(idregs, ID_ISAR2, 0x21112231);
@@ -90,10 +90,10 @@ static void cortex_m3_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x00000200);
SET_IDREG(idregs, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00000030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x00000000;
- cpu->isar.id_mmfr3 = 0x00000000;
+ SET_IDREG(idregs, ID_MMFR0, 0x00000030);
+ SET_IDREG(idregs, ID_MMFR1, 0x00000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x00000000);
+ SET_IDREG(idregs, ID_MMFR3, 0x00000000);
SET_IDREG(idregs, ID_ISAR0, 0x01141110);
SET_IDREG(idregs, ID_ISAR1, 0x02111000);
SET_IDREG(idregs, ID_ISAR2, 0x21112231);
@@ -121,10 +121,10 @@ static void cortex_m4_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x00000200);
SET_IDREG(idregs, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00000030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x00000000;
- cpu->isar.id_mmfr3 = 0x00000000;
+ SET_IDREG(idregs, ID_MMFR0, 0x00000030);
+ SET_IDREG(idregs, ID_MMFR1, 0x00000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x00000000);
+ SET_IDREG(idregs, ID_MMFR3, 0x00000000);
SET_IDREG(idregs, ID_ISAR0, 0x01141110);
SET_IDREG(idregs, ID_ISAR1, 0x02111000);
SET_IDREG(idregs, ID_ISAR2, 0x21112231);
@@ -152,10 +152,10 @@ static void cortex_m7_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x00000200);
SET_IDREG(idregs, ID_DFR0, 0x00100000);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00100030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x01000000;
- cpu->isar.id_mmfr3 = 0x00000000;
+ SET_IDREG(idregs, ID_MMFR0, 0x00100030);
+ SET_IDREG(idregs, ID_MMFR1, 0x00000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01000000);
+ SET_IDREG(idregs, ID_MMFR3, 0x00000000);
SET_IDREG(idregs, ID_ISAR0, 0x01101110);
SET_IDREG(idregs, ID_ISAR1, 0x02112000);
SET_IDREG(idregs, ID_ISAR2, 0x20232231);
@@ -185,10 +185,10 @@ static void cortex_m33_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x00000210);
SET_IDREG(idregs, ID_DFR0, 0x00200000);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00101F40;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x01000000;
- cpu->isar.id_mmfr3 = 0x00000000;
+ SET_IDREG(idregs, ID_MMFR0, 0x00101F40);
+ SET_IDREG(idregs, ID_MMFR1, 0x00000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01000000);
+ SET_IDREG(idregs, ID_MMFR3, 0x00000000);
SET_IDREG(idregs, ID_ISAR0, 0x01101110);
SET_IDREG(idregs, ID_ISAR1, 0x02212000);
SET_IDREG(idregs, ID_ISAR2, 0x20232232);
@@ -223,10 +223,10 @@ static void cortex_m55_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x00000230);
SET_IDREG(idregs, ID_DFR0, 0x10200000);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00111040;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x01000000;
- cpu->isar.id_mmfr3 = 0x00000011;
+ SET_IDREG(idregs, ID_MMFR0, 0x00111040);
+ SET_IDREG(idregs, ID_MMFR1, 0x00000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01000000);
+ SET_IDREG(idregs, ID_MMFR3, 0x00000011);
SET_IDREG(idregs, ID_ISAR0, 0x01103110);
SET_IDREG(idregs, ID_ISAR1, 0x02212000);
SET_IDREG(idregs, ID_ISAR2, 0x20232232);
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 1d2261865b39..a03642b07536 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -55,21 +55,17 @@ void aa32_max_features(ARMCPU *cpu)
t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
cpu->isar.mvfr2 = t;
- t = cpu->isar.id_mmfr3;
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
- cpu->isar.id_mmfr3 = t;
+ FIELD_DP32_IDREG(idregs, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
- t = cpu->isar.id_mmfr4;
+ t = GET_IDREG(idregs, ID_MMFR4);
t = FIELD_DP32(t, ID_MMFR4, HPDS, 2); /* FEAT_HPDS2 */
t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */
- cpu->isar.id_mmfr4 = t;
+ SET_IDREG(idregs, ID_MMFR4, t);
- t = cpu->isar.id_mmfr5;
- t = FIELD_DP32(t, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
- cpu->isar.id_mmfr5 = t;
+ FIELD_DP32_IDREG(idregs, ID_MMFR5, ETS, 2); /* FEAT_ETS2 */
t = GET_IDREG(idregs, ID_PFR0);
t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CSV2 */
@@ -230,9 +226,9 @@ static void arm1136_r2_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x1);
SET_IDREG(idregs, ID_DFR0, 0x2);
cpu->id_afr0 = 0x3;
- cpu->isar.id_mmfr0 = 0x01130003;
- cpu->isar.id_mmfr1 = 0x10030302;
- cpu->isar.id_mmfr2 = 0x01222110;
+ SET_IDREG(idregs, ID_MMFR0, 0x01130003);
+ SET_IDREG(idregs, ID_MMFR1, 0x10030302);
+ SET_IDREG(idregs, ID_MMFR2, 0x01222110);
SET_IDREG(idregs, ID_ISAR0, 0x00140011);
SET_IDREG(idregs, ID_ISAR1, 0x12002111);
SET_IDREG(idregs, ID_ISAR2, 0x11231111);
@@ -262,9 +258,9 @@ static void arm1136_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x1);
SET_IDREG(idregs, ID_DFR0, 0x2);
cpu->id_afr0 = 0x3;
- cpu->isar.id_mmfr0 = 0x01130003;
- cpu->isar.id_mmfr1 = 0x10030302;
- cpu->isar.id_mmfr2 = 0x01222110;
+ SET_IDREG(idregs, ID_MMFR0, 0x01130003);
+ SET_IDREG(idregs, ID_MMFR1, 0x10030302);
+ SET_IDREG(idregs, ID_MMFR2, 0x01222110);
SET_IDREG(idregs, ID_ISAR0, 0x00140011);
SET_IDREG(idregs, ID_ISAR1, 0x12002111);
SET_IDREG(idregs, ID_ISAR2, 0x11231111);
@@ -295,9 +291,9 @@ static void arm1176_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x11);
SET_IDREG(idregs, ID_DFR0, 0x33);
cpu->id_afr0 = 0;
- cpu->isar.id_mmfr0 = 0x01130003;
- cpu->isar.id_mmfr1 = 0x10030302;
- cpu->isar.id_mmfr2 = 0x01222100;
+ SET_IDREG(idregs, ID_MMFR0, 0x01130003);
+ SET_IDREG(idregs, ID_MMFR1, 0x10030302);
+ SET_IDREG(idregs, ID_MMFR2, 0x01222100);
SET_IDREG(idregs, ID_ISAR0, 0x0140011);
SET_IDREG(idregs, ID_ISAR1, 0x12002111);
SET_IDREG(idregs, ID_ISAR2, 0x11231121);
@@ -325,9 +321,9 @@ static void arm11mpcore_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x1);
SET_IDREG(idregs, ID_DFR0, 0);
cpu->id_afr0 = 0x2;
- cpu->isar.id_mmfr0 = 0x01100103;
- cpu->isar.id_mmfr1 = 0x10020302;
- cpu->isar.id_mmfr2 = 0x01222000;
+ SET_IDREG(idregs, ID_MMFR0, 0x01100103);
+ SET_IDREG(idregs, ID_MMFR1, 0x10020302);
+ SET_IDREG(idregs, ID_MMFR2, 0x01222000);
SET_IDREG(idregs, ID_ISAR0, 0x00100011);
SET_IDREG(idregs, ID_ISAR1, 0x12002111);
SET_IDREG(idregs, ID_ISAR2, 0x11221011);
@@ -365,10 +361,10 @@ static void cortex_a8_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x11);
SET_IDREG(idregs, ID_DFR0, 0x400);
cpu->id_afr0 = 0;
- cpu->isar.id_mmfr0 = 0x31100003;
- cpu->isar.id_mmfr1 = 0x20000000;
- cpu->isar.id_mmfr2 = 0x01202000;
- cpu->isar.id_mmfr3 = 0x11;
+ SET_IDREG(idregs, ID_MMFR0, 0x31100003);
+ SET_IDREG(idregs, ID_MMFR1, 0x20000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01202000);
+ SET_IDREG(idregs, ID_MMFR3, 0x11);
SET_IDREG(idregs, ID_ISAR0, 0x00101111);
SET_IDREG(idregs, ID_ISAR1, 0x12112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232031);
@@ -441,10 +437,10 @@ static void cortex_a9_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x11);
SET_IDREG(idregs, ID_DFR0, 0x000);
cpu->id_afr0 = 0;
- cpu->isar.id_mmfr0 = 0x00100103;
- cpu->isar.id_mmfr1 = 0x20000000;
- cpu->isar.id_mmfr2 = 0x01230000;
- cpu->isar.id_mmfr3 = 0x00002111;
+ SET_IDREG(idregs, ID_MMFR0, 0x00100103);
+ SET_IDREG(idregs, ID_MMFR1, 0x20000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01230000);
+ SET_IDREG(idregs, ID_MMFR3, 0x00002111);
SET_IDREG(idregs, ID_ISAR0, 0x00101111);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232041);
@@ -507,10 +503,10 @@ static void cortex_a7_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x00011011);
SET_IDREG(idregs, ID_DFR0, 0x02010555);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x10101105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01240000;
- cpu->isar.id_mmfr3 = 0x02102211;
+ SET_IDREG(idregs, ID_MMFR0, 0x10101105);
+ SET_IDREG(idregs, ID_MMFR1, 0x40000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01240000);
+ SET_IDREG(idregs, ID_MMFR3, 0x02102211);
/*
* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
* table 4-41 gives 0x02101110, which includes the arm div insns.
@@ -559,10 +555,10 @@ static void cortex_a15_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x00011011);
SET_IDREG(idregs, ID_DFR0, 0x02010555);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x20000000;
- cpu->isar.id_mmfr2 = 0x01240000;
- cpu->isar.id_mmfr3 = 0x02102211;
+ SET_IDREG(idregs, ID_MMFR0, 0x10201105);
+ SET_IDREG(idregs, ID_MMFR1, 0x20000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01240000);
+ SET_IDREG(idregs, ID_MMFR3, 0x02102211);
SET_IDREG(idregs, ID_ISAR0, 0x02101110);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232041);
@@ -603,10 +599,10 @@ static void cortex_r5_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x001);
SET_IDREG(idregs, ID_DFR0, 0x010400);
cpu->id_afr0 = 0x0;
- cpu->isar.id_mmfr0 = 0x0210030;
- cpu->isar.id_mmfr1 = 0x00000000;
- cpu->isar.id_mmfr2 = 0x01200000;
- cpu->isar.id_mmfr3 = 0x0211;
+ SET_IDREG(idregs, ID_MMFR0, 0x0210030);
+ SET_IDREG(idregs, ID_MMFR1, 0x00000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01200000);
+ SET_IDREG(idregs, ID_MMFR3, 0x0211);
SET_IDREG(idregs, ID_ISAR0, 0x02101111);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232141);
@@ -750,11 +746,11 @@ static void cortex_r52_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x10111001);
SET_IDREG(idregs, ID_DFR0, 0x03010006);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x00211040;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01200000;
- cpu->isar.id_mmfr3 = 0xf0102211;
- cpu->isar.id_mmfr4 = 0x00000010;
+ SET_IDREG(idregs, ID_MMFR0, 0x00211040);
+ SET_IDREG(idregs, ID_MMFR1, 0x40000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01200000);
+ SET_IDREG(idregs, ID_MMFR3, 0xf0102211);
+ SET_IDREG(idregs, ID_MMFR4, 0x00000010);
SET_IDREG(idregs, ID_ISAR0, 0x02101110);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232142);
@@ -982,10 +978,10 @@ static void arm_max_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x00011011);
SET_IDREG(idregs, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x10101105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02102211;
+ ET_IDREG(idregs, ID_MMFR0, 0x10101105);
+ ET_IDREG(idregs, ID_MMFR1, 0x40000000);
+ ET_IDREG(idregs, ID_MMFR2, 0x01260000);
+ ET_IDREG(idregs, ID_MMFR3, 0x02102211);
SET_IDREG(idregs, ID_ISAR0, 0x02101110);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232042);
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index eb42633f3d80..54925b273efc 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -53,10 +53,10 @@ static void aarch64_a35_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x00011011);
SET_IDREG(idregs, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02102211;
+ SET_IDREG(idregs, ID_MMFR0, 0x10201105);
+ SET_IDREG(idregs, ID_MMFR1, 0x40000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01260000);
+ SET_IDREG(idregs, ID_MMFR3, 0x02102211);
SET_IDREG(idregs, ID_ISAR0, 0x02101110);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232042);
@@ -236,11 +236,11 @@ static void aarch64_a55_initfn(Object *obj)
SET_IDREG(idregs, ID_ISAR4, 0x00011142);
SET_IDREG(idregs, ID_ISAR5, 0x01011121);
SET_IDREG(idregs, ID_ISAR6, 0x00000010);
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_mmfr4 = 0x00021110;
+ SET_IDREG(idregs, ID_MMFR0, 0x10201105);
+ SET_IDREG(idregs, ID_MMFR1, 0x40000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01260000);
+ SET_IDREG(idregs, ID_MMFR3, 0x02122211);
+ SET_IDREG(idregs, ID_MMFR4, 0x00021110);
SET_IDREG(idregs, ID_PFR0, 0x10010131);
SET_IDREG(idregs, ID_PFR1, 0x00011011);
SET_IDREG(idregs, ID_PFR2, 0x00000011);
@@ -299,10 +299,10 @@ static void aarch64_a72_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x00011011);
SET_IDREG(idregs, ID_DFR0, 0x03010066);
cpu->id_afr0 = 0x00000000;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02102211;
+ SET_IDREG(idregs, ID_MMFR0, 0x10201105);
+ SET_IDREG(idregs, ID_MMFR1, 0x40000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01260000);
+ SET_IDREG(idregs, ID_MMFR3, 0x02102211);
SET_IDREG(idregs, ID_ISAR0, 0x02101110);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232042);
@@ -369,11 +369,11 @@ static void aarch64_a76_initfn(Object *obj)
SET_IDREG(idregs, ID_ISAR4, 0x00010142);
SET_IDREG(idregs, ID_ISAR5, 0x01011121);
SET_IDREG(idregs, ID_ISAR6, 0x00000010);
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_mmfr4 = 0x00021110;
+ SET_IDREG(idregs, ID_MMFR0, 0x10201105);
+ SET_IDREG(idregs, ID_MMFR1, 0x40000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01260000);
+ SET_IDREG(idregs, ID_MMFR3, 0x02122211);
+ SET_IDREG(idregs, ID_MMFR4, 0x00021110);
SET_IDREG(idregs, ID_PFR0, 0x10010131);
SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */
SET_IDREG(idregs, ID_PFR2, 0x00000011);
@@ -617,11 +617,11 @@ static void aarch64_neoverse_n1_initfn(Object *obj)
SET_IDREG(idregs, ID_ISAR4, 0x00010142);
SET_IDREG(idregs, ID_ISAR5, 0x01011121);
SET_IDREG(idregs, ID_ISAR6, 0x00000010);
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_mmfr4 = 0x00021110;
+ SET_IDREG(idregs, ID_MMFR0, 0x10201105);
+ SET_IDREG(idregs, ID_MMFR1, 0x40000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01260000);
+ SET_IDREG(idregs, ID_MMFR3, 0x02122211);
+ SET_IDREG(idregs, ID_MMFR4, 0x00021110);
SET_IDREG(idregs, ID_PFR0, 0x10010131);
SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */
SET_IDREG(idregs, ID_PFR2, 0x00000011);
@@ -696,11 +696,11 @@ static void aarch64_neoverse_v1_initfn(Object *obj)
SET_IDREG(idregs, ID_ISAR4, 0x00010142);
SET_IDREG(idregs, ID_ISAR5, 0x11011121);
SET_IDREG(idregs, ID_ISAR6, 0x01100111);
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
- cpu->isar.id_mmfr4 = 0x01021110;
+ SET_IDREG(idregs, ID_MMFR0, 0x10201105);
+ SET_IDREG(idregs, ID_MMFR1, 0x40000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01260000);
+ SET_IDREG(idregs, ID_MMFR3, 0x02122211);
+ SET_IDREG(idregs, ID_MMFR4, 0x01021110);
SET_IDREG(idregs, ID_PFR0, 0x21110131);
SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */
SET_IDREG(idregs, ID_PFR2, 0x00000011);
@@ -906,17 +906,17 @@ static void aarch64_a710_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */
SET_IDREG(idregs, ID_DFR0, 0x16011099);
cpu->id_afr0 = 0;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
+ SET_IDREG(idregs, ID_MMFR0, 0x10201105);
+ SET_IDREG(idregs, ID_MMFR1, 0x40000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01260000);
+ SET_IDREG(idregs, ID_MMFR3, 0x02122211);
SET_IDREG(idregs, ID_ISAR0, 0x02101110);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232042);
SET_IDREG(idregs, ID_ISAR3, 0x01112131);
SET_IDREG(idregs, ID_ISAR4, 0x00010142);
SET_IDREG(idregs, ID_ISAR5, 0x11011121); /* with Crypto */
- cpu->isar.id_mmfr4 = 0x21021110;
+ SET_IDREG(idregs, ID_MMFR4, 0x21021110);
SET_IDREG(idregs, ID_ISAR6, 0x01111111);
cpu->isar.mvfr0 = 0x10110222;
cpu->isar.mvfr1 = 0x13211111;
@@ -1009,17 +1009,17 @@ static void aarch64_neoverse_n2_initfn(Object *obj)
SET_IDREG(idregs, ID_PFR1, 0x00010000); /* GIC filled in later */
SET_IDREG(idregs, ID_DFR0, 0x16011099);
cpu->id_afr0 = 0;
- cpu->isar.id_mmfr0 = 0x10201105;
- cpu->isar.id_mmfr1 = 0x40000000;
- cpu->isar.id_mmfr2 = 0x01260000;
- cpu->isar.id_mmfr3 = 0x02122211;
+ SET_IDREG(idregs, ID_MMFR0, 0x10201105);
+ SET_IDREG(idregs, ID_MMFR1, 0x40000000);
+ SET_IDREG(idregs, ID_MMFR2, 0x01260000);
+ SET_IDREG(idregs, ID_MMFR3, 0x02122211);
SET_IDREG(idregs, ID_ISAR0, 0x02101110);
SET_IDREG(idregs, ID_ISAR1, 0x13112111);
SET_IDREG(idregs, ID_ISAR2, 0x21232042);
SET_IDREG(idregs, ID_ISAR3, 0x01112131);
SET_IDREG(idregs, ID_ISAR4, 0x00010142);
SET_IDREG(idregs, ID_ISAR5, 0x11011121); /* with Crypto */
- cpu->isar.id_mmfr4 = 0x01021110;
+ SET_IDREG(idregs, ID_MMFR4, 0x01021110);
SET_IDREG(idregs, ID_ISAR6, 0x01111111);
cpu->isar.mvfr0 = 0x10110222;
cpu->isar.mvfr1 = 0x13211111;
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH 13/15] arm/cpu: Add infra to handle generated ID register definitions
2025-02-07 11:02 [PATCH 00/15] arm: rework id register storage Cornelia Huck
` (11 preceding siblings ...)
2025-02-07 11:02 ` [PATCH 12/15] arm/cpu: Store id_mmfr0-5 " Cornelia Huck
@ 2025-02-07 11:02 ` Cornelia Huck
2025-02-18 16:06 ` Eric Auger
2025-02-07 11:02 ` [PATCH 14/15] arm/cpu: Add sysreg generation scripts Cornelia Huck
2025-02-07 11:02 ` [PATCH 15/15] arm/cpu: Add generated files Cornelia Huck
14 siblings, 1 reply; 29+ messages in thread
From: Cornelia Huck @ 2025-02-07 11:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
The known ID regs are described in a new initialization function
dubbed initialize_cpu_sysreg_properties(). That code will be
automatically generated from linux arch/arm64/tools/sysreg. For the
time being let's just describe a single id reg, CTR_EL0. In this
description we only care about non RES/RAZ fields, ie. named fields.
The registers are populated in an array indexed by ARMIDRegisterIdx
and their fields are added in a sorted list.
[CH: adapted to reworked register storage]
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-custom.h | 55 ++++++++++++++++++++++++++++++
target/arm/cpu-sysreg-properties.c | 41 ++++++++++++++++++++++
target/arm/cpu64.c | 2 ++
target/arm/meson.build | 1 +
4 files changed, 99 insertions(+)
create mode 100644 target/arm/cpu-custom.h
create mode 100644 target/arm/cpu-sysreg-properties.c
diff --git a/target/arm/cpu-custom.h b/target/arm/cpu-custom.h
new file mode 100644
index 000000000000..17533765dacd
--- /dev/null
+++ b/target/arm/cpu-custom.h
@@ -0,0 +1,55 @@
+#ifndef ARM_CPU_CUSTOM_H
+#define ARM_CPU_CUSTOM_H
+
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "cpu.h"
+#include "cpu-sysregs.h"
+
+typedef struct ARM64SysRegField {
+ const char *name; /* name of the field, for instance CTR_EL0_IDC */
+ int index;
+ int lower;
+ int upper;
+} ARM64SysRegField;
+
+typedef struct ARM64SysReg {
+ const char *name; /* name of the sysreg, for instance CTR_EL0 */
+ ARMSysRegs sysreg;
+ int index;
+ GList *fields; /* list of named fields, excluding RES* */
+} ARM64SysReg;
+
+void initialize_cpu_sysreg_properties(void);
+
+/*
+ * List of exposed ID regs (automatically populated from linux
+ * arch/arm64/tools/sysreg)
+ */
+extern ARM64SysReg arm64_id_regs[NUM_ID_IDX];
+
+/* Allocate a new field and insert it at the head of the @reg list */
+static inline GList *arm64_sysreg_add_field(ARM64SysReg *reg, const char *name,
+ uint8_t min, uint8_t max) {
+
+ ARM64SysRegField *field = g_new0(ARM64SysRegField, 1);
+
+ field->name = name;
+ field->lower = min;
+ field->upper = max;
+ field->index = reg->index;
+
+ reg->fields = g_list_append(reg->fields, field);
+ return reg->fields;
+}
+
+static inline ARM64SysReg *arm64_sysreg_get(ARMIDRegisterIdx index)
+{
+ ARM64SysReg *reg = &arm64_id_regs[index];
+
+ reg->index = index;
+ reg->sysreg = id_register_sysreg[index];
+ return reg;
+}
+
+#endif
diff --git a/target/arm/cpu-sysreg-properties.c b/target/arm/cpu-sysreg-properties.c
new file mode 100644
index 000000000000..8b7ef5badfb9
--- /dev/null
+++ b/target/arm/cpu-sysreg-properties.c
@@ -0,0 +1,41 @@
+/*
+ * QEMU ARM CPU SYSREG PROPERTIES
+ * to be generated from linux sysreg
+ *
+ * Copyright (c) Red Hat, Inc. 2024
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#include "cpu-custom.h"
+
+ARM64SysReg arm64_id_regs[NUM_ID_IDX];
+
+void initialize_cpu_sysreg_properties(void)
+{
+ memset(arm64_id_regs, 0, sizeof(ARM64SysReg) * NUM_ID_IDX);
+ /* CTR_EL0 */
+ ARM64SysReg *CTR_EL0 = arm64_sysreg_get(CTR_EL0_IDX);
+ CTR_EL0->name = "CTR_EL0";
+ arm64_sysreg_add_field(CTR_EL0, "TminLine", 32, 37);
+ arm64_sysreg_add_field(CTR_EL0, "DIC", 29, 29);
+ arm64_sysreg_add_field(CTR_EL0, "IDC", 28, 28);
+ arm64_sysreg_add_field(CTR_EL0, "CWG", 24, 27);
+ arm64_sysreg_add_field(CTR_EL0, "ERG", 20, 23);
+ arm64_sysreg_add_field(CTR_EL0, "DminLine", 16, 19);
+ arm64_sysreg_add_field(CTR_EL0, "L1Ip", 14, 15);
+ arm64_sysreg_add_field(CTR_EL0, "IminLine", 0, 3);
+}
+
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index beba1733c99f..8371aabce5f4 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -35,6 +35,7 @@
#include "internals.h"
#include "cpu-features.h"
#include "cpregs.h"
+#include "cpu-custom.h"
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
{
@@ -894,6 +895,7 @@ static void aarch64_cpu_register_types(void)
{
size_t i;
+ initialize_cpu_sysreg_properties();
type_register_static(&aarch64_cpu_type_info);
for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
diff --git a/target/arm/meson.build b/target/arm/meson.build
index 2e10464dbb6b..9c7a04ee1b26 100644
--- a/target/arm/meson.build
+++ b/target/arm/meson.build
@@ -14,6 +14,7 @@ arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c'))
arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
'cpu64.c',
'gdbstub64.c',
+ 'cpu-sysreg-properties.c',
))
arm_system_ss = ss.source_set()
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 13/15] arm/cpu: Add infra to handle generated ID register definitions
2025-02-07 11:02 ` [PATCH 13/15] arm/cpu: Add infra to handle generated ID register definitions Cornelia Huck
@ 2025-02-18 16:06 ` Eric Auger
0 siblings, 0 replies; 29+ messages in thread
From: Eric Auger @ 2025-02-18 16:06 UTC (permalink / raw)
To: Cornelia Huck, eric.auger.pro, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini
Hi Connie,
On 2/7/25 12:02 PM, Cornelia Huck wrote:
> From: Eric Auger <eric.auger@redhat.com>
>
> The known ID regs are described in a new initialization function
> dubbed initialize_cpu_sysreg_properties(). That code will be
> automatically generated from linux arch/arm64/tools/sysreg. For the
> time being let's just describe a single id reg, CTR_EL0. In this
> description we only care about non RES/RAZ fields, ie. named fields.
>
> The registers are populated in an array indexed by ARMIDRegisterIdx
> and their fields are added in a sorted list.
I don't think we need all the infra related to properties in this
prerequisite series. I would postpone it until the main CPU model series.
You can just keep scripts/gen-cpu-sysregs-header.awk to generate the
sysreg definitions
>
> [CH: adapted to reworked register storage]
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
> ---
> target/arm/cpu-custom.h | 55 ++++++++++++++++++++++++++++++
> target/arm/cpu-sysreg-properties.c | 41 ++++++++++++++++++++++
> target/arm/cpu64.c | 2 ++
> target/arm/meson.build | 1 +
> 4 files changed, 99 insertions(+)
> create mode 100644 target/arm/cpu-custom.h
> create mode 100644 target/arm/cpu-sysreg-properties.c
>
> diff --git a/target/arm/cpu-custom.h b/target/arm/cpu-custom.h
by the custom we may get rid of the 'custom' terminology
> new file mode 100644
> index 000000000000..17533765dacd
> --- /dev/null
> +++ b/target/arm/cpu-custom.h
> @@ -0,0 +1,55 @@
> +#ifndef ARM_CPU_CUSTOM_H
> +#define ARM_CPU_CUSTOM_H
> +
> +#include "qemu/osdep.h"
> +#include "qemu/error-report.h"
> +#include "cpu.h"
> +#include "cpu-sysregs.h"
> +
> +typedef struct ARM64SysRegField {
> + const char *name; /* name of the field, for instance CTR_EL0_IDC */
> + int index;
> + int lower;
> + int upper;
> +} ARM64SysRegField;
> +
> +typedef struct ARM64SysReg {
> + const char *name; /* name of the sysreg, for instance CTR_EL0 */
> + ARMSysRegs sysreg;
> + int index;
> + GList *fields; /* list of named fields, excluding RES* */
> +} ARM64SysReg;
> +
> +void initialize_cpu_sysreg_properties(void);
> +
> +/*
> + * List of exposed ID regs (automatically populated from linux
> + * arch/arm64/tools/sysreg)
> + */
> +extern ARM64SysReg arm64_id_regs[NUM_ID_IDX];
> +
> +/* Allocate a new field and insert it at the head of the @reg list */
> +static inline GList *arm64_sysreg_add_field(ARM64SysReg *reg, const char *name,
> + uint8_t min, uint8_t max) {
> +
> + ARM64SysRegField *field = g_new0(ARM64SysRegField, 1);
> +
> + field->name = name;
> + field->lower = min;
> + field->upper = max;
> + field->index = reg->index;
> +
> + reg->fields = g_list_append(reg->fields, field);
> + return reg->fields;
> +}
> +
> +static inline ARM64SysReg *arm64_sysreg_get(ARMIDRegisterIdx index)
> +{
> + ARM64SysReg *reg = &arm64_id_regs[index];
> +
> + reg->index = index;
> + reg->sysreg = id_register_sysreg[index];
> + return reg;
> +}
> +
> +#endif
> diff --git a/target/arm/cpu-sysreg-properties.c b/target/arm/cpu-sysreg-properties.c
> new file mode 100644
> index 000000000000..8b7ef5badfb9
> --- /dev/null
> +++ b/target/arm/cpu-sysreg-properties.c
> @@ -0,0 +1,41 @@
> +/*
> + * QEMU ARM CPU SYSREG PROPERTIES
> + * to be generated from linux sysreg
> + *
> + * Copyright (c) Red Hat, Inc. 2024
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, see
> + * <http://www.gnu.org/licenses/gpl-2.0.html>
> + */
> +
> +#include "cpu-custom.h"
> +
> +ARM64SysReg arm64_id_regs[NUM_ID_IDX];
> +
> +void initialize_cpu_sysreg_properties(void)
> +{
> + memset(arm64_id_regs, 0, sizeof(ARM64SysReg) * NUM_ID_IDX);
> + /* CTR_EL0 */
> + ARM64SysReg *CTR_EL0 = arm64_sysreg_get(CTR_EL0_IDX);
> + CTR_EL0->name = "CTR_EL0";
> + arm64_sysreg_add_field(CTR_EL0, "TminLine", 32, 37);
> + arm64_sysreg_add_field(CTR_EL0, "DIC", 29, 29);
> + arm64_sysreg_add_field(CTR_EL0, "IDC", 28, 28);
> + arm64_sysreg_add_field(CTR_EL0, "CWG", 24, 27);
> + arm64_sysreg_add_field(CTR_EL0, "ERG", 20, 23);
> + arm64_sysreg_add_field(CTR_EL0, "DminLine", 16, 19);
> + arm64_sysreg_add_field(CTR_EL0, "L1Ip", 14, 15);
> + arm64_sysreg_add_field(CTR_EL0, "IminLine", 0, 3);
> +}
> +
> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
> index beba1733c99f..8371aabce5f4 100644
> --- a/target/arm/cpu64.c
> +++ b/target/arm/cpu64.c
> @@ -35,6 +35,7 @@
> #include "internals.h"
> #include "cpu-features.h"
> #include "cpregs.h"
> +#include "cpu-custom.h"
>
> void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
> {
> @@ -894,6 +895,7 @@ static void aarch64_cpu_register_types(void)
> {
> size_t i;
>
> + initialize_cpu_sysreg_properties();
> type_register_static(&aarch64_cpu_type_info);
>
> for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
> diff --git a/target/arm/meson.build b/target/arm/meson.build
> index 2e10464dbb6b..9c7a04ee1b26 100644
> --- a/target/arm/meson.build
> +++ b/target/arm/meson.build
> @@ -14,6 +14,7 @@ arm_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c'))
> arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
> 'cpu64.c',
> 'gdbstub64.c',
> + 'cpu-sysreg-properties.c',
> ))
>
> arm_system_ss = ss.source_set()
Thanks
Eric
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 14/15] arm/cpu: Add sysreg generation scripts
2025-02-07 11:02 [PATCH 00/15] arm: rework id register storage Cornelia Huck
` (12 preceding siblings ...)
2025-02-07 11:02 ` [PATCH 13/15] arm/cpu: Add infra to handle generated ID register definitions Cornelia Huck
@ 2025-02-07 11:02 ` Cornelia Huck
2025-02-07 14:14 ` Marc Zyngier
2025-02-07 11:02 ` [PATCH 15/15] arm/cpu: Add generated files Cornelia Huck
14 siblings, 1 reply; 29+ messages in thread
From: Cornelia Huck @ 2025-02-07 11:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
From: Eric Auger <eric.auger@redhat.com>
Introduce scripts that automate the generation of system register
definitions from a given linux source tree arch/arm64/tools/sysreg.
Invocation of
./update-aarch64-sysreg-code.sh $PATH_TO_LINUX_SOURCE_TREE
in scripts directory do generate 2 qemu files:
- target/arm/cpu-sysreg-properties.c
- target/arm/cpu-sysregs.h.inc
cpu-sysregs.h.inc creates defines for all system registers.
However cpu-sysreg-properties.c only cares about feature ID registers.
update-aarch64-sysreg-code.sh calls two awk scripts.
gen-cpu-sysreg-properties.awk is inherited from kernel
arch/arm64/tools/gen-sysreg.awk. All credits to Mark Rutland
the original author of this script.
[CH: update to handle current kernel sysregs structure, and to emit
the re-worked register structures]
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
scripts/gen-cpu-sysreg-properties.awk | 325 ++++++++++++++++++++++++++
| 70 ++++++
scripts/update-aarch64-sysreg-code.sh | 30 +++
3 files changed, 425 insertions(+)
create mode 100755 scripts/gen-cpu-sysreg-properties.awk
create mode 100755 scripts/gen-cpu-sysregs-header.awk
create mode 100755 scripts/update-aarch64-sysreg-code.sh
diff --git a/scripts/gen-cpu-sysreg-properties.awk b/scripts/gen-cpu-sysreg-properties.awk
new file mode 100755
index 000000000000..76c37938b168
--- /dev/null
+++ b/scripts/gen-cpu-sysreg-properties.awk
@@ -0,0 +1,325 @@
+#!/bin/awk -f
+# SPDX-License-Identifier: GPL-2.0
+# gen-cpu-sysreg-properties.awk: arm64 sysreg header generator
+#
+# Usage: awk -f gen-cpu-sysreg-properties.awk $LINUX_PATH/arch/arm64/tools/sysreg
+
+function block_current() {
+ return __current_block[__current_block_depth];
+}
+
+# Log an error and terminate
+function fatal(msg) {
+ print "Error at " NR ": " msg > "/dev/stderr"
+
+ printf "Current block nesting:"
+
+ for (i = 0; i <= __current_block_depth; i++) {
+ printf " " __current_block[i]
+ }
+ printf "\n"
+
+ exit 1
+}
+
+# Enter a new block, setting the active block to @block
+function block_push(block) {
+ __current_block[++__current_block_depth] = block
+}
+
+# Exit a block, setting the active block to the parent block
+function block_pop() {
+ if (__current_block_depth == 0)
+ fatal("error: block_pop() in root block")
+
+ __current_block_depth--;
+}
+
+# Sanity check the number of records for a field makes sense. If not, produce
+# an error and terminate.
+function expect_fields(nf) {
+ if (NF != nf)
+ fatal(NF " fields found where " nf " expected")
+}
+
+# Print a CPP macro definition, padded with spaces so that the macro bodies
+# line up in a column
+function define(name, val) {
+ printf "%-56s%s\n", "#define " name, val
+}
+
+# Print standard BITMASK/SHIFT/WIDTH CPP definitions for a field
+function define_field(reg, field, msb, lsb, idreg) {
+ if (idreg)
+ print " arm64_sysreg_add_field("reg", \""field"\", "lsb", "msb");"
+}
+
+# Print a field _SIGNED definition for a field
+function define_field_sign(reg, field, sign, idreg) {
+ if (idreg)
+ print " arm64_sysreg_add_field("reg", \""field"\", "lsb", "msb");"
+}
+
+# Parse a "<msb>[:<lsb>]" string into the global variables @msb and @lsb
+function parse_bitdef(reg, field, bitdef, _bits)
+{
+ if (bitdef ~ /^[0-9]+$/) {
+ msb = bitdef
+ lsb = bitdef
+ } else if (split(bitdef, _bits, ":") == 2) {
+ msb = _bits[1]
+ lsb = _bits[2]
+ } else {
+ fatal("invalid bit-range definition '" bitdef "'")
+ }
+
+
+ if (msb != next_bit)
+ fatal(reg "." field " starts at " msb " not " next_bit)
+ if (63 < msb || msb < 0)
+ fatal(reg "." field " invalid high bit in '" bitdef "'")
+ if (63 < lsb || lsb < 0)
+ fatal(reg "." field " invalid low bit in '" bitdef "'")
+ if (msb < lsb)
+ fatal(reg "." field " invalid bit-range '" bitdef "'")
+ if (low > high)
+ fatal(reg "." field " has invalid range " high "-" low)
+
+ next_bit = lsb - 1
+}
+
+BEGIN {
+ print "#include \"cpu-custom.h\""
+ print ""
+ print "ARM64SysReg arm64_id_regs[NUM_ID_IDX];"
+ print ""
+ print "void initialize_cpu_sysreg_properties(void)"
+ print "{"
+ print " memset(arm64_id_regs, 0, sizeof(ARM64SysReg) * NUM_ID_IDX);"
+ print ""
+
+ __current_block_depth = 0
+ __current_block[__current_block_depth] = "Root"
+}
+
+END {
+ if (__current_block_depth != 0)
+ fatal("Missing terminator for " block_current() " block")
+
+ print "}"
+}
+
+# skip blank lines and comment lines
+/^$/ { next }
+/^[\t ]*#/ { next }
+
+/^SysregFields/ && block_current() == "Root" {
+ block_push("SysregFields")
+
+ expect_fields(2)
+
+ reg = $2
+
+ res0 = "UL(0)"
+ res1 = "UL(0)"
+ unkn = "UL(0)"
+
+ next_bit = 63
+
+ next
+}
+
+/^EndSysregFields/ && block_current() == "SysregFields" {
+ if (next_bit > 0)
+ fatal("Unspecified bits in " reg)
+
+ reg = null
+ res0 = null
+ res1 = null
+ unkn = null
+
+ block_pop()
+ next
+}
+
+/^Sysreg/ && block_current() == "Root" {
+ block_push("Sysreg")
+
+ expect_fields(7)
+
+ reg = $2
+ op0 = $3
+ op1 = $4
+ crn = $5
+ crm = $6
+ op2 = $7
+
+ res0 = "UL(0)"
+ res1 = "UL(0)"
+ unkn = "UL(0)"
+
+ if (op0 == 3 && (op1>=0 && op1<=3) && crn==0 && (crm>=0 && crm<=7) && (op2>=0 && op2<=7)) {
+ idreg = 1
+ } else {
+ idreg = 0
+ }
+
+ if (idreg == 1) {
+ print " /* "reg" */"
+ print " ARM64SysReg *"reg" = arm64_sysreg_get("reg"_IDX);"
+ print " "reg"->name = \""reg"\";"
+ }
+
+ next_bit = 63
+
+ next
+}
+
+/^EndSysreg/ && block_current() == "Sysreg" {
+ if (next_bit > 0)
+ fatal("Unspecified bits in " reg)
+
+ reg = null
+ op0 = null
+ op1 = null
+ crn = null
+ crm = null
+ op2 = null
+ res0 = null
+ res1 = null
+ unkn = null
+
+ if (idreg==1)
+ print ""
+ block_pop()
+ next
+}
+
+# Currently this is effectivey a comment, in future we may want to emit
+# defines for the fields.
+(/^Fields/ || /^Mapping/) && block_current() == "Sysreg" {
+ expect_fields(2)
+
+ if (next_bit != 63)
+ fatal("Some fields already defined for " reg)
+
+ print "/* For " reg " fields see " $2 " */"
+ print ""
+
+ next_bit = 0
+ res0 = null
+ res1 = null
+ unkn = null
+
+ next
+}
+
+
+/^Res0/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
+ expect_fields(2)
+ parse_bitdef(reg, "RES0", $2)
+ field = "RES0_" msb "_" lsb
+
+ res0 = res0 " | GENMASK_ULL(" msb ", " lsb ")"
+
+ next
+}
+
+/^Res1/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
+ expect_fields(2)
+ parse_bitdef(reg, "RES1", $2)
+ field = "RES1_" msb "_" lsb
+
+ res1 = res1 " | GENMASK_ULL(" msb ", " lsb ")"
+
+ next
+}
+
+/^Unkn/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
+ expect_fields(2)
+ parse_bitdef(reg, "UNKN", $2)
+ field = "UNKN_" msb "_" lsb
+
+ unkn = unkn " | GENMASK_ULL(" msb ", " lsb ")"
+
+ next
+}
+
+/^Field/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
+ expect_fields(3)
+ field = $3
+ parse_bitdef(reg, field, $2)
+
+
+ define_field(reg, field, msb, lsb, idreg)
+
+ next
+}
+
+/^Raz/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
+ expect_fields(2)
+ parse_bitdef(reg, field, $2)
+
+ next
+}
+
+/^SignedEnum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
+ block_push("Enum")
+
+ expect_fields(3)
+ field = $3
+ parse_bitdef(reg, field, $2)
+
+ define_field(reg, field, msb, lsb, idreg)
+ define_field_sign(reg, field, "true", idreg)
+
+ next
+}
+
+/^UnsignedEnum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
+ block_push("Enum")
+
+ expect_fields(3)
+ field = $3
+ parse_bitdef(reg, field, $2)
+
+ define_field(reg, field, msb, lsb, idreg)
+ #define_field_sign(reg, field, "false", idreg)
+
+ next
+}
+
+/^Enum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
+ block_push("Enum")
+
+ expect_fields(3)
+ field = $3
+ parse_bitdef(reg, field, $2)
+
+ define_field(reg, field, msb, lsb, idreg)
+
+ next
+}
+
+/^EndEnum/ && block_current() == "Enum" {
+
+ field = null
+ msb = null
+ lsb = null
+
+ block_pop()
+ next
+}
+
+/0b[01]+/ && block_current() == "Enum" {
+ expect_fields(2)
+ val = $1
+ name = $2
+
+ next
+}
+
+# Any lines not handled by previous rules are unexpected
+{
+ fatal("unhandled statement")
+}
--git a/scripts/gen-cpu-sysregs-header.awk b/scripts/gen-cpu-sysregs-header.awk
new file mode 100755
index 000000000000..27a222856a84
--- /dev/null
+++ b/scripts/gen-cpu-sysregs-header.awk
@@ -0,0 +1,70 @@
+#!/bin/awk -f
+# SPDX-License-Identifier: GPL-2.0
+# gen-cpu-sysregs-header.awk: arm64 sysreg header generator
+#
+# Usage: awk -f gen-cpu-sysregs-header.awk -- -v structure=xxx $LINUX_PATH/arch/arm64/tools/sysreg
+# where structure is one of "idx" "reg" "table"
+
+BEGIN {
+ print ""
+ if (structure == "idx") {
+ print "typedef enum ARMIDRegisterIdx {"
+ }
+ if (structure == "reg") {
+ print "typedef enum ARMSysRegs {"
+ }
+ if (structure == "table") {
+ print "static const uint32_t id_register_sysreg[NUM_ID_IDX] = {"
+ }
+} END {
+ if (structure == "idx") {
+ print " NUM_ID_IDX,"
+ print "} ARMIDRegisterIdx;"
+ }
+ if (structure == "reg") {
+ print "} ARMSysRegs;"
+ }
+ if (structure == "table") {
+ print "};"
+ }
+ print ""
+}
+
+# skip blank lines and comment lines
+/^$/ { next }
+/^[\t ]*#/ { next }
+
+/^Sysreg\t/ || /^Sysreg /{
+
+ reg = $2
+ op0 = $3
+ op1 = $4
+ crn = $5
+ crm = $6
+ op2 = $7
+
+ if (op0 == 3 && (op1>=0 && op1<=3) && crn==0 && (crm>=0 && crm<=7) && (op2>=0 && op2<=7)) {
+ idreg = 1
+ } else {
+ idreg = 0
+ }
+
+ if (idreg) {
+ if (structure == "idx") {
+ print " "reg"_IDX,"
+ }
+ if (structure == "reg") {
+ print " SYS_"reg" = ENCODE_ID_REG("op0", "op1", "crn", "crm", "op2"),"
+ }
+ if (structure == "table") {
+ print " ["reg"_IDX] = SYS_"reg","
+ }
+ }
+
+ next
+}
+
+{
+ /* skip all other lines */
+ next
+}
diff --git a/scripts/update-aarch64-sysreg-code.sh b/scripts/update-aarch64-sysreg-code.sh
new file mode 100755
index 000000000000..b8169dc984d2
--- /dev/null
+++ b/scripts/update-aarch64-sysreg-code.sh
@@ -0,0 +1,30 @@
+#!/bin/sh -e
+#
+# Update target/arm/cpu-sysreg-properties.c and target/arm/cpu-sysregs.h
+# from a linux source tree (arch/arm64/tools/sysreg)
+#
+# Copyright Red Hat, Inc. 2024
+#
+# Authors:
+# Eric Auger <eric.auger@redhat.com>
+#
+
+linux="$1"
+output="$PWD"
+
+if [ -z "$linux" ] || ! [ -d "$linux" ]; then
+ cat << EOF
+usage: update-aarch64-sysreg-code.sh LINUX_PATH
+
+LINUX_PATH Linux kernel directory to obtain the headers from
+EOF
+ exit 1
+fi
+
+echo "/* GENERATED FILE -- DO NOT EDIT */" > ../target/arm/cpu-sysregs.h.inc
+for structure in "idx" "reg" "table"; do
+ awk -f gen-cpu-sysregs-header.awk -v structure="$structure"\
+ $linux/arch/arm64/tools/sysreg >> ../target/arm/cpu-sysregs.h.inc
+done
+awk -f gen-cpu-sysreg-properties.awk \
+ $linux/arch/arm64/tools/sysreg > ../target/arm/cpu-sysreg-properties.c
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 14/15] arm/cpu: Add sysreg generation scripts
2025-02-07 11:02 ` [PATCH 14/15] arm/cpu: Add sysreg generation scripts Cornelia Huck
@ 2025-02-07 14:14 ` Marc Zyngier
0 siblings, 0 replies; 29+ messages in thread
From: Marc Zyngier @ 2025-02-07 14:14 UTC (permalink / raw)
To: Cornelia Huck
Cc: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar, shahuang, mark.rutland, philmd, pbonzini
On Fri, 07 Feb 2025 11:02:47 +0000,
Cornelia Huck <cohuck@redhat.com> wrote:
>
> From: Eric Auger <eric.auger@redhat.com>
>
> Introduce scripts that automate the generation of system register
> definitions from a given linux source tree arch/arm64/tools/sysreg.
>
> Invocation of
> ./update-aarch64-sysreg-code.sh $PATH_TO_LINUX_SOURCE_TREE
> in scripts directory do generate 2 qemu files:
> - target/arm/cpu-sysreg-properties.c
> - target/arm/cpu-sysregs.h.inc
>
> cpu-sysregs.h.inc creates defines for all system registers.
> However cpu-sysreg-properties.c only cares about feature ID registers.
>
> update-aarch64-sysreg-code.sh calls two awk scripts.
> gen-cpu-sysreg-properties.awk is inherited from kernel
> arch/arm64/tools/gen-sysreg.awk. All credits to Mark Rutland
> the original author of this script.
>
> [CH: update to handle current kernel sysregs structure, and to emit
> the re-worked register structures]
> Signed-off-by: Eric Auger <eric.auger@redhat.com>
> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
> ---
> scripts/gen-cpu-sysreg-properties.awk | 325 ++++++++++++++++++++++++++
> scripts/gen-cpu-sysregs-header.awk | 70 ++++++
> scripts/update-aarch64-sysreg-code.sh | 30 +++
> 3 files changed, 425 insertions(+)
> create mode 100755 scripts/gen-cpu-sysreg-properties.awk
> create mode 100755 scripts/gen-cpu-sysregs-header.awk
> create mode 100755 scripts/update-aarch64-sysreg-code.sh
Shameless plug:
https://lore.kernel.org/r/20250102144339.1564778-1-maz@kernel.org
You could use (something like) this to generate the sysreg file itself
from the architecture data, or another representation as required.
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH 15/15] arm/cpu: Add generated files
2025-02-07 11:02 [PATCH 00/15] arm: rework id register storage Cornelia Huck
` (13 preceding siblings ...)
2025-02-07 11:02 ` [PATCH 14/15] arm/cpu: Add sysreg generation scripts Cornelia Huck
@ 2025-02-07 11:02 ` Cornelia Huck
2025-02-07 19:02 ` Richard Henderson
14 siblings, 1 reply; 29+ messages in thread
From: Cornelia Huck @ 2025-02-07 11:02 UTC (permalink / raw)
To: eric.auger.pro, eric.auger, qemu-devel, qemu-arm, kvmarm,
peter.maydell, richard.henderson, alex.bennee, maz, oliver.upton,
sebott, shameerali.kolothum.thodi, armbru, berrange, abologna,
jdenemar
Cc: shahuang, mark.rutland, philmd, pbonzini, Cornelia Huck
And switch to using the generated definitions.
Generated against Linux 6.14-rc1.
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
target/arm/cpu-sysreg-properties.c | 716 ++++++++++++++++++++++++++++-
target/arm/cpu-sysregs.h | 116 +----
target/arm/cpu-sysregs.h.inc | 164 +++++++
3 files changed, 860 insertions(+), 136 deletions(-)
create mode 100644 target/arm/cpu-sysregs.h.inc
diff --git a/target/arm/cpu-sysreg-properties.c b/target/arm/cpu-sysreg-properties.c
index 8b7ef5badfb9..05eb40487313 100644
--- a/target/arm/cpu-sysreg-properties.c
+++ b/target/arm/cpu-sysreg-properties.c
@@ -1,24 +1,3 @@
-/*
- * QEMU ARM CPU SYSREG PROPERTIES
- * to be generated from linux sysreg
- *
- * Copyright (c) Red Hat, Inc. 2024
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see
- * <http://www.gnu.org/licenses/gpl-2.0.html>
- */
-
#include "cpu-custom.h"
ARM64SysReg arm64_id_regs[NUM_ID_IDX];
@@ -26,6 +5,627 @@ ARM64SysReg arm64_id_regs[NUM_ID_IDX];
void initialize_cpu_sysreg_properties(void)
{
memset(arm64_id_regs, 0, sizeof(ARM64SysReg) * NUM_ID_IDX);
+
+ /* ID_PFR0_EL1 */
+ ARM64SysReg *ID_PFR0_EL1 = arm64_sysreg_get(ID_PFR0_EL1_IDX);
+ ID_PFR0_EL1->name = "ID_PFR0_EL1";
+ arm64_sysreg_add_field(ID_PFR0_EL1, "RAS", 28, 31);
+ arm64_sysreg_add_field(ID_PFR0_EL1, "DIT", 24, 27);
+ arm64_sysreg_add_field(ID_PFR0_EL1, "AMU", 20, 23);
+ arm64_sysreg_add_field(ID_PFR0_EL1, "CSV2", 16, 19);
+ arm64_sysreg_add_field(ID_PFR0_EL1, "State3", 12, 15);
+ arm64_sysreg_add_field(ID_PFR0_EL1, "State2", 8, 11);
+ arm64_sysreg_add_field(ID_PFR0_EL1, "State1", 4, 7);
+ arm64_sysreg_add_field(ID_PFR0_EL1, "State0", 0, 3);
+
+ /* ID_PFR1_EL1 */
+ ARM64SysReg *ID_PFR1_EL1 = arm64_sysreg_get(ID_PFR1_EL1_IDX);
+ ID_PFR1_EL1->name = "ID_PFR1_EL1";
+ arm64_sysreg_add_field(ID_PFR1_EL1, "GIC", 28, 31);
+ arm64_sysreg_add_field(ID_PFR1_EL1, "Virt_frac", 24, 27);
+ arm64_sysreg_add_field(ID_PFR1_EL1, "Sec_frac", 20, 23);
+ arm64_sysreg_add_field(ID_PFR1_EL1, "GenTimer", 16, 19);
+ arm64_sysreg_add_field(ID_PFR1_EL1, "Virtualization", 12, 15);
+ arm64_sysreg_add_field(ID_PFR1_EL1, "MProgMod", 8, 11);
+ arm64_sysreg_add_field(ID_PFR1_EL1, "Security", 4, 7);
+ arm64_sysreg_add_field(ID_PFR1_EL1, "ProgMod", 0, 3);
+
+ /* ID_DFR0_EL1 */
+ ARM64SysReg *ID_DFR0_EL1 = arm64_sysreg_get(ID_DFR0_EL1_IDX);
+ ID_DFR0_EL1->name = "ID_DFR0_EL1";
+ arm64_sysreg_add_field(ID_DFR0_EL1, "TraceFilt", 28, 31);
+ arm64_sysreg_add_field(ID_DFR0_EL1, "PerfMon", 24, 27);
+ arm64_sysreg_add_field(ID_DFR0_EL1, "MProfDbg", 20, 23);
+ arm64_sysreg_add_field(ID_DFR0_EL1, "MMapTrc", 16, 19);
+ arm64_sysreg_add_field(ID_DFR0_EL1, "CopTrc", 12, 15);
+ arm64_sysreg_add_field(ID_DFR0_EL1, "MMapDbg", 8, 11);
+ arm64_sysreg_add_field(ID_DFR0_EL1, "CopSDbg", 4, 7);
+ arm64_sysreg_add_field(ID_DFR0_EL1, "CopDbg", 0, 3);
+
+ /* ID_AFR0_EL1 */
+ ARM64SysReg *ID_AFR0_EL1 = arm64_sysreg_get(ID_AFR0_EL1_IDX);
+ ID_AFR0_EL1->name = "ID_AFR0_EL1";
+ arm64_sysreg_add_field(ID_AFR0_EL1, "IMPDEF3", 12, 15);
+ arm64_sysreg_add_field(ID_AFR0_EL1, "IMPDEF2", 8, 11);
+ arm64_sysreg_add_field(ID_AFR0_EL1, "IMPDEF1", 4, 7);
+ arm64_sysreg_add_field(ID_AFR0_EL1, "IMPDEF0", 0, 3);
+
+ /* ID_MMFR0_EL1 */
+ ARM64SysReg *ID_MMFR0_EL1 = arm64_sysreg_get(ID_MMFR0_EL1_IDX);
+ ID_MMFR0_EL1->name = "ID_MMFR0_EL1";
+ arm64_sysreg_add_field(ID_MMFR0_EL1, "InnerShr", 28, 31);
+ arm64_sysreg_add_field(ID_MMFR0_EL1, "FCSE", 24, 27);
+ arm64_sysreg_add_field(ID_MMFR0_EL1, "AuxReg", 20, 23);
+ arm64_sysreg_add_field(ID_MMFR0_EL1, "TCM", 16, 19);
+ arm64_sysreg_add_field(ID_MMFR0_EL1, "ShareLvl", 12, 15);
+ arm64_sysreg_add_field(ID_MMFR0_EL1, "OuterShr", 8, 11);
+ arm64_sysreg_add_field(ID_MMFR0_EL1, "PMSA", 4, 7);
+ arm64_sysreg_add_field(ID_MMFR0_EL1, "VMSA", 0, 3);
+
+ /* ID_MMFR1_EL1 */
+ ARM64SysReg *ID_MMFR1_EL1 = arm64_sysreg_get(ID_MMFR1_EL1_IDX);
+ ID_MMFR1_EL1->name = "ID_MMFR1_EL1";
+ arm64_sysreg_add_field(ID_MMFR1_EL1, "BPred", 28, 31);
+ arm64_sysreg_add_field(ID_MMFR1_EL1, "L1TstCln", 24, 27);
+ arm64_sysreg_add_field(ID_MMFR1_EL1, "L1Uni", 20, 23);
+ arm64_sysreg_add_field(ID_MMFR1_EL1, "L1Hvd", 16, 19);
+ arm64_sysreg_add_field(ID_MMFR1_EL1, "L1UniSW", 12, 15);
+ arm64_sysreg_add_field(ID_MMFR1_EL1, "L1HvdSW", 8, 11);
+ arm64_sysreg_add_field(ID_MMFR1_EL1, "L1UniVA", 4, 7);
+ arm64_sysreg_add_field(ID_MMFR1_EL1, "L1HvdVA", 0, 3);
+
+ /* ID_MMFR2_EL1 */
+ ARM64SysReg *ID_MMFR2_EL1 = arm64_sysreg_get(ID_MMFR2_EL1_IDX);
+ ID_MMFR2_EL1->name = "ID_MMFR2_EL1";
+ arm64_sysreg_add_field(ID_MMFR2_EL1, "HWAccFlg", 28, 31);
+ arm64_sysreg_add_field(ID_MMFR2_EL1, "WFIStall", 24, 27);
+ arm64_sysreg_add_field(ID_MMFR2_EL1, "MemBarr", 20, 23);
+ arm64_sysreg_add_field(ID_MMFR2_EL1, "UniTLB", 16, 19);
+ arm64_sysreg_add_field(ID_MMFR2_EL1, "HvdTLB", 12, 15);
+ arm64_sysreg_add_field(ID_MMFR2_EL1, "L1HvdRng", 8, 11);
+ arm64_sysreg_add_field(ID_MMFR2_EL1, "L1HvdBG", 4, 7);
+ arm64_sysreg_add_field(ID_MMFR2_EL1, "L1HvdFG", 0, 3);
+
+ /* ID_MMFR3_EL1 */
+ ARM64SysReg *ID_MMFR3_EL1 = arm64_sysreg_get(ID_MMFR3_EL1_IDX);
+ ID_MMFR3_EL1->name = "ID_MMFR3_EL1";
+ arm64_sysreg_add_field(ID_MMFR3_EL1, "Supersec", 28, 31);
+ arm64_sysreg_add_field(ID_MMFR3_EL1, "CMemSz", 24, 27);
+ arm64_sysreg_add_field(ID_MMFR3_EL1, "CohWalk", 20, 23);
+ arm64_sysreg_add_field(ID_MMFR3_EL1, "PAN", 16, 19);
+ arm64_sysreg_add_field(ID_MMFR3_EL1, "MaintBcst", 12, 15);
+ arm64_sysreg_add_field(ID_MMFR3_EL1, "BPMaint", 8, 11);
+ arm64_sysreg_add_field(ID_MMFR3_EL1, "CMaintSW", 4, 7);
+ arm64_sysreg_add_field(ID_MMFR3_EL1, "CMaintVA", 0, 3);
+
+ /* ID_ISAR0_EL1 */
+ ARM64SysReg *ID_ISAR0_EL1 = arm64_sysreg_get(ID_ISAR0_EL1_IDX);
+ ID_ISAR0_EL1->name = "ID_ISAR0_EL1";
+ arm64_sysreg_add_field(ID_ISAR0_EL1, "Divide", 24, 27);
+ arm64_sysreg_add_field(ID_ISAR0_EL1, "Debug", 20, 23);
+ arm64_sysreg_add_field(ID_ISAR0_EL1, "Coproc", 16, 19);
+ arm64_sysreg_add_field(ID_ISAR0_EL1, "CmpBranch", 12, 15);
+ arm64_sysreg_add_field(ID_ISAR0_EL1, "BitField", 8, 11);
+ arm64_sysreg_add_field(ID_ISAR0_EL1, "BitCount", 4, 7);
+ arm64_sysreg_add_field(ID_ISAR0_EL1, "Swap", 0, 3);
+
+ /* ID_ISAR1_EL1 */
+ ARM64SysReg *ID_ISAR1_EL1 = arm64_sysreg_get(ID_ISAR1_EL1_IDX);
+ ID_ISAR1_EL1->name = "ID_ISAR1_EL1";
+ arm64_sysreg_add_field(ID_ISAR1_EL1, "Jazelle", 28, 31);
+ arm64_sysreg_add_field(ID_ISAR1_EL1, "Interwork", 24, 27);
+ arm64_sysreg_add_field(ID_ISAR1_EL1, "Immediate", 20, 23);
+ arm64_sysreg_add_field(ID_ISAR1_EL1, "IfThen", 16, 19);
+ arm64_sysreg_add_field(ID_ISAR1_EL1, "Extend", 12, 15);
+ arm64_sysreg_add_field(ID_ISAR1_EL1, "Except_AR", 8, 11);
+ arm64_sysreg_add_field(ID_ISAR1_EL1, "Except", 4, 7);
+ arm64_sysreg_add_field(ID_ISAR1_EL1, "Endian", 0, 3);
+
+ /* ID_ISAR2_EL1 */
+ ARM64SysReg *ID_ISAR2_EL1 = arm64_sysreg_get(ID_ISAR2_EL1_IDX);
+ ID_ISAR2_EL1->name = "ID_ISAR2_EL1";
+ arm64_sysreg_add_field(ID_ISAR2_EL1, "Reversal", 28, 31);
+ arm64_sysreg_add_field(ID_ISAR2_EL1, "PSR_AR", 24, 27);
+ arm64_sysreg_add_field(ID_ISAR2_EL1, "MultU", 20, 23);
+ arm64_sysreg_add_field(ID_ISAR2_EL1, "MultS", 16, 19);
+ arm64_sysreg_add_field(ID_ISAR2_EL1, "Mult", 12, 15);
+ arm64_sysreg_add_field(ID_ISAR2_EL1, "MultiAccessInt", 8, 11);
+ arm64_sysreg_add_field(ID_ISAR2_EL1, "MemHint", 4, 7);
+ arm64_sysreg_add_field(ID_ISAR2_EL1, "LoadStore", 0, 3);
+
+ /* ID_ISAR3_EL1 */
+ ARM64SysReg *ID_ISAR3_EL1 = arm64_sysreg_get(ID_ISAR3_EL1_IDX);
+ ID_ISAR3_EL1->name = "ID_ISAR3_EL1";
+ arm64_sysreg_add_field(ID_ISAR3_EL1, "T32EE", 28, 31);
+ arm64_sysreg_add_field(ID_ISAR3_EL1, "TrueNOP", 24, 27);
+ arm64_sysreg_add_field(ID_ISAR3_EL1, "T32Copy", 20, 23);
+ arm64_sysreg_add_field(ID_ISAR3_EL1, "TabBranch", 16, 19);
+ arm64_sysreg_add_field(ID_ISAR3_EL1, "SynchPrim", 12, 15);
+ arm64_sysreg_add_field(ID_ISAR3_EL1, "SVC", 8, 11);
+ arm64_sysreg_add_field(ID_ISAR3_EL1, "SIMD", 4, 7);
+ arm64_sysreg_add_field(ID_ISAR3_EL1, "Saturate", 0, 3);
+
+ /* ID_ISAR4_EL1 */
+ ARM64SysReg *ID_ISAR4_EL1 = arm64_sysreg_get(ID_ISAR4_EL1_IDX);
+ ID_ISAR4_EL1->name = "ID_ISAR4_EL1";
+ arm64_sysreg_add_field(ID_ISAR4_EL1, "SWP_frac", 28, 31);
+ arm64_sysreg_add_field(ID_ISAR4_EL1, "PSR_M", 24, 27);
+ arm64_sysreg_add_field(ID_ISAR4_EL1, "SynchPrim_frac", 20, 23);
+ arm64_sysreg_add_field(ID_ISAR4_EL1, "Barrier", 16, 19);
+ arm64_sysreg_add_field(ID_ISAR4_EL1, "SMC", 12, 15);
+ arm64_sysreg_add_field(ID_ISAR4_EL1, "Writeback", 8, 11);
+ arm64_sysreg_add_field(ID_ISAR4_EL1, "WithShifts", 4, 7);
+ arm64_sysreg_add_field(ID_ISAR4_EL1, "Unpriv", 0, 3);
+
+ /* ID_ISAR5_EL1 */
+ ARM64SysReg *ID_ISAR5_EL1 = arm64_sysreg_get(ID_ISAR5_EL1_IDX);
+ ID_ISAR5_EL1->name = "ID_ISAR5_EL1";
+ arm64_sysreg_add_field(ID_ISAR5_EL1, "VCMA", 28, 31);
+ arm64_sysreg_add_field(ID_ISAR5_EL1, "RDM", 24, 27);
+ arm64_sysreg_add_field(ID_ISAR5_EL1, "CRC32", 16, 19);
+ arm64_sysreg_add_field(ID_ISAR5_EL1, "SHA2", 12, 15);
+ arm64_sysreg_add_field(ID_ISAR5_EL1, "SHA1", 8, 11);
+ arm64_sysreg_add_field(ID_ISAR5_EL1, "AES", 4, 7);
+ arm64_sysreg_add_field(ID_ISAR5_EL1, "SEVL", 0, 3);
+
+ /* ID_ISAR6_EL1 */
+ ARM64SysReg *ID_ISAR6_EL1 = arm64_sysreg_get(ID_ISAR6_EL1_IDX);
+ ID_ISAR6_EL1->name = "ID_ISAR6_EL1";
+ arm64_sysreg_add_field(ID_ISAR6_EL1, "I8MM", 24, 27);
+ arm64_sysreg_add_field(ID_ISAR6_EL1, "BF16", 20, 23);
+ arm64_sysreg_add_field(ID_ISAR6_EL1, "SPECRES", 16, 19);
+ arm64_sysreg_add_field(ID_ISAR6_EL1, "SB", 12, 15);
+ arm64_sysreg_add_field(ID_ISAR6_EL1, "FHM", 8, 11);
+ arm64_sysreg_add_field(ID_ISAR6_EL1, "DP", 4, 7);
+ arm64_sysreg_add_field(ID_ISAR6_EL1, "JSCVT", 0, 3);
+
+ /* ID_MMFR4_EL1 */
+ ARM64SysReg *ID_MMFR4_EL1 = arm64_sysreg_get(ID_MMFR4_EL1_IDX);
+ ID_MMFR4_EL1->name = "ID_MMFR4_EL1";
+ arm64_sysreg_add_field(ID_MMFR4_EL1, "EVT", 28, 31);
+ arm64_sysreg_add_field(ID_MMFR4_EL1, "CCIDX", 24, 27);
+ arm64_sysreg_add_field(ID_MMFR4_EL1, "LSM", 20, 23);
+ arm64_sysreg_add_field(ID_MMFR4_EL1, "HPDS", 16, 19);
+ arm64_sysreg_add_field(ID_MMFR4_EL1, "CnP", 12, 15);
+ arm64_sysreg_add_field(ID_MMFR4_EL1, "XNX", 8, 11);
+ arm64_sysreg_add_field(ID_MMFR4_EL1, "AC2", 4, 7);
+ arm64_sysreg_add_field(ID_MMFR4_EL1, "SpecSEI", 0, 3);
+
+ /* MVFR0_EL1 */
+ ARM64SysReg *MVFR0_EL1 = arm64_sysreg_get(MVFR0_EL1_IDX);
+ MVFR0_EL1->name = "MVFR0_EL1";
+ arm64_sysreg_add_field(MVFR0_EL1, "FPRound", 28, 31);
+ arm64_sysreg_add_field(MVFR0_EL1, "FPShVec", 24, 27);
+ arm64_sysreg_add_field(MVFR0_EL1, "FPSqrt", 20, 23);
+ arm64_sysreg_add_field(MVFR0_EL1, "FPDivide", 16, 19);
+ arm64_sysreg_add_field(MVFR0_EL1, "FPTrap", 12, 15);
+ arm64_sysreg_add_field(MVFR0_EL1, "FPDP", 8, 11);
+ arm64_sysreg_add_field(MVFR0_EL1, "FPSP", 4, 7);
+ arm64_sysreg_add_field(MVFR0_EL1, "SIMDReg", 0, 3);
+
+ /* MVFR1_EL1 */
+ ARM64SysReg *MVFR1_EL1 = arm64_sysreg_get(MVFR1_EL1_IDX);
+ MVFR1_EL1->name = "MVFR1_EL1";
+ arm64_sysreg_add_field(MVFR1_EL1, "SIMDFMAC", 28, 31);
+ arm64_sysreg_add_field(MVFR1_EL1, "FPHP", 24, 27);
+ arm64_sysreg_add_field(MVFR1_EL1, "SIMDHP", 20, 23);
+ arm64_sysreg_add_field(MVFR1_EL1, "SIMDSP", 16, 19);
+ arm64_sysreg_add_field(MVFR1_EL1, "SIMDInt", 12, 15);
+ arm64_sysreg_add_field(MVFR1_EL1, "SIMDLS", 8, 11);
+ arm64_sysreg_add_field(MVFR1_EL1, "FPDNaN", 4, 7);
+ arm64_sysreg_add_field(MVFR1_EL1, "FPFtZ", 0, 3);
+
+ /* MVFR2_EL1 */
+ ARM64SysReg *MVFR2_EL1 = arm64_sysreg_get(MVFR2_EL1_IDX);
+ MVFR2_EL1->name = "MVFR2_EL1";
+ arm64_sysreg_add_field(MVFR2_EL1, "FPMisc", 4, 7);
+ arm64_sysreg_add_field(MVFR2_EL1, "SIMDMisc", 0, 3);
+
+ /* ID_PFR2_EL1 */
+ ARM64SysReg *ID_PFR2_EL1 = arm64_sysreg_get(ID_PFR2_EL1_IDX);
+ ID_PFR2_EL1->name = "ID_PFR2_EL1";
+ arm64_sysreg_add_field(ID_PFR2_EL1, "RAS_frac", 8, 11);
+ arm64_sysreg_add_field(ID_PFR2_EL1, "SSBS", 4, 7);
+ arm64_sysreg_add_field(ID_PFR2_EL1, "CSV3", 0, 3);
+
+ /* ID_DFR1_EL1 */
+ ARM64SysReg *ID_DFR1_EL1 = arm64_sysreg_get(ID_DFR1_EL1_IDX);
+ ID_DFR1_EL1->name = "ID_DFR1_EL1";
+ arm64_sysreg_add_field(ID_DFR1_EL1, "HPMN0", 4, 7);
+ arm64_sysreg_add_field(ID_DFR1_EL1, "MTPMU", 0, 3);
+
+ /* ID_MMFR5_EL1 */
+ ARM64SysReg *ID_MMFR5_EL1 = arm64_sysreg_get(ID_MMFR5_EL1_IDX);
+ ID_MMFR5_EL1->name = "ID_MMFR5_EL1";
+ arm64_sysreg_add_field(ID_MMFR5_EL1, "nTLBPA", 4, 7);
+ arm64_sysreg_add_field(ID_MMFR5_EL1, "ETS", 0, 3);
+
+ /* ID_AA64PFR0_EL1 */
+ ARM64SysReg *ID_AA64PFR0_EL1 = arm64_sysreg_get(ID_AA64PFR0_EL1_IDX);
+ ID_AA64PFR0_EL1->name = "ID_AA64PFR0_EL1";
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "CSV3", 60, 63);
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "CSV2", 56, 59);
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "RME", 52, 55);
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "DIT", 48, 51);
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "AMU", 44, 47);
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "MPAM", 40, 43);
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "SEL2", 36, 39);
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "SVE", 32, 35);
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "RAS", 28, 31);
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "GIC", 24, 27);
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "AdvSIMD", 20, 23);
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "AdvSIMD", 20, 23);
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "FP", 16, 19);
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "FP", 16, 19);
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "EL3", 12, 15);
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "EL2", 8, 11);
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "EL1", 4, 7);
+ arm64_sysreg_add_field(ID_AA64PFR0_EL1, "EL0", 0, 3);
+
+ /* ID_AA64PFR1_EL1 */
+ ARM64SysReg *ID_AA64PFR1_EL1 = arm64_sysreg_get(ID_AA64PFR1_EL1_IDX);
+ ID_AA64PFR1_EL1->name = "ID_AA64PFR1_EL1";
+ arm64_sysreg_add_field(ID_AA64PFR1_EL1, "PFAR", 60, 63);
+ arm64_sysreg_add_field(ID_AA64PFR1_EL1, "DF2", 56, 59);
+ arm64_sysreg_add_field(ID_AA64PFR1_EL1, "MTEX", 52, 55);
+ arm64_sysreg_add_field(ID_AA64PFR1_EL1, "THE", 48, 51);
+ arm64_sysreg_add_field(ID_AA64PFR1_EL1, "GCS", 44, 47);
+ arm64_sysreg_add_field(ID_AA64PFR1_EL1, "MTE_frac", 40, 43);
+ arm64_sysreg_add_field(ID_AA64PFR1_EL1, "NMI", 36, 39);
+ arm64_sysreg_add_field(ID_AA64PFR1_EL1, "CSV2_frac", 32, 35);
+ arm64_sysreg_add_field(ID_AA64PFR1_EL1, "RNDR_trap", 28, 31);
+ arm64_sysreg_add_field(ID_AA64PFR1_EL1, "SME", 24, 27);
+ arm64_sysreg_add_field(ID_AA64PFR1_EL1, "MPAM_frac", 16, 19);
+ arm64_sysreg_add_field(ID_AA64PFR1_EL1, "RAS_frac", 12, 15);
+ arm64_sysreg_add_field(ID_AA64PFR1_EL1, "MTE", 8, 11);
+ arm64_sysreg_add_field(ID_AA64PFR1_EL1, "SSBS", 4, 7);
+ arm64_sysreg_add_field(ID_AA64PFR1_EL1, "BT", 0, 3);
+
+ /* ID_AA64PFR2_EL1 */
+ ARM64SysReg *ID_AA64PFR2_EL1 = arm64_sysreg_get(ID_AA64PFR2_EL1_IDX);
+ ID_AA64PFR2_EL1->name = "ID_AA64PFR2_EL1";
+ arm64_sysreg_add_field(ID_AA64PFR2_EL1, "FPMR", 32, 35);
+ arm64_sysreg_add_field(ID_AA64PFR2_EL1, "UINJ", 16, 19);
+ arm64_sysreg_add_field(ID_AA64PFR2_EL1, "MTEFAR", 8, 11);
+ arm64_sysreg_add_field(ID_AA64PFR2_EL1, "MTESTOREONLY", 4, 7);
+ arm64_sysreg_add_field(ID_AA64PFR2_EL1, "MTEPERM", 0, 3);
+
+ /* ID_AA64ZFR0_EL1 */
+ ARM64SysReg *ID_AA64ZFR0_EL1 = arm64_sysreg_get(ID_AA64ZFR0_EL1_IDX);
+ ID_AA64ZFR0_EL1->name = "ID_AA64ZFR0_EL1";
+ arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "F64MM", 56, 59);
+ arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "F32MM", 52, 55);
+ arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "F16MM", 48, 51);
+ arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "I8MM", 44, 47);
+ arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "SM4", 40, 43);
+ arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "SHA3", 32, 35);
+ arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "B16B16", 24, 27);
+ arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "BF16", 20, 23);
+ arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "BitPerm", 16, 19);
+ arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "EltPerm", 12, 15);
+ arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "AES", 4, 7);
+ arm64_sysreg_add_field(ID_AA64ZFR0_EL1, "SVEver", 0, 3);
+
+ /* ID_AA64SMFR0_EL1 */
+ ARM64SysReg *ID_AA64SMFR0_EL1 = arm64_sysreg_get(ID_AA64SMFR0_EL1_IDX);
+ ID_AA64SMFR0_EL1->name = "ID_AA64SMFR0_EL1";
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "FA64", 63, 63);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "LUTv2", 60, 60);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SMEver", 56, 59);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "I16I64", 52, 55);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F64F64", 48, 48);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "I16I32", 44, 47);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "B16B16", 43, 43);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F16F16", 42, 42);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F8F16", 41, 41);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F8F32", 40, 40);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "I8I32", 36, 39);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F16F32", 35, 35);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "B16F32", 34, 34);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "BI32I32", 33, 33);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "F32F32", 32, 32);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SF8FMA", 30, 30);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SF8DP4", 29, 29);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SF8DP2", 28, 28);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SBitPerm", 25, 25);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "AES", 24, 24);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SFEXPA", 23, 23);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "STMOP", 16, 16);
+ arm64_sysreg_add_field(ID_AA64SMFR0_EL1, "SMOP4", 0, 0);
+
+ /* ID_AA64FPFR0_EL1 */
+ ARM64SysReg *ID_AA64FPFR0_EL1 = arm64_sysreg_get(ID_AA64FPFR0_EL1_IDX);
+ ID_AA64FPFR0_EL1->name = "ID_AA64FPFR0_EL1";
+ arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8CVT", 31, 31);
+ arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8FMA", 30, 30);
+ arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8DP4", 29, 29);
+ arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8DP2", 28, 28);
+ arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8MM8", 27, 27);
+ arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8MM4", 26, 26);
+ arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8E4M3", 1, 1);
+ arm64_sysreg_add_field(ID_AA64FPFR0_EL1, "F8E5M2", 0, 0);
+
+ /* ID_AA64DFR0_EL1 */
+ ARM64SysReg *ID_AA64DFR0_EL1 = arm64_sysreg_get(ID_AA64DFR0_EL1_IDX);
+ ID_AA64DFR0_EL1->name = "ID_AA64DFR0_EL1";
+ arm64_sysreg_add_field(ID_AA64DFR0_EL1, "HPMN0", 60, 63);
+ arm64_sysreg_add_field(ID_AA64DFR0_EL1, "ExtTrcBuff", 56, 59);
+ arm64_sysreg_add_field(ID_AA64DFR0_EL1, "BRBE", 52, 55);
+ arm64_sysreg_add_field(ID_AA64DFR0_EL1, "MTPMU", 48, 51);
+ arm64_sysreg_add_field(ID_AA64DFR0_EL1, "MTPMU", 48, 51);
+ arm64_sysreg_add_field(ID_AA64DFR0_EL1, "TraceBuffer", 44, 47);
+ arm64_sysreg_add_field(ID_AA64DFR0_EL1, "TraceFilt", 40, 43);
+ arm64_sysreg_add_field(ID_AA64DFR0_EL1, "DoubleLock", 36, 39);
+ arm64_sysreg_add_field(ID_AA64DFR0_EL1, "PMSVer", 32, 35);
+ arm64_sysreg_add_field(ID_AA64DFR0_EL1, "CTX_CMPs", 28, 31);
+ arm64_sysreg_add_field(ID_AA64DFR0_EL1, "SEBEP", 24, 27);
+ arm64_sysreg_add_field(ID_AA64DFR0_EL1, "WRPs", 20, 23);
+ arm64_sysreg_add_field(ID_AA64DFR0_EL1, "PMSS", 16, 19);
+ arm64_sysreg_add_field(ID_AA64DFR0_EL1, "BRPs", 12, 15);
+ arm64_sysreg_add_field(ID_AA64DFR0_EL1, "PMUVer", 8, 11);
+ arm64_sysreg_add_field(ID_AA64DFR0_EL1, "TraceVer", 4, 7);
+ arm64_sysreg_add_field(ID_AA64DFR0_EL1, "DebugVer", 0, 3);
+
+ /* ID_AA64DFR1_EL1 */
+ ARM64SysReg *ID_AA64DFR1_EL1 = arm64_sysreg_get(ID_AA64DFR1_EL1_IDX);
+ ID_AA64DFR1_EL1->name = "ID_AA64DFR1_EL1";
+ arm64_sysreg_add_field(ID_AA64DFR1_EL1, "ABL_CMPs", 56, 63);
+ arm64_sysreg_add_field(ID_AA64DFR1_EL1, "DPFZS", 52, 55);
+ arm64_sysreg_add_field(ID_AA64DFR1_EL1, "EBEP", 48, 51);
+ arm64_sysreg_add_field(ID_AA64DFR1_EL1, "ITE", 44, 47);
+ arm64_sysreg_add_field(ID_AA64DFR1_EL1, "ABLE", 40, 43);
+ arm64_sysreg_add_field(ID_AA64DFR1_EL1, "PMICNTR", 36, 39);
+ arm64_sysreg_add_field(ID_AA64DFR1_EL1, "SPMU", 32, 35);
+ arm64_sysreg_add_field(ID_AA64DFR1_EL1, "CTX_CMPs", 24, 31);
+ arm64_sysreg_add_field(ID_AA64DFR1_EL1, "WRPs", 16, 23);
+ arm64_sysreg_add_field(ID_AA64DFR1_EL1, "BRPs", 8, 15);
+ arm64_sysreg_add_field(ID_AA64DFR1_EL1, "SYSPMUID", 0, 7);
+
+ /* ID_AA64DFR2_EL1 */
+ ARM64SysReg *ID_AA64DFR2_EL1 = arm64_sysreg_get(ID_AA64DFR2_EL1_IDX);
+ ID_AA64DFR2_EL1->name = "ID_AA64DFR2_EL1";
+ arm64_sysreg_add_field(ID_AA64DFR2_EL1, "TRBE_EXC", 24, 27);
+ arm64_sysreg_add_field(ID_AA64DFR2_EL1, "SPE_nVM", 20, 23);
+ arm64_sysreg_add_field(ID_AA64DFR2_EL1, "SPE_EXC", 16, 19);
+ arm64_sysreg_add_field(ID_AA64DFR2_EL1, "BWE", 4, 7);
+ arm64_sysreg_add_field(ID_AA64DFR2_EL1, "STEP", 0, 3);
+
+ /* ID_AA64AFR0_EL1 */
+ ARM64SysReg *ID_AA64AFR0_EL1 = arm64_sysreg_get(ID_AA64AFR0_EL1_IDX);
+ ID_AA64AFR0_EL1->name = "ID_AA64AFR0_EL1";
+ arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF7", 28, 31);
+ arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF6", 24, 27);
+ arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF5", 20, 23);
+ arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF4", 16, 19);
+ arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF3", 12, 15);
+ arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF2", 8, 11);
+ arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF1", 4, 7);
+ arm64_sysreg_add_field(ID_AA64AFR0_EL1, "IMPDEF0", 0, 3);
+
+ /* ID_AA64AFR1_EL1 */
+ ARM64SysReg *ID_AA64AFR1_EL1 = arm64_sysreg_get(ID_AA64AFR1_EL1_IDX);
+ ID_AA64AFR1_EL1->name = "ID_AA64AFR1_EL1";
+
+ /* ID_AA64ISAR0_EL1 */
+ ARM64SysReg *ID_AA64ISAR0_EL1 = arm64_sysreg_get(ID_AA64ISAR0_EL1_IDX);
+ ID_AA64ISAR0_EL1->name = "ID_AA64ISAR0_EL1";
+ arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "RNDR", 60, 63);
+ arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "TLB", 56, 59);
+ arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "TS", 52, 55);
+ arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "FHM", 48, 51);
+ arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "DP", 44, 47);
+ arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "SM4", 40, 43);
+ arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "SM3", 36, 39);
+ arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "SHA3", 32, 35);
+ arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "RDM", 28, 31);
+ arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "TME", 24, 27);
+ arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "ATOMIC", 20, 23);
+ arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "CRC32", 16, 19);
+ arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "SHA2", 12, 15);
+ arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "SHA1", 8, 11);
+ arm64_sysreg_add_field(ID_AA64ISAR0_EL1, "AES", 4, 7);
+
+ /* ID_AA64ISAR1_EL1 */
+ ARM64SysReg *ID_AA64ISAR1_EL1 = arm64_sysreg_get(ID_AA64ISAR1_EL1_IDX);
+ ID_AA64ISAR1_EL1->name = "ID_AA64ISAR1_EL1";
+ arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "LS64", 60, 63);
+ arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "XS", 56, 59);
+ arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "I8MM", 52, 55);
+ arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "DGH", 48, 51);
+ arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "BF16", 44, 47);
+ arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "SPECRES", 40, 43);
+ arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "SB", 36, 39);
+ arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "FRINTTS", 32, 35);
+ arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "GPI", 28, 31);
+ arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "GPA", 24, 27);
+ arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "LRCPC", 20, 23);
+ arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "FCMA", 16, 19);
+ arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "JSCVT", 12, 15);
+ arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "API", 8, 11);
+ arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "APA", 4, 7);
+ arm64_sysreg_add_field(ID_AA64ISAR1_EL1, "DPB", 0, 3);
+
+ /* ID_AA64ISAR2_EL1 */
+ ARM64SysReg *ID_AA64ISAR2_EL1 = arm64_sysreg_get(ID_AA64ISAR2_EL1_IDX);
+ ID_AA64ISAR2_EL1->name = "ID_AA64ISAR2_EL1";
+ arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "ATS1A", 60, 63);
+ arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "LUT", 56, 59);
+ arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "CSSC", 52, 55);
+ arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "RPRFM", 48, 51);
+ arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "PCDPHINT", 44, 47);
+ arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "PRFMSLC", 40, 43);
+ arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "SYSINSTR_128", 36, 39);
+ arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "SYSREG_128", 32, 35);
+ arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "CLRBHB", 28, 31);
+ arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "PAC_frac", 24, 27);
+ arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "BC", 20, 23);
+ arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "MOPS", 16, 19);
+ arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "APA3", 12, 15);
+ arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "GPA3", 8, 11);
+ arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "RPRES", 4, 7);
+ arm64_sysreg_add_field(ID_AA64ISAR2_EL1, "WFxT", 0, 3);
+
+ /* ID_AA64ISAR3_EL1 */
+ ARM64SysReg *ID_AA64ISAR3_EL1 = arm64_sysreg_get(ID_AA64ISAR3_EL1_IDX);
+ ID_AA64ISAR3_EL1->name = "ID_AA64ISAR3_EL1";
+ arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "FPRCVT", 28, 31);
+ arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "LSUI", 24, 27);
+ arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "OCCMO", 20, 23);
+ arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "LSFE", 16, 19);
+ arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "PACM", 12, 15);
+ arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "TLBIW", 8, 11);
+ arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "FAMINMAX", 4, 7);
+ arm64_sysreg_add_field(ID_AA64ISAR3_EL1, "CPA", 0, 3);
+
+ /* ID_AA64MMFR0_EL1 */
+ ARM64SysReg *ID_AA64MMFR0_EL1 = arm64_sysreg_get(ID_AA64MMFR0_EL1_IDX);
+ ID_AA64MMFR0_EL1->name = "ID_AA64MMFR0_EL1";
+ arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "ECV", 60, 63);
+ arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "FGT", 56, 59);
+ arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "EXS", 44, 47);
+ arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN4_2", 40, 43);
+ arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN64_2", 36, 39);
+ arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN16_2", 32, 35);
+ arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN4", 28, 31);
+ arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN4", 28, 31);
+ arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN64", 24, 27);
+ arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN64", 24, 27);
+ arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "TGRAN16", 20, 23);
+ arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "BIGENDEL0", 16, 19);
+ arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "SNSMEM", 12, 15);
+ arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "BIGEND", 8, 11);
+ arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "ASIDBITS", 4, 7);
+ arm64_sysreg_add_field(ID_AA64MMFR0_EL1, "PARANGE", 0, 3);
+
+ /* ID_AA64MMFR1_EL1 */
+ ARM64SysReg *ID_AA64MMFR1_EL1 = arm64_sysreg_get(ID_AA64MMFR1_EL1_IDX);
+ ID_AA64MMFR1_EL1->name = "ID_AA64MMFR1_EL1";
+ arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "ECBHB", 60, 63);
+ arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "CMOW", 56, 59);
+ arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "TIDCP1", 52, 55);
+ arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "nTLBPA", 48, 51);
+ arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "AFP", 44, 47);
+ arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "HCX", 40, 43);
+ arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "ETS", 36, 39);
+ arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "TWED", 32, 35);
+ arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "XNX", 28, 31);
+ arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "SpecSEI", 24, 27);
+ arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "PAN", 20, 23);
+ arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "LO", 16, 19);
+ arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "HPDS", 12, 15);
+ arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "VH", 8, 11);
+ arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "VMIDBits", 4, 7);
+ arm64_sysreg_add_field(ID_AA64MMFR1_EL1, "HAFDBS", 0, 3);
+
+ /* ID_AA64MMFR2_EL1 */
+ ARM64SysReg *ID_AA64MMFR2_EL1 = arm64_sysreg_get(ID_AA64MMFR2_EL1_IDX);
+ ID_AA64MMFR2_EL1->name = "ID_AA64MMFR2_EL1";
+ arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "E0PD", 60, 63);
+ arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "EVT", 56, 59);
+ arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "BBM", 52, 55);
+ arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "TTL", 48, 51);
+ arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "FWB", 40, 43);
+ arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "IDS", 36, 39);
+ arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "AT", 32, 35);
+ arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "ST", 28, 31);
+ arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "NV", 24, 27);
+ arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "CCIDX", 20, 23);
+ arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "VARange", 16, 19);
+ arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "IESB", 12, 15);
+ arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "LSM", 8, 11);
+ arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "UAO", 4, 7);
+ arm64_sysreg_add_field(ID_AA64MMFR2_EL1, "CnP", 0, 3);
+
+ /* ID_AA64MMFR3_EL1 */
+ ARM64SysReg *ID_AA64MMFR3_EL1 = arm64_sysreg_get(ID_AA64MMFR3_EL1_IDX);
+ ID_AA64MMFR3_EL1->name = "ID_AA64MMFR3_EL1";
+ arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "Spec_FPACC", 60, 63);
+ arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "ADERR", 56, 59);
+ arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "SDERR", 52, 55);
+ arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "ANERR", 44, 47);
+ arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "SNERR", 40, 43);
+ arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "D128_2", 36, 39);
+ arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "D128", 32, 35);
+ arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "MEC", 28, 31);
+ arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "AIE", 24, 27);
+ arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "S2POE", 20, 23);
+ arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "S1POE", 16, 19);
+ arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "S2PIE", 12, 15);
+ arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "S1PIE", 8, 11);
+ arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "SCTLRX", 4, 7);
+ arm64_sysreg_add_field(ID_AA64MMFR3_EL1, "TCRX", 0, 3);
+
+ /* ID_AA64MMFR4_EL1 */
+ ARM64SysReg *ID_AA64MMFR4_EL1 = arm64_sysreg_get(ID_AA64MMFR4_EL1_IDX);
+ ID_AA64MMFR4_EL1->name = "ID_AA64MMFR4_EL1";
+ arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "E3DSE", 36, 39);
+ arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "E2H0", 24, 27);
+ arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "E2H0", 24, 27);
+ arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "NV_frac", 20, 23);
+ arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "FGWTE3", 16, 19);
+ arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "HACDBS", 12, 15);
+ arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "ASID2", 8, 11);
+ arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "EIESB", 4, 7);
+ arm64_sysreg_add_field(ID_AA64MMFR4_EL1, "EIESB", 4, 7);
+
+/* For ZCR_EL1 fields see ZCR_ELx */
+
+/* For SMCR_EL1 fields see SMCR_ELx */
+
+/* For GCSCR_EL1 fields see GCSCR_ELx */
+
+/* For GCSPR_EL1 fields see GCSPR_ELx */
+
+/* For CONTEXTIDR_EL1 fields see CONTEXTIDR_ELx */
+
+ /* CCSIDR_EL1 */
+ ARM64SysReg *CCSIDR_EL1 = arm64_sysreg_get(CCSIDR_EL1_IDX);
+ CCSIDR_EL1->name = "CCSIDR_EL1";
+ arm64_sysreg_add_field(CCSIDR_EL1, "NumSets", 13, 27);
+ arm64_sysreg_add_field(CCSIDR_EL1, "Associativity", 3, 12);
+ arm64_sysreg_add_field(CCSIDR_EL1, "LineSize", 0, 2);
+
+ /* CLIDR_EL1 */
+ ARM64SysReg *CLIDR_EL1 = arm64_sysreg_get(CLIDR_EL1_IDX);
+ CLIDR_EL1->name = "CLIDR_EL1";
+ arm64_sysreg_add_field(CLIDR_EL1, "Ttypen", 33, 46);
+ arm64_sysreg_add_field(CLIDR_EL1, "ICB", 30, 32);
+ arm64_sysreg_add_field(CLIDR_EL1, "LoUU", 27, 29);
+ arm64_sysreg_add_field(CLIDR_EL1, "LoC", 24, 26);
+ arm64_sysreg_add_field(CLIDR_EL1, "LoUIS", 21, 23);
+ arm64_sysreg_add_field(CLIDR_EL1, "Ctype7", 18, 20);
+ arm64_sysreg_add_field(CLIDR_EL1, "Ctype6", 15, 17);
+ arm64_sysreg_add_field(CLIDR_EL1, "Ctype5", 12, 14);
+ arm64_sysreg_add_field(CLIDR_EL1, "Ctype4", 9, 11);
+ arm64_sysreg_add_field(CLIDR_EL1, "Ctype3", 6, 8);
+ arm64_sysreg_add_field(CLIDR_EL1, "Ctype2", 3, 5);
+ arm64_sysreg_add_field(CLIDR_EL1, "Ctype1", 0, 2);
+
+ /* CCSIDR2_EL1 */
+ ARM64SysReg *CCSIDR2_EL1 = arm64_sysreg_get(CCSIDR2_EL1_IDX);
+ CCSIDR2_EL1->name = "CCSIDR2_EL1";
+ arm64_sysreg_add_field(CCSIDR2_EL1, "NumSets", 0, 23);
+
+ /* GMID_EL1 */
+ ARM64SysReg *GMID_EL1 = arm64_sysreg_get(GMID_EL1_IDX);
+ GMID_EL1->name = "GMID_EL1";
+ arm64_sysreg_add_field(GMID_EL1, "BS", 0, 3);
+
+ /* SMIDR_EL1 */
+ ARM64SysReg *SMIDR_EL1 = arm64_sysreg_get(SMIDR_EL1_IDX);
+ SMIDR_EL1->name = "SMIDR_EL1";
+ arm64_sysreg_add_field(SMIDR_EL1, "IMPLEMENTER", 24, 31);
+ arm64_sysreg_add_field(SMIDR_EL1, "REVISION", 16, 23);
+ arm64_sysreg_add_field(SMIDR_EL1, "SMPS", 15, 15);
+ arm64_sysreg_add_field(SMIDR_EL1, "AFFINITY", 0, 11);
+
+ /* CSSELR_EL1 */
+ ARM64SysReg *CSSELR_EL1 = arm64_sysreg_get(CSSELR_EL1_IDX);
+ CSSELR_EL1->name = "CSSELR_EL1";
+ arm64_sysreg_add_field(CSSELR_EL1, "TnD", 4, 4);
+ arm64_sysreg_add_field(CSSELR_EL1, "Level", 1, 3);
+ arm64_sysreg_add_field(CSSELR_EL1, "InD", 0, 0);
+
/* CTR_EL0 */
ARM64SysReg *CTR_EL0 = arm64_sysreg_get(CTR_EL0_IDX);
CTR_EL0->name = "CTR_EL0";
@@ -37,5 +637,77 @@ void initialize_cpu_sysreg_properties(void)
arm64_sysreg_add_field(CTR_EL0, "DminLine", 16, 19);
arm64_sysreg_add_field(CTR_EL0, "L1Ip", 14, 15);
arm64_sysreg_add_field(CTR_EL0, "IminLine", 0, 3);
-}
+ /* DCZID_EL0 */
+ ARM64SysReg *DCZID_EL0 = arm64_sysreg_get(DCZID_EL0_IDX);
+ DCZID_EL0->name = "DCZID_EL0";
+ arm64_sysreg_add_field(DCZID_EL0, "DZP", 4, 4);
+ arm64_sysreg_add_field(DCZID_EL0, "BS", 0, 3);
+
+/* For GCSPR_EL0 fields see GCSPR_ELx */
+
+/* For HFGRTR_EL2 fields see HFGxTR_EL2 */
+
+/* For HFGWTR_EL2 fields see HFGxTR_EL2 */
+
+/* For ZCR_EL2 fields see ZCR_ELx */
+
+/* For SMCR_EL2 fields see SMCR_ELx */
+
+/* For GCSCR_EL2 fields see GCSCR_ELx */
+
+/* For GCSPR_EL2 fields see GCSPR_ELx */
+
+/* For CONTEXTIDR_EL2 fields see CONTEXTIDR_ELx */
+
+/* For CPACR_EL12 fields see CPACR_EL1 */
+
+/* For ZCR_EL12 fields see ZCR_EL1 */
+
+/* For TRFCR_EL12 fields see TRFCR_EL1 */
+
+/* For SMCR_EL12 fields see SMCR_EL1 */
+
+/* For GCSCR_EL12 fields see GCSCR_EL1 */
+
+/* For GCSPR_EL12 fields see GCSPR_EL1 */
+
+/* For MPAM1_EL12 fields see MPAM1_ELx */
+
+/* For CONTEXTIDR_EL12 fields see CONTEXTIDR_EL1 */
+
+/* For TTBR0_EL1 fields see TTBRx_EL1 */
+
+/* For TTBR1_EL1 fields see TTBRx_EL1 */
+
+/* For TCR2_EL12 fields see TCR2_EL1 */
+
+/* For MAIR2_EL1 fields see MAIR2_ELx */
+
+/* For MAIR2_EL2 fields see MAIR2_ELx */
+
+/* For PIRE0_EL1 fields see PIRx_ELx */
+
+/* For PIRE0_EL12 fields see PIRE0_EL1 */
+
+/* For PIRE0_EL2 fields see PIRx_ELx */
+
+/* For PIR_EL1 fields see PIRx_ELx */
+
+/* For PIR_EL12 fields see PIR_EL1 */
+
+/* For PIR_EL2 fields see PIRx_ELx */
+
+/* For POR_EL0 fields see PIRx_ELx */
+
+/* For POR_EL1 fields see PIRx_ELx */
+
+/* For POR_EL2 fields see PIRx_ELx */
+
+/* For POR_EL12 fields see POR_EL1 */
+
+/* For S2POR_EL1 fields see PIRx_ELx */
+
+/* For S2PIR_EL2 fields see PIRx_ELx */
+
+}
diff --git a/target/arm/cpu-sysregs.h b/target/arm/cpu-sysregs.h
index 54a4fadbf0c1..6074516c6d2c 100644
--- a/target/arm/cpu-sysregs.h
+++ b/target/arm/cpu-sysregs.h
@@ -13,120 +13,8 @@
((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \
((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT))
-typedef enum ARMIDRegisterIdx {
- ID_AA64PFR0_EL1_IDX,
- ID_AA64PFR1_EL1_IDX,
- ID_AA64SMFR0_EL1_IDX,
- ID_AA64DFR0_EL1_IDX,
- ID_AA64DFR1_EL1_IDX,
- ID_AA64ISAR0_EL1_IDX,
- ID_AA64ISAR1_EL1_IDX,
- ID_AA64ISAR2_EL1_IDX,
- ID_AA64MMFR0_EL1_IDX,
- ID_AA64MMFR1_EL1_IDX,
- ID_AA64MMFR2_EL1_IDX,
- ID_AA64MMFR3_EL1_IDX,
- ID_PFR0_EL1_IDX,
- ID_PFR1_EL1_IDX,
- ID_DFR0_EL1_IDX,
- ID_MMFR0_EL1_IDX,
- ID_MMFR1_EL1_IDX,
- ID_MMFR2_EL1_IDX,
- ID_MMFR3_EL1_IDX,
- ID_ISAR0_EL1_IDX,
- ID_ISAR1_EL1_IDX,
- ID_ISAR2_EL1_IDX,
- ID_ISAR3_EL1_IDX,
- ID_ISAR4_EL1_IDX,
- ID_ISAR5_EL1_IDX,
- ID_MMFR4_EL1_IDX,
- ID_ISAR6_EL1_IDX,
- MVFR0_EL1_IDX,
- MVFR1_EL1_IDX,
- MVFR2_EL1_IDX,
- ID_PFR2_EL1_IDX,
- ID_DFR1_EL1_IDX,
- ID_MMFR5_EL1_IDX,
- ID_AA64ZFR0_EL1_IDX,
- CTR_EL0_IDX,
- NUM_ID_IDX,
-} ARMIDRegisterIdx;
-
-typedef enum ARMSysRegs {
- SYS_ID_AA64PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 0),
- SYS_ID_AA64PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 1),
- SYS_ID_AA64SMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 5),
- SYS_ID_AA64DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 0),
- SYS_ID_AA64DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 1),
- SYS_ID_AA64ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 0),
- SYS_ID_AA64ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 1),
- SYS_ID_AA64ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 2),
- SYS_ID_AA64MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 0),
- SYS_ID_AA64MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 1),
- SYS_ID_AA64MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 2),
- SYS_ID_AA64MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 3),
- SYS_ID_PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 0),
- SYS_ID_PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 1),
- SYS_ID_DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 2),
- SYS_ID_MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 4),
- SYS_ID_MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 5),
- SYS_ID_MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 6),
- SYS_ID_MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 7),
- SYS_ID_ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 0),
- SYS_ID_ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 1),
- SYS_ID_ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 2),
- SYS_ID_ISAR3_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 3),
- SYS_ID_ISAR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 4),
- SYS_ID_ISAR5_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 5),
- SYS_ID_MMFR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 6),
- SYS_ID_ISAR6_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 7),
- SYS_MVFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 0),
- SYS_MVFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 1),
- SYS_MVFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 2),
- SYS_ID_PFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 4),
- SYS_ID_DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 5),
- SYS_ID_MMFR5_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 6),
- SYS_ID_AA64ZFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 4),
- SYS_CTR_EL0 = ENCODE_ID_REG(3, 3, 0, 0, 1),
-} ARMSysRegs;
-
-static const uint32_t id_register_sysreg[NUM_ID_IDX] = {
- [ID_AA64PFR0_EL1_IDX] = SYS_ID_AA64PFR0_EL1,
- [ID_AA64PFR1_EL1_IDX] = SYS_ID_AA64PFR1_EL1,
- [ID_AA64SMFR0_EL1_IDX] = SYS_ID_AA64SMFR0_EL1,
- [ID_AA64DFR0_EL1_IDX] = SYS_ID_AA64DFR0_EL1,
- [ID_AA64DFR1_EL1_IDX] = SYS_ID_AA64DFR1_EL1,
- [ID_AA64ISAR0_EL1_IDX] = SYS_ID_AA64ISAR0_EL1,
- [ID_AA64ISAR1_EL1_IDX] = SYS_ID_AA64ISAR1_EL1,
- [ID_AA64ISAR2_EL1_IDX] = SYS_ID_AA64ISAR2_EL1,
- [ID_AA64MMFR0_EL1_IDX] = SYS_ID_AA64MMFR0_EL1,
- [ID_AA64MMFR1_EL1_IDX] = SYS_ID_AA64MMFR1_EL1,
- [ID_AA64MMFR2_EL1_IDX] = SYS_ID_AA64MMFR2_EL1,
- [ID_AA64MMFR3_EL1_IDX] = SYS_ID_AA64MMFR3_EL1,
- [ID_PFR0_EL1_IDX] = SYS_ID_PFR0_EL1,
- [ID_PFR1_EL1_IDX] = SYS_ID_PFR1_EL1,
- [ID_DFR0_EL1_IDX] = SYS_ID_DFR0_EL1,
- [ID_MMFR0_EL1_IDX] = SYS_ID_MMFR0_EL1,
- [ID_MMFR1_EL1_IDX] = SYS_ID_MMFR1_EL1,
- [ID_MMFR2_EL1_IDX] = SYS_ID_MMFR2_EL1,
- [ID_MMFR3_EL1_IDX] = SYS_ID_MMFR3_EL1,
- [ID_ISAR0_EL1_IDX] = SYS_ID_ISAR0_EL1,
- [ID_ISAR1_EL1_IDX] = SYS_ID_ISAR1_EL1,
- [ID_ISAR2_EL1_IDX] = SYS_ID_ISAR2_EL1,
- [ID_ISAR3_EL1_IDX] = SYS_ID_ISAR3_EL1,
- [ID_ISAR4_EL1_IDX] = SYS_ID_ISAR4_EL1,
- [ID_ISAR5_EL1_IDX] = SYS_ID_ISAR5_EL1,
- [ID_MMFR4_EL1_IDX] = SYS_ID_MMFR4_EL1,
- [ID_ISAR6_EL1_IDX] = SYS_ID_ISAR6_EL1,
- [MVFR0_EL1_IDX] = SYS_MVFR0_EL1,
- [MVFR1_EL1_IDX] = SYS_MVFR1_EL1,
- [MVFR2_EL1_IDX] = SYS_MVFR2_EL1,
- [ID_PFR2_EL1_IDX] = SYS_ID_PFR2_EL1,
- [ID_DFR1_EL1_IDX] = SYS_ID_DFR1_EL1,
- [ID_MMFR5_EL1_IDX] = SYS_ID_MMFR5_EL1,
- [ID_AA64ZFR0_EL1_IDX] = SYS_ID_AA64ZFR0_EL1,
- [CTR_EL0_IDX] = SYS_CTR_EL0,
-};
+/* include generated definitions */
+#include "cpu-sysregs.h.inc"
int get_sysreg_idx(ARMSysRegs sysreg);
uint64_t idregs_sysreg_to_kvm_reg(ARMSysRegs sysreg);
diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
new file mode 100644
index 000000000000..eee4187f580e
--- /dev/null
+++ b/target/arm/cpu-sysregs.h.inc
@@ -0,0 +1,164 @@
+/* GENERATED FILE -- DO NOT EDIT */
+
+typedef enum ARMIDRegisterIdx {
+ ID_PFR0_EL1_IDX,
+ ID_PFR1_EL1_IDX,
+ ID_DFR0_EL1_IDX,
+ ID_AFR0_EL1_IDX,
+ ID_MMFR0_EL1_IDX,
+ ID_MMFR1_EL1_IDX,
+ ID_MMFR2_EL1_IDX,
+ ID_MMFR3_EL1_IDX,
+ ID_ISAR0_EL1_IDX,
+ ID_ISAR1_EL1_IDX,
+ ID_ISAR2_EL1_IDX,
+ ID_ISAR3_EL1_IDX,
+ ID_ISAR4_EL1_IDX,
+ ID_ISAR5_EL1_IDX,
+ ID_ISAR6_EL1_IDX,
+ ID_MMFR4_EL1_IDX,
+ MVFR0_EL1_IDX,
+ MVFR1_EL1_IDX,
+ MVFR2_EL1_IDX,
+ ID_PFR2_EL1_IDX,
+ ID_DFR1_EL1_IDX,
+ ID_MMFR5_EL1_IDX,
+ ID_AA64PFR0_EL1_IDX,
+ ID_AA64PFR1_EL1_IDX,
+ ID_AA64PFR2_EL1_IDX,
+ ID_AA64ZFR0_EL1_IDX,
+ ID_AA64SMFR0_EL1_IDX,
+ ID_AA64FPFR0_EL1_IDX,
+ ID_AA64DFR0_EL1_IDX,
+ ID_AA64DFR1_EL1_IDX,
+ ID_AA64DFR2_EL1_IDX,
+ ID_AA64AFR0_EL1_IDX,
+ ID_AA64AFR1_EL1_IDX,
+ ID_AA64ISAR0_EL1_IDX,
+ ID_AA64ISAR1_EL1_IDX,
+ ID_AA64ISAR2_EL1_IDX,
+ ID_AA64ISAR3_EL1_IDX,
+ ID_AA64MMFR0_EL1_IDX,
+ ID_AA64MMFR1_EL1_IDX,
+ ID_AA64MMFR2_EL1_IDX,
+ ID_AA64MMFR3_EL1_IDX,
+ ID_AA64MMFR4_EL1_IDX,
+ CCSIDR_EL1_IDX,
+ CLIDR_EL1_IDX,
+ CCSIDR2_EL1_IDX,
+ GMID_EL1_IDX,
+ SMIDR_EL1_IDX,
+ CSSELR_EL1_IDX,
+ CTR_EL0_IDX,
+ DCZID_EL0_IDX,
+ NUM_ID_IDX,
+} ARMIDRegisterIdx;
+
+
+typedef enum ARMSysRegs {
+ SYS_ID_PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 0),
+ SYS_ID_PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 1),
+ SYS_ID_DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 2),
+ SYS_ID_AFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 3),
+ SYS_ID_MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 4),
+ SYS_ID_MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 5),
+ SYS_ID_MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 6),
+ SYS_ID_MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 1, 7),
+ SYS_ID_ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 0),
+ SYS_ID_ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 1),
+ SYS_ID_ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 2),
+ SYS_ID_ISAR3_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 3),
+ SYS_ID_ISAR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 4),
+ SYS_ID_ISAR5_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 5),
+ SYS_ID_ISAR6_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 7),
+ SYS_ID_MMFR4_EL1 = ENCODE_ID_REG(3, 0, 0, 2, 6),
+ SYS_MVFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 0),
+ SYS_MVFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 1),
+ SYS_MVFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 2),
+ SYS_ID_PFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 4),
+ SYS_ID_DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 5),
+ SYS_ID_MMFR5_EL1 = ENCODE_ID_REG(3, 0, 0, 3, 6),
+ SYS_ID_AA64PFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 0),
+ SYS_ID_AA64PFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 1),
+ SYS_ID_AA64PFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 2),
+ SYS_ID_AA64ZFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 4),
+ SYS_ID_AA64SMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 5),
+ SYS_ID_AA64FPFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 4, 7),
+ SYS_ID_AA64DFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 0),
+ SYS_ID_AA64DFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 1),
+ SYS_ID_AA64DFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 2),
+ SYS_ID_AA64AFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 4),
+ SYS_ID_AA64AFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 5, 5),
+ SYS_ID_AA64ISAR0_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 0),
+ SYS_ID_AA64ISAR1_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 1),
+ SYS_ID_AA64ISAR2_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 2),
+ SYS_ID_AA64ISAR3_EL1 = ENCODE_ID_REG(3, 0, 0, 6, 3),
+ SYS_ID_AA64MMFR0_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 0),
+ SYS_ID_AA64MMFR1_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 1),
+ SYS_ID_AA64MMFR2_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 2),
+ SYS_ID_AA64MMFR3_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 3),
+ SYS_ID_AA64MMFR4_EL1 = ENCODE_ID_REG(3, 0, 0, 7, 4),
+ SYS_CCSIDR_EL1 = ENCODE_ID_REG(3, 1, 0, 0, 0),
+ SYS_CLIDR_EL1 = ENCODE_ID_REG(3, 1, 0, 0, 1),
+ SYS_CCSIDR2_EL1 = ENCODE_ID_REG(3, 1, 0, 0, 2),
+ SYS_GMID_EL1 = ENCODE_ID_REG(3, 1, 0, 0, 4),
+ SYS_SMIDR_EL1 = ENCODE_ID_REG(3, 1, 0, 0, 6),
+ SYS_CSSELR_EL1 = ENCODE_ID_REG(3, 2, 0, 0, 0),
+ SYS_CTR_EL0 = ENCODE_ID_REG(3, 3, 0, 0, 1),
+ SYS_DCZID_EL0 = ENCODE_ID_REG(3, 3, 0, 0, 7),
+} ARMSysRegs;
+
+
+static const uint32_t id_register_sysreg[NUM_ID_IDX] = {
+ [ID_PFR0_EL1_IDX] = SYS_ID_PFR0_EL1,
+ [ID_PFR1_EL1_IDX] = SYS_ID_PFR1_EL1,
+ [ID_DFR0_EL1_IDX] = SYS_ID_DFR0_EL1,
+ [ID_AFR0_EL1_IDX] = SYS_ID_AFR0_EL1,
+ [ID_MMFR0_EL1_IDX] = SYS_ID_MMFR0_EL1,
+ [ID_MMFR1_EL1_IDX] = SYS_ID_MMFR1_EL1,
+ [ID_MMFR2_EL1_IDX] = SYS_ID_MMFR2_EL1,
+ [ID_MMFR3_EL1_IDX] = SYS_ID_MMFR3_EL1,
+ [ID_ISAR0_EL1_IDX] = SYS_ID_ISAR0_EL1,
+ [ID_ISAR1_EL1_IDX] = SYS_ID_ISAR1_EL1,
+ [ID_ISAR2_EL1_IDX] = SYS_ID_ISAR2_EL1,
+ [ID_ISAR3_EL1_IDX] = SYS_ID_ISAR3_EL1,
+ [ID_ISAR4_EL1_IDX] = SYS_ID_ISAR4_EL1,
+ [ID_ISAR5_EL1_IDX] = SYS_ID_ISAR5_EL1,
+ [ID_ISAR6_EL1_IDX] = SYS_ID_ISAR6_EL1,
+ [ID_MMFR4_EL1_IDX] = SYS_ID_MMFR4_EL1,
+ [MVFR0_EL1_IDX] = SYS_MVFR0_EL1,
+ [MVFR1_EL1_IDX] = SYS_MVFR1_EL1,
+ [MVFR2_EL1_IDX] = SYS_MVFR2_EL1,
+ [ID_PFR2_EL1_IDX] = SYS_ID_PFR2_EL1,
+ [ID_DFR1_EL1_IDX] = SYS_ID_DFR1_EL1,
+ [ID_MMFR5_EL1_IDX] = SYS_ID_MMFR5_EL1,
+ [ID_AA64PFR0_EL1_IDX] = SYS_ID_AA64PFR0_EL1,
+ [ID_AA64PFR1_EL1_IDX] = SYS_ID_AA64PFR1_EL1,
+ [ID_AA64PFR2_EL1_IDX] = SYS_ID_AA64PFR2_EL1,
+ [ID_AA64ZFR0_EL1_IDX] = SYS_ID_AA64ZFR0_EL1,
+ [ID_AA64SMFR0_EL1_IDX] = SYS_ID_AA64SMFR0_EL1,
+ [ID_AA64FPFR0_EL1_IDX] = SYS_ID_AA64FPFR0_EL1,
+ [ID_AA64DFR0_EL1_IDX] = SYS_ID_AA64DFR0_EL1,
+ [ID_AA64DFR1_EL1_IDX] = SYS_ID_AA64DFR1_EL1,
+ [ID_AA64DFR2_EL1_IDX] = SYS_ID_AA64DFR2_EL1,
+ [ID_AA64AFR0_EL1_IDX] = SYS_ID_AA64AFR0_EL1,
+ [ID_AA64AFR1_EL1_IDX] = SYS_ID_AA64AFR1_EL1,
+ [ID_AA64ISAR0_EL1_IDX] = SYS_ID_AA64ISAR0_EL1,
+ [ID_AA64ISAR1_EL1_IDX] = SYS_ID_AA64ISAR1_EL1,
+ [ID_AA64ISAR2_EL1_IDX] = SYS_ID_AA64ISAR2_EL1,
+ [ID_AA64ISAR3_EL1_IDX] = SYS_ID_AA64ISAR3_EL1,
+ [ID_AA64MMFR0_EL1_IDX] = SYS_ID_AA64MMFR0_EL1,
+ [ID_AA64MMFR1_EL1_IDX] = SYS_ID_AA64MMFR1_EL1,
+ [ID_AA64MMFR2_EL1_IDX] = SYS_ID_AA64MMFR2_EL1,
+ [ID_AA64MMFR3_EL1_IDX] = SYS_ID_AA64MMFR3_EL1,
+ [ID_AA64MMFR4_EL1_IDX] = SYS_ID_AA64MMFR4_EL1,
+ [CCSIDR_EL1_IDX] = SYS_CCSIDR_EL1,
+ [CLIDR_EL1_IDX] = SYS_CLIDR_EL1,
+ [CCSIDR2_EL1_IDX] = SYS_CCSIDR2_EL1,
+ [GMID_EL1_IDX] = SYS_GMID_EL1,
+ [SMIDR_EL1_IDX] = SYS_SMIDR_EL1,
+ [CSSELR_EL1_IDX] = SYS_CSSELR_EL1,
+ [CTR_EL0_IDX] = SYS_CTR_EL0,
+ [DCZID_EL0_IDX] = SYS_DCZID_EL0,
+};
+
--
2.48.1
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH 15/15] arm/cpu: Add generated files
2025-02-07 11:02 ` [PATCH 15/15] arm/cpu: Add generated files Cornelia Huck
@ 2025-02-07 19:02 ` Richard Henderson
2025-02-10 15:20 ` Cornelia Huck
0 siblings, 1 reply; 29+ messages in thread
From: Richard Henderson @ 2025-02-07 19:02 UTC (permalink / raw)
To: Cornelia Huck, qemu-devel, qemu-arm, kvmarm
On 2/7/25 03:02, Cornelia Huck wrote:
> And switch to using the generated definitions.
>
> Generated against Linux 6.14-rc1.
>
> Signed-off-by: Cornelia Huck<cohuck@redhat.com>
> ---
> target/arm/cpu-sysreg-properties.c | 716 ++++++++++++++++++++++++++++-
> target/arm/cpu-sysregs.h | 116 +----
> target/arm/cpu-sysregs.h.inc | 164 +++++++
> 3 files changed, 860 insertions(+), 136 deletions(-)
> create mode 100644 target/arm/cpu-sysregs.h.inc
Why are we committing generated files and not generating them at build-time?
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 15/15] arm/cpu: Add generated files
2025-02-07 19:02 ` Richard Henderson
@ 2025-02-10 15:20 ` Cornelia Huck
2025-02-18 15:38 ` Eric Auger
0 siblings, 1 reply; 29+ messages in thread
From: Cornelia Huck @ 2025-02-10 15:20 UTC (permalink / raw)
To: Richard Henderson, qemu-devel, qemu-arm, kvmarm
On Fri, Feb 07 2025, Richard Henderson <richard.henderson@linaro.org> wrote:
> On 2/7/25 03:02, Cornelia Huck wrote:
>> And switch to using the generated definitions.
>>
>> Generated against Linux 6.14-rc1.
>>
>> Signed-off-by: Cornelia Huck<cohuck@redhat.com>
>> ---
>> target/arm/cpu-sysreg-properties.c | 716 ++++++++++++++++++++++++++++-
>> target/arm/cpu-sysregs.h | 116 +----
>> target/arm/cpu-sysregs.h.inc | 164 +++++++
>> 3 files changed, 860 insertions(+), 136 deletions(-)
>> create mode 100644 target/arm/cpu-sysregs.h.inc
>
> Why are we committing generated files and not generating them at build-time?
We'd either have to carry a copy of Linux' sysregs file, or generate a
build dependency on Linux. I think we should handle this similar to the
Linux headers update, where we do an explicit update and check for
anything unexpected that might have crept in. (Same applies if we switch
to any other external source for register definitions.)
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH 15/15] arm/cpu: Add generated files
2025-02-10 15:20 ` Cornelia Huck
@ 2025-02-18 15:38 ` Eric Auger
0 siblings, 0 replies; 29+ messages in thread
From: Eric Auger @ 2025-02-18 15:38 UTC (permalink / raw)
To: Cornelia Huck, Richard Henderson, qemu-devel, qemu-arm, kvmarm
Hi,
On 2/10/25 4:20 PM, Cornelia Huck wrote:
> On Fri, Feb 07 2025, Richard Henderson <richard.henderson@linaro.org> wrote:
>
>> On 2/7/25 03:02, Cornelia Huck wrote:
>>> And switch to using the generated definitions.
>>>
>>> Generated against Linux 6.14-rc1.
>>>
>>> Signed-off-by: Cornelia Huck<cohuck@redhat.com>
>>> ---
>>> target/arm/cpu-sysreg-properties.c | 716 ++++++++++++++++++++++++++++-
>>> target/arm/cpu-sysregs.h | 116 +----
>>> target/arm/cpu-sysregs.h.inc | 164 +++++++
>>> 3 files changed, 860 insertions(+), 136 deletions(-)
>>> create mode 100644 target/arm/cpu-sysregs.h.inc
>> Why are we committing generated files and not generating them at build-time?
> We'd either have to carry a copy of Linux' sysregs file, or generate a
> build dependency on Linux. I think we should handle this similar to the
> Linux headers update, where we do an explicit update and check for
> anything unexpected that might have crept in. (Same applies if we switch
> to any other external source for register definitions.)
Yes this was the initial intent, I mean do a manual import from linux
sysreg or any other reliable source such as the JSON dump pointed out by
Marc. That way we are still able to analyze potential breakages.
Eric
>
>
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